TW201115702A - Non-uniform alignment of wafer bumps with substrate solders - Google Patents

Non-uniform alignment of wafer bumps with substrate solders Download PDF

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Publication number
TW201115702A
TW201115702A TW099131158A TW99131158A TW201115702A TW 201115702 A TW201115702 A TW 201115702A TW 099131158 A TW099131158 A TW 099131158A TW 99131158 A TW99131158 A TW 99131158A TW 201115702 A TW201115702 A TW 201115702A
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TW
Taiwan
Prior art keywords
metal
bumps
bump
under
compensation
Prior art date
Application number
TW099131158A
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English (en)
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TWI440149B (zh
Inventor
Hung-Jui Kuo
Chung-Shi Liu
Chen-Hua Yu
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Taiwan Semiconductor Mfg
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Publication of TW201115702A publication Critical patent/TW201115702A/zh
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Publication of TWI440149B publication Critical patent/TWI440149B/zh

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  • Engineering & Computer Science (AREA)
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  • Wire Bonding (AREA)

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201115702 六、發明說明： 【發明所屬之技術領域】 且特別是有關於一種含 集成，以及其製造方法。 本發明係有關於積體電路， 積體電路晶片及封裝基板之封裝 【先前技術】 現今積體電路係形成於半導體晶片上。為了增加 能及降低製造成本’積料路係製造在半導體晶圓中， 籲每-晶圓中含有大量相同的半導體晶片。待積體電路製 造完畢後，自晶圓切割下半導體晶片並將其封裝以作使 用。 在-般封裝製程中，首先將半導體晶片（習知技術 中亦稱為晶粒）貼附（attach)於封裝基材上。此步驟包 含以物理方式將半導體晶片固定於封裝基材上，及將半 導體晶片上之連接墊與封裝基材上之連蜂墊相連接，且 更使用底部填充材料（通常包含環氧樹脂） 人 •固定。半導越晶片之間可使用覆晶連接或 接合。所得之封裝體稱為球柵陣列（ball grid array，BGA ) 模組。可整合許多不同功能的晶片於同一球栅陣列模組 中’以形成系統級封裝（SyStem-in-package )模組。 第1及2圖顯示半導體晶片100封裝至封裝基材11〇 上於各種中間階段之剖面圖。半導體晶片1〇〇包含凸塊 102及其上之助熔劑（flux) 1〇4。封裝基材11〇包含焊 料凸塊112。凸塊102之位置及節距與焊料凸塊112之位 置及節距彼此互相準確對齊。然而，既然封裝基材n〇 〇503-A35015TWF/jeff 201115702 (及/或半導體晶片1〇〇)具有多層不同材料之膜層，焊 料凸塊112可能會因多層結構所產生的應力造成其位置 偏移jpositionshift)(如箭頭114所示）而造成應力產 生於這些疊層巾。位置偏移會造成焊料凸塊n2彼此之 間的節距改變’而與預設值有所差異。因此，如第2圖 所不，當半導體晶片100及封裝基材110互相接合時， 凸塊102及焊料凸塊112未能準確對齊，造成有更多應 力施加至半導體晶片1〇〇,且當某些凸塊1〇2與其所對應 知料凸塊1 1 2元全錯位（fUlly diSalignment )時，可能 會造成短路。 【發明内容】 本發明係提供一種積體電路結構，包括：一第一工 件，擇自由下列組成之群組：一半導體晶片及一封裝基 材，其中此第-工件包含：多個第一凸塊下金屬，分佈 於此第一工件之主要表面上；以及多個第一金屬凸塊， 其中每一第一金屬凸塊直接位於一個此第一凸塊下金屬 上並與其電性連接，其中此多個第一凸塊下金屬及多個 第一金屬凸塊之間的配置係具有一疊對補償，且至少一 邻分的第一凸塊下金屬與其對應之此第一金屬凸塊具有 錯位。 本發明亦提供一種積體電路結構，包括：一半導體 晶片，包含多個第一凸塊下金屬分佈於此半導體晶片之 主要表面上；一封裝基材，包含多個第二凸塊下金屬分 佈於此封裝基材之主要表面上；以及多個含銅凸塊，且 0503-A3 5015TWF/jeff 4 201115702 每一含銅凸塊透過焊接方式與此多個第一凸塊下金屬或 此多個第二凸塊下金屬其中一者電性連接， 接方式與另-者電性連接’且其中此多個含鋼== 多個第一凸塊下金屬或此多個第二凸塊下金屬之間具有 一疊對補償。 〃 本發明更提供一種積體電路結構，包括··一半導體 晶片及一封裝基材，包含：多個凸塊下金屬分佈於此 半導體晶片之主要表面上；以及多個金屬凸塊，其中至 馨少-部分之多個凸塊下金屬與其下方所對應之金屬凸塊 曰位且其中罪近此半導體晶片中央之金屬凸塊與其下 方所對應之金屬凸塊之錯位較遠離此半導體晶片 金屬凸塊大。 、 為讓本發明之上述和其他目的、特徵、和優點能更 月,4易懂，·下文特舉出較佳實施例，並配合所附圖式， 作詳細說明如下： ’ • 【實施方式】 本發明接下來將會提供許多不同的實施例以實施本 發明中不同的特徵。然而，這些實施例並非用於限定本 月以下所5寸論之特定貫施例僅用於舉例本發明實施 例之製造及使用，但不限定本發明之範實 在此，將揭示依照本發明實施例製造積體電路之新 穎方法，及將舉例—實施例於製造時之各種中間階段， 並將討論此實施狀各種變化。在本發明所舉例之各種 圖不及實施例中’相似參考標號代表相似元件。 〇503-A35015TWF/jeff 201115702 第3A圖顯示半導體晶片10及封裝基材4〇之剖面 圖。可知的是，所顯示之半導體晶片1〇及封裝基材4〇 在同一平面中僅是用於舉例及比較，其事實上為分開的 元件。封裝基材40已製造完畢，而半導體晶片丨〇之凸 塊尚未形成。半導體晶片10可包含半導體基材u及積 體電路裝置（未顯示），例如形成電晶體於半導體基材 11表面上。半導體晶片1〇亦可為翹曲的（warpage)。 金屬連接元件12 (標記為12一 1、12_2)，可為形成於半 導體晶片ίο表面上之凸塊下金屬（under bump metallurgies，UBMs)或連接墊。凸塊下金屬12」、i2」 之間的節距（pitch) $ pi。圖示中兩元件之間的節距係 由兩7L件之中央開始量測，或亦可量測相對應的側邊。 封裝基材40包含金屬繞線（r〇uting metai )及通孔 (未顯示），其可電性連接封巧基材40 —側之悍料凸塊 44 (私β己為44_1、44_2 )至另一相反側。封裝基材4〇更 包含金屬連接元件（metallic connections) 42 (標記為 42一 1、42—2) ’其可為凸塊下金屬或連接墊。焊料凸塊 44形成於凸塊下金屬42上，在凸塊下金屬^ }、们 之間的節距為P1，。 一 — 3八圖步驟中，凸塊…4-2'未顯示於第 月> S 6及7圖）各自形成於凸塊下金屬12」 442—ί上二以各自與凸塊44-卜44-2接合。因此，凸塊 之間所預設的節距（其可能會與凸塊下金屬 節距Ρ!，相Π之間的節距相同）與凸塊14-1、14-2之間的 然而，由於封裝基材40 (或可能是半導 〇503-A35015TWF/jeff 201115702 體晶片1 ο)中因材料不同而導致的應力（例如不同材料 層之熱膨脹係數的差異），封裝基材40及/或半導體晶片 10可能是歪曲的（distorted)，例如彎曲（bent)，造成 節距ΡΓ與預設值有所差異。因此，在第3圖中，=距 P1與節距P1，不同。在本說明書中，詞彙“歪曲，，用於指稱 凸塊之位置及節距的改變，其中歪曲可包含位置的偏 移、旋轉、及/或任何其他三級扭曲（third_〇rder) (非規則性的扭曲）。為了舉例說明，凸塊下金屬i2間 之節距P1小於凸塊44間之節距P1，，然而其他實施二 中，節距pi可大於或小於節距P1，。第3B圖顯示第3a 圖所不結構之俯視圖。此俯視圖顯示半導體晶片可包 含多個凸塊下金屬42,及封裝基材4G可包含多個凸塊 44。第3A圖之剖面圖來自於第3B圖中沿線段3a_3a之 剖面。 在一實施例中’纟完成封裝基材40之製造後，量測 凸塊料間的節距（例如節距pr)。所量測的節距可盘 凸塊節距之預設值比較（預設與節距ρι相同）以判斷凸 塊44的位置歪曲程度。接著，形成凸塊U (在第5至7 圖中標記為凸塊14 1、14 2)以蚀f門— ， - -2)以使其間之卽距與所量測 二曝相同。第4圖所示之製造步驟顯示對光阻 :二：16亦可由其他罩幕層來替代，例如乾 二=爾，所舉例之光阻16形狀是在曝光及 m:非僅進行曝光時之形狀。光阻16定義 出凸塊14之圖案及位置（第6及7圖 使用微影罩幕18來對光 實Μ·]中， 尤阻16進仃曝光，此微影罩幕18 〇503-A35015TWF/jeff *7 201115702 包含可使光穿透之透明圖案及阻擋光之不透明圖案。此 微影罩幕18之圖案不會考慮封裝基材4〇中歪曲的凸 塊。因此’所定義之凸塊14之圖案間的節距仍為pi。 為了確保直接形成在凸塊下金屬12一1、12_2上之凸 塊對齊凸塊44一1、44_2,欲形成在凸塊下金屬12j、12 2 上之凸塊需具有節距P1，。因此，在對光阻16進行曝光 時，於此曝光步驟中施予疊對補償（overlay〇ffset)，其 中疊對補償（標記為傾斜箭頭20)係由進行曝光之裝置 來進行’例如圖示所舉例之步進曝光機台（stepper) 22。 此疊對補償使曝光後之光阻16具有與微影罩幕之節距 P1不同的節距p 1 ’。如未施予疊對補償，光阻16中的開 口邊界將位在如16’所示之位置。如節距pi’大於節距 P1 ’疊對補償將造成圖案擴張（尺寸縮放（scaling)的 一種）。在其他實施例中，依照凸塊44的位置歪曲程度， 可，調整步進曝光機台22以使疊對補償造成光阻16中的 曝光圖案縮小、旋轉及/或其他三度空間之扭曲。 參見第5圖，由例如電鍍形成凸塊14(標記為丨.4」、 14_2)。凸塊14可由鑛銅（plated copper)形成，且更 可包含鍍鎳層（未顯示）於此鍍銅層上。再者，亦可形 成一電鍍焊料薄層（未顯示）於此鍍鎳層上。在形成凸 塊14之後，移除光阻16,最終結構如第6圖所示。可知 的是’由於疊對補償’凸塊14及凸塊44具有相同的節 距P1’，因此凸塊14及凸塊44的接合可無任何錯位。此 外，更可觀察到凸塊14與其所對應之下方的凸塊下金屬 12無任何錯位。 0503-A35015TWF/jeff 8 201115702 凸塊第用示本發明另一實施例’其中凸塊14為焊料 14時，:代第5及6圖之銅凸塊。在形成焊料凸塊 ί 施予疊對補償來定義焊料凸塊14 胃 此疊對補償可在㈣阳、叶塊Μ的位置。 光阻可為用進行圖案化時施予， 凰:圖案化介電層24之光阻。藉此，凸塊下金 14接合。齡疊對補償的細節基本 别述，故在此不再重複贅述。
Π)二二第3至7圖之步驟製造之半導體晶片 〇之，視圖。為了顯Μ對補㈣效果，以實線所示之 =案為經過疊對補償之圖案，且為經上述步驟製造之圖 >、。以虛線圓®所示之圖案為不經疊對補償之圖案，且 此圖案僅為微影罩幕18之圖案（第4圖）。虛線圓圈之 位置亦為凸塊下金屬12之位置。值得注意的是，凸塊Μ 間的節距在在X方向上具有尺寸補償。 第9圖顯示半導體晶片1〇與封裝基材如之接合。 隨著在形成凸塊14時施予疊對補償，凸塊14準確^齊 其所對應之凸塊44。在形成如第9圖所示之結構後，在 凸塊44及/或14中的焊料迴流以形成封裝總成。 第10圖顯示本發明另一實施例之剖面圖，其中不僅 對半導體晶片10施予疊對補償’且對封裝基材4〇施予 額外的疊對補償。在此實施例中’結合形成凸塊14時之 疊對補償及形成凸塊44時之額外的疊對補償，可以抵鎖 半導體晶片10及封裝基材40之間的位置/節距的差異， 因此凸塊14及44可互相對齊。凸塊44可具有與凸塊14 相同或不同的結構’用於施予疊對補償至凸塊44之製 0503-A35015TWF/jeff 9 201115702 程，基本上與前述相同。值得注意的是，對於凸塊14之 疊對補償（標記為箭頭26 )及對於凸塊44時之疊對補償 (標記為箭頭56所示）為相反（inversed)的。亦即， 如疊對補償26是使凸塊14間的節距增加，則疊對補償 56是使凸塊44間的節距縮短，反之亦然。 第Π及第12圖顯示另兩種可能之實施例。第u圖 顯以二維的疊對補償形成凸塊14,其對半導體晶片1〇(或 封裝基材40)之X及Y方向施予疊對補償。再者，可能 會發生凸塊14及44之錯位需要旋轉凸塊14及/或44凸 塊之情況。第12圖顯示之實施例中，對凸塊14及/或44 施予疊對補償，使其相較於其所預設之位置及相較於其 下方元件（例如凸塊下金屬12)的方向有所旋轉。 可知的是，仍有多種變化例可用以實施本發明之實 施例。例如，可在形成凸塊14及/或44時施予疊對補償， 但不對例如凸塊下金屬12及/或42之下層戈件 (underlying features)施予疊對補償，以使製造成本得 以降低。然而，在另一實施例中，可在形成一或多個例 如凸塊下金屬12及/或42之下層元件時施予疊對補償， 然所剩餘的下層元件不施予任何疊對補償。在又一實施 例中，可結合各種疊對補償，例如擴展、縮減、旋轉及 二級扭曲’以使凸塊14及凸塊44儘可能的對齊。 疊對補償可施予至整個在晶圓中的全部晶片或僅施 予至晶圓中的部分晶片。當使用步進曝光機.台22 (參見 第4圖）以曝光光阻16時，在同一晶圆中的每一半導體 晶片10皆需曝光。因此，為了對每一半導體晶片1〇進 0503-A35015TWF/jeff 201115702 =行晶片進行疊對補償，或對全部 多個曰片m ^ 13至15圖更顯示對同一晶圓中 B曰圓2中之半導體晶片1〇 圃π 晶片中形成凸塊14(未頻干）度“目同，且在全部 (稱為位置轉移）。在二:）時皆施予相同的疊對補償 置轉移）。在第14圖巾，晶圓2 =10具有不同的旋轉的歪曲，靠近晶圓2中央的S片相 ”曰曰圓2中央的晶片具有較小的旋轉的歪曲。因 導體ί二稱且？轉補償。在第15圖中，晶圓2中的半 片告1〇具有不同的偏移的歪曲，靠近晶圓2中央的 :^遠離晶圓2中央的晶片具有較小的移位歪曲⑽ 曰圓0V二日。，此，進行對稱的尺寸調整，以使對靠近 :固中央的晶片施予較小的疊對補償，而對遠離晶圓中 央的晶片施予較大的疊對補償。 本發明具有眾多優點，例如可消除半導體晶片上及 上凸塊不對齊的情況，且此解決方法不需增加 k成本’既然其僅包含進行—測量步驟’剩餘步驟均 可由步進曝光機台自動化完成。 雖然本發明已以數個較佳實施例揭露如 .» jo …、六 jlil 非用以限疋本發明，任何所屬技術領域中具有通常知識 者，在不脫離本發明之精神和範圍内，當可作任意之更 動與潤飾’因此本發明之賴範圍當視後附之申^專利 範圍所界定者為準。此外，熟知本領域技藝人士將可依 照本發明所揭示之現有或未來所發展之特定程序、機 器、製造、物質之組合、功能、方法或步驟達成相同的 〇503_A35015丁 WF/jeff 201115702 功能或相同的結果。因此本發明之保護範圍包含這些程 序、機器、製造、物質之組合、功能、方法或步驟。再 者，每一申請專利範圍皆可視為建構一單獨的實施例， 且各申請專利範圍及實施例之結合皆在本發明之範圍 中。 0503-A35015TWF/jefF 12 201115702 【圖式簡單說明】 第1及2圖顯示傳統接合製程接合半導體晶片及封 裝基材於各種中間階段之剖面圖； 第3A至7顯示依照本發明實施例凸塊製造於各種中 間階段之俯視圖及剖面圖； 第8圖顯示半導體基材之俯視圖，其中所凸塊使用 疊對補償形成； 第9圖顯示接合半導體晶片及封裝基材； • 第10圖掩飾半導體晶片及封裝基材之剖面圖，其中 半導體晶片及封裝基材之凸塊皆使用疊對補償形成； 第11圖顯示半導體晶片之俯視圖，其中凸塊在X及 Y方向皆使用疊對補償； 第12圖顯示半導體晶片之俯視圖，其中在形成凸塊 時施予疊對補償使其旋轉；
第13圖顯示疊對補償使用於整個晶圓上的導 片，其中凸塊位置整體轉移； BB • 第14圖顯示叠對補償使用於整個晶圓上的半導㉟曰 片’其中凸塊位置整體旋轉； 曰曰 第15圖顯示疊對補償使用於整個晶圓上的半導體晶 片’其t凸塊位置整體偏移。 曰曰 【主要元件符號說明】 凸塊下金屬； 2〜晶圓； 11〜半導體基材； U—l〜凸塊下金屬； 10〜半導體晶片； 12〜凸塊下金屬； 12 2〜凸德下各屈 0503-A350I5TWF/jeff 13 201115702 14〜凸塊； 14_1〜凸塊； 14_2〜凸塊； 16〜光阻； 16 ’〜開口邊界； 18〜微影罩幕； 20〜疊對補償； 22〜步進曝光機台； 24〜介電層； 26〜疊對補償； 40〜封裝基材； 42_1〜凸塊下金屬； 42_2〜凸塊下金屬； 44〜凸塊； 44_1〜凸塊； 44_2〜凸塊； 56〜疊對補償； 100〜半導體晶片； 102〜凸塊； 104〜助溶劑； 110〜封裝基材； 112〜焊料凸塊； 114〜偏移； P1 ’〜節距。 P1〜節距； 0503-A35015TWF/jeff 14

Claims (1)

  1. 201115702 七、申請專利範圍： 1. 一種積體電路結構，包括： 一第一工件，擇自一半導體晶片 成之群組，其中該第一工件包含： 多個第一凸塊下金屬，分佈於該第 面上；以及 多個第-金屬凸塊，其中每一第一金屬凸塊直接位 於-個該第-凸塊下金屬上並與其電性連接 第：Γ屬及該些第一金屬凸塊之間的配置係 -且對仙，且至少一部分的第一凸塊 之該第-金屬凸塊具有錯位。 胃 2. 如專利範圍第1項所叙龍電路結構 ，補償包含尺寸補償’該些第一金屬凸塊具有第一 ^其所對應的第—凸塊下金屬具有與 不同之第二節距。 即此談疊=了41利範圍第1項所述之積體電路結構，其中 二:广旋轉補償，該些第-凸塊金屬配置於相 對於該些[凸塊下金屬麵旋狀位置。 4如申請專㈣㈣w所述 靠=第-工件中央之金屬凸塊與路對。構:： -金屬凸塊之錯位較遠離該第一工件中央之金： 一封裝基材所組 工 件之主要表 大 含 :如申請專利範圍第i項所述之積體電路結構，更包 一第二工件，其中該第 〇503-A35015TWF/jeff 工 件與該第一工件透過該 15 201115702 些第一金屬凸塊接合，且其中 凸塊下金屬，且每一該第二凸塊 包含多個第二 塊金屬接合， 凸塊下金屬與一個該第一凸 产 一 ’ /、k二第一金屬凸塊具有額外的聶f+補 償，且每一第一金屬凸塊 二額：：疊對補 齊。 f應之第一金屬凸塊對 6.一種積體電路結構，包括·· 凸塊下金屬分佈於該 一半導體晶片，包含多個第一 半導體晶片之主要表面上； 巴言夕個第 裝基材之主要表面上；_以及〜塊下金屬分佈於該封 此第夕二1銅凸塊’且每―含銅凸塊透過料方式與該 2 一凸塊下金屬或該些第二凸塊下金屬其卜者電性 連接，並透過非焊接方式與另一者電性連接，且苴”亥 與:些第一凸塊下金屬或該些第二凸塊下金 屬之間具有一疊對補償。 7’如申明專利範圍第6項所述之積體電路結構，其中 該疊對補償介於該些含銅凸塊及該些第—凸塊下金屬、之 間或介於該些含銅凸塊及該些第二凸塊下金屬之間。 8. 如申請專利範圍第6項所述之積體電路結構，更包 含一額外的疊對補償介於該些卜及第二凸塊下金屬兩 者之剩餘未有疊對補償者與該些含銅凸塊之間。 9. 一種積體電路結構，包括 一半導體晶片及一封裝基材，包含： 0503-A350I5丁 WF/jeff 16 201115702 ::凸塊下金屬’分佈於該半導體晶片之主要表面 ,以及 與二:塊中至少-部分之多個凸塊下金屬 = 屬凸塊錯位，且其甲靠近該半導體 曰曰片中央之金屬凸塊與其下方所對應之金 較遠離該半導體晶片中央之金屬凸塊大。兔之錯位
    中^0trrr範圍第9項所述之積體電路結構，其 屬凸塊以一第一尺寸為節距分佈 ： :.如申請專利範圍第9項所tr體為電^4佈里 中該些金屬凸塊相對於該些凸塊下金屬有所旋轉，。異
    17 0503-A35015TWF/jeff
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