201115694 • 六、發明說明： 【發明所屬之技術領域】 種具線 ，. 本發明係有關—種封裝基板及其製法，尤指 路層之封裝基板及其製法。 【先前技術】 . 4符合封裝件輕薄短小、多功能、高速度及高頻化的 開發方向，目前封裝基板已朝向細線路及小孔徑發展。於 二般_電祕或龍基板巾之金屬層職線路圖宰化之 E線:料=為經常使用之方式，尤以 Γ之㈣絲’於龍敍量產製^ • :?.木帛。但知用濕麵刻往往會產生飯刻底切之問題， 故為避免餘刻之底切問題，且無法製造具肴更細小之線寬 線距線路，遂有圖案轉移（patterning)製程之發展。 请芩閱第1A至1D圖，其係為習知封裝基板之圖案 轉移製法示意圖。如第lA圖所示，在/雙面具有銅箔1〇£ 魯之基板本體1〇中形成複數通孔，並於該銅箔i〇a及 該些通孔100a之孔壁上形成導電層u，再於該導電層Π 上形成係為乾膜之阻層12，且該阻詹12中形成複數開口 區120，以外露出部分之導電層η表面。再如第iB圖所 示，於各該開口區120中之導電層η上電鑛形成線路層 13 ’並於該些通孔1 〇〇a中形成導電通孔1〇〇。如弟ic圖 所示，剝除該阻層12。最後，如第ip圖所示，蝕刻移除 被前述阻層12所覆蓋之導電層u與銅箔l〇a，以露出電 性連接該導電通孔之線路層13。 111378 201115694 惟，上述之習知技術係藉由該阻層12之曝光、顯影 以形成圖案化開口區120’再於该開口區120中之導電層 11上電鍍形成圖案化之線路層13。由於電鍍形成線路層 13之後，需依序剝除該阻層12、導電層11及銅箔10a， 在移除該阻層12、導電層11及銅箔10a之蝕刻製程，往 往會破壞該線路層13之外形，除會影響線路層13之外形 外，而無法達到預設之電性要求，且易造成斷路，導致習 知線路層13之良率降低。 另外，若加寬該阻層12之開口區120，以令該線路層 13之線寬增加，雖可避免該線路層13之外形於蝕刻移除 該導電層11與銅箔10a時受破壞而造成斷路，但因線路層 13之線寬加大，卻反而會導致無法滿足細間距之線路的需 求。 因此，如何避免習知技術中上述之種種問題，實已成 目前亟欲解決的課題。 【發明内容】 鑑於上述習知技術之種種缺失，本發明之一目的係提 供一種能提高線路成型良率之封裝基板及其製法。 本發明之又一目的係提供一種適用於設計細間距線 路之封裝基板及其製法。 為達上述及其他目的，本發明揭露一種封裝基板，係 包括：基板本體，該基板本體具有兩相對之表面；以及第 一線路層，係設於該基板本體之至少一表面上，該第一線 路層係為化鍍金屬材所形成，且於該基板本體與第一線路 111378 201115694 層之間復具有一導電層，而該第一線路層係完整包覆該導 . 電層之上表面及側表面。 依上所述之封裝基板，該基板本體可為兩相對表面具 有銅箔的銅箔基板（CCL)，且該第一線路層係完整包覆 該銅箔之側表面、導電層之侧表面及上表面。 前述之封裝基板中，該基板本體具有複數貫穿該兩表 面之導電通孔，令該些導電通孔電性連接設於該兩表面上 之第一線路層，較佳地，該導電通孔係如化鍍金屬材所形 籲成者。 前述之封裝基板復包括絕緣保護層，係設於該基板本 體及第一線路層上，該絕緣保護層並具有複數絕緣保護層 開孔，以令各該第一線路層之部分表面外露於各該絕緣保 護層開孔，俾供作為電性接觸墊。 以具有電性接觸墊為需求，前述之封裝基板復包括表 面處理層，係設於各該電性接觸墊上，且形成該表面處理 φ 層之材料係選自由電鍍鎳/金、電鍍銀、電鍍錫、化鎳浸金 (ENIG)、化錄把浸金（ENEPIG)、化學鑛錫（Imnlersion Tin)、化學金、化學銀及有機保焊劑（OSP)所組成之群組 中之其中一者。 本發明復揭露一種封裝基板之製法，係包括：提供一 基板本體，係具有兩相對之表面；於該基板本體之表面上 形成導電層；於該導電層上形成阻層，且該阻層中形成複 數開口區，以外露出該導電層之部分表面；移除各該開口 區中之導電層，以令該基板本體之表面外露出各該開口 5 111378 115694 區 層；^及於該基板本體之導電層上化鐘形成 :而該第-線路層係完整包覆該導電層之上表 的輞中，該基板本體係為兩相對表面具有銅箔 教移除且於移除各該開口區中之導電層時， 矛、。乂導電g所覆蓋之 一 〜側表面、導電層之側表面層— 之通：述基板本體可具有複數貫穿該兩表面 形成第-料^電層復形成於該些觀之孔壁上，且當 从電性連接設於孔中化錢形成導電通孔， 义、兩表面上之苐一線路層。 成絕：：:：法，包括於該基板本體及第-線路層上形 孔，以令各^楚一緣保護層並具有複數絕緣保護層開 層開孔:魏分表面外露於各該絕緣保護 電性:求，前述之製法復包括於各該 _墊形成表面處理層，且形成該表面處理層之材 艸係選自由電鐘鎳/金、電鍍銀、電錄錫、化錄浸金 t(ENIG)、化鎳！巴浸金（ENEPIG)、化學鍍錫（iminersi〇n201115694 • VI. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a package substrate and a method of manufacturing the same, and more particularly to a package substrate of a road layer and a method of manufacturing the same. [Prior Art] . 4 In line with the development direction of light and thin package, multi-function, high speed and high frequency, the package substrate has been developed towards thin lines and small apertures. The second line of the metal layer of the electric secret or the dragon substrate towel is the E line of the slaughtering line: material = the way of frequent use, especially the 四 ( (4) silk 'Yu Long 量 production system ^ : :?. 帛. However, knowing that the wet surface engraving often causes the problem of undercutting, so in order to avoid the problem of the undercut of the engraving, and it is impossible to manufacture a line with a fine line width and a wide line spacing, there is a development of a patterning process. . Please refer to Figures 1A to 1D, which are schematic diagrams of a pattern transfer process of a conventional package substrate. As shown in FIG. 1A, a plurality of via holes are formed in the substrate body 1 / having a double-sided copper foil, and a conductive layer is formed on the copper foil i〇a and the hole walls of the through holes 100a. Then, a resist layer 12 which is a dry film is formed on the conductive layer ,, and a plurality of open regions 120 are formed in the resist 12 to expose a portion of the surface of the conductive layer η. Further, as shown in the iB, the conductive layer n in each of the open regions 120 forms a wiring layer 13' and forms a conductive via 1 in the vias 1a. The resist layer 12 is stripped as shown in Figure ic. Finally, as shown in the ip diagram, the conductive layer u and the copper foil 10a covered by the resist layer 12 are removed by etching to expose the wiring layer 13 electrically connected to the conductive via. 111378 201115694 However, the above-mentioned conventional technique forms a patterned circuit layer 13 by electroplating and developing the resist layer 12 to form a patterned opening region 120' and then plating on the conductive layer 11 in the opening region 120. After the circuit layer 13 is formed by electroplating, the resist layer 12, the conductive layer 11 and the copper foil 10a are sequentially stripped, and the etching process for removing the resist layer 12, the conductive layer 11 and the copper foil 10a often destroys the line. The shape of the layer 13 is not only affected by the shape of the circuit layer 13, but also cannot meet the preset electrical requirements, and is easy to cause an open circuit, resulting in a decrease in the yield of the conventional circuit layer 13. In addition, if the opening region 120 of the resist layer 12 is widened to increase the line width of the circuit layer 13, the circuit layer 13 can be prevented from being damaged when the conductive layer 11 and the copper foil 10a are removed by etching. The circuit is broken, but the line width of the circuit layer 13 is increased, but the demand for the fine pitch line cannot be met. Therefore, how to avoid the above-mentioned various problems in the prior art has become a problem that is currently being solved. SUMMARY OF THE INVENTION In view of the above various deficiencies of the prior art, it is an object of the present invention to provide a package substrate capable of improving the line forming yield and a method of manufacturing the same. Another object of the present invention is to provide a package substrate suitable for designing fine pitch lines and a method of fabricating the same. To achieve the above and other objects, the present invention provides a package substrate, comprising: a substrate body having two opposite surfaces; and a first circuit layer disposed on at least one surface of the substrate body, the first The circuit layer is formed by a metallization material, and has a conductive layer between the substrate body and the first line 111378 201115694 layer, and the first circuit layer completely covers the upper surface of the conductive layer and Side surface. According to the package substrate, the substrate body may be a copper foil substrate (CCL) having copper foil on opposite surfaces, and the first circuit layer completely covers the side surface of the copper foil, the side surface of the conductive layer, and Upper surface. In the above package substrate, the substrate body has a plurality of conductive vias penetrating the two surfaces, and the conductive vias are electrically connected to the first circuit layer disposed on the two surfaces. Preferably, the conductive vias are Such as the formation of metallized metal. The package substrate further includes an insulating protective layer disposed on the substrate body and the first circuit layer, and the insulating protective layer has a plurality of insulating protective layer openings, so that a part of the surface of each of the first circuit layers is exposed The insulating protective layer is opened and used as an electrical contact pad. The above-mentioned package substrate includes a surface treatment layer, which is disposed on each of the electrical contact pads, and the material forming the surface treatment φ layer is selected from the group consisting of electroplated nickel/gold, electroplated silver, and electroplating. One of a group consisting of tin, nickel immersion gold (ENIG), immersion gold (ENEPIG), chemical tin (Imnlersion Tin), chemical gold, chemical silver, and organic solder resist (OSP). The invention discloses a method for manufacturing a package substrate, comprising: providing a substrate body having two opposite surfaces; forming a conductive layer on a surface of the substrate body; forming a resist layer on the conductive layer, and the resist layer Forming a plurality of open areas, exposing a portion of the surface of the conductive layer; removing the conductive layer in each of the open areas to expose the surface of the substrate body to the opening 5 111378 115694; and the substrate body The conductive layer is formed on the clock: and the first circuit layer completely covers the upper surface of the conductive layer, the substrate is provided with copper foil on both opposite surfaces to be removed and removed in each of the open areas When the conductive layer is used, the spear. One of the side surfaces of the conductive layer g, the side surface layer of the conductive layer, and the side surface layer of the conductive layer: the substrate body may have a plurality of layers formed through the two surfaces and formed on the wall of the plurality of holes. When the electrical connection is made in the hole to form a conductive through hole, the circuit layer on the two surfaces is defined. The method of forming a :::: method comprises: forming a hole on the substrate body and the first layer of the circuit layer, so as to have a protective layer of a plurality of insulating layers and opening openings of the plurality of insulating layers: the surface of the Wei is exposed to each of the insulating layers Protective electric property: The above method is included in each of the mats to form a surface treatment layer, and the material forming the surface treatment layer is selected from the group consisting of electric clock nickel/gold, electroplating silver, electro-recording tin, chemical recording immersion gold t (ENIG), nickel! ENEPIG, electroless tin plating (iminersi〇n
Tln)、化學金、化學銀及有機保焊劑(〇sp)所組成之群組 中之其中一者。 由上可知，本發明藉由該阻層之曝光、顯影形成圖案 匕開口區，再移除該開口區中之導電層，以形成圖案化之 導電層，再化鍍金屬於保留下之導電層上，相較於習知技 111378 6 201115694 術 …本發明不需於該開-=丨电毅缘 略所需之金Μ从,, 可避免移除該阻層時破壞該線路外形之情兄工喝材，故 鍍形成第一線路層後不需再蝕刻，因而^ ' 且本發明化 俾有效提高線路成型之良率，且持線路原形’ 【實施方式】 <線路。 以下藉由特定的具體實施例說明本 式，熟悉此技藝之人士可由本說明蚩 只&方 所揭不之内容輕易地 瞭解本發明之其他優點及功效。One of a group consisting of Tln), chemical gold, chemical silver, and organic solder resist (〇sp). It can be seen from the above that the present invention forms the pattern opening region by exposure and development of the resist layer, and then removes the conductive layer in the open region to form a patterned conductive layer, and then metallizes the remaining conductive layer. Compared with the conventional technology 111378 6 201115694, the present invention does not need to be used for the opening and closing of the circuit layer. After drinking the material, it is not necessary to etch after forming the first circuit layer, and thus the sputum of the present invention effectively improves the yield of the line forming, and holds the original shape of the line. [Embodiment] < In the following, the present invention will be described by way of specific examples, and those skilled in the art can readily appreciate other advantages and effects of the present invention from the description and the disclosure.
請參閱第2Α至2Η圖，係為本發明所揭露之 裝基板之製法。 3 如第2Α圖所示，提供一基板本體2〇,且該基板本體 2〇係為mi基板（CCL)，即該基板本體2Q之兩相對表 面具有銅箔20a之核心板。或者，亦可如第2A，圖所示， 該基板本體2G為兩相對表面不具有域之承載板或介電 層；然，有關基板之種類繁多，且為業界所熟知，例如内 部具有線路之基板等，並不以上述之基板為限，特此述明。 如第2B圖所示，於該基板本體2〇中形成複數貫穿該 兩表面之通孔200a。 如第2C圖所示’於該基板本體2〇之兩表面的銅箔 20a及該些通孔2〇〇a之孔壁上形成導電層21。 如第2D圖所示，於該導電層21上形成阻層22，且 該阻層22中形成複數開口區22〇，以外露出該導電層21 之部分表面。所述之阻層22係為一例如乾膜或液態光阻等 光阻層（Photoresist)，其係利用印刷、旋塗或貼合等方式形 7 111378 201115694 成於該導電層2i上，再藉由曝光、顯影等方式加以圖宰 化，以於該阻層22中形成圖案化開口區220,而外露出^ 份之導電層21。 如第2E圖所示，移除各該開口區22〇中之導電層2ι 及其所覆蓋之銅羯20a ’以令該基板本體2〇之部份表面外 露於各該開口區220。 如第2F圖所示，移除該阻層22，以外露出該基板本 體20之部份表面及導電層21。 如第2G圖所示，於該基板本體2〇之導電層21上化 鑛鋼材（electroless copperplating)以形成第—線路層^ 且於各該通孔200a之導電層21上化鍍銅材而形成導電通 孔200,俾令該些導電通孔200電性連接該基板本體 兩表面上的第一線路層23。 本發明藉由該阻層22之曝光、顯影以形成圖案化開 口區220 ’再移除該開口區220中之導電層21，以形成圖 案化之導電層21，再經由化鍍金屬於保留下之導電層u 上，相較於習知技術之先電鍍金屬再移除導電層，由曰於本 發明不需於該開口區220中形成電鑛線路所需之金屬材， 故可避免移除該阻層22時破壞該第—線路層23 況，且本發明化鑛形成第一線路層23❹需再餘刻1 ^ 可保持線路之設計原形，俾有效提高線路成型之良率，且 易於設計成細間距之線路。 如第2H圖所示，於該基板本體2〇及第一線路層y 上形成絕緣保護層24，該絕緣保護層24中並形成複^Please refer to Figures 2 to 2 for the fabrication of the substrate as disclosed in the present invention. 3 As shown in Fig. 2, a substrate body 2 is provided, and the substrate body 2 is a mi substrate (CCL), that is, the opposite surface of the substrate body 2Q has a core plate of copper foil 20a. Alternatively, as shown in FIG. 2A, the substrate body 2G is a carrier or dielectric layer having no domains on opposite surfaces; however, there are many types of related substrates, and are well known in the industry, for example, having internal wiring. The substrate and the like are not limited to the above-described substrate, and thus will be described. As shown in Fig. 2B, a plurality of through holes 200a penetrating the both surfaces are formed in the substrate body 2''. As shown in Fig. 2C, a conductive layer 21 is formed on the copper foil 20a on both surfaces of the substrate body 2 and the hole walls of the through holes 2A. As shown in Fig. 2D, a resist layer 22 is formed on the conductive layer 21, and a plurality of open regions 22a are formed in the resist layer 22, and a part of the surface of the conductive layer 21 is exposed. The resist layer 22 is a photoresist layer such as a dry film or a liquid photoresist, which is formed on the conductive layer 2i by printing, spin coating or lamination. The patterning is performed by exposure, development, etc., so that the patterned opening region 220 is formed in the resist layer 22, and the conductive layer 21 is exposed. As shown in Fig. 2E, the conductive layer 2i in each of the open regions 22 and the copper pads 20a' covered therein are removed to expose a portion of the surface of the substrate body 2 to each of the open regions 220. As shown in Fig. 2F, the resist layer 22 is removed, and a part of the surface of the substrate body 20 and the conductive layer 21 are exposed. As shown in FIG. 2G, an electroless copper plating is formed on the conductive layer 21 of the substrate body 2 to form a first wiring layer, and a copper material is formed on the conductive layer 21 of each of the via holes 200a. The conductive vias 200 electrically connect the conductive vias 200 to the first wiring layer 23 on both surfaces of the substrate body. In the present invention, the conductive layer 21 in the open region 220 is removed by exposure and development of the resist layer 22 to form a patterned opening region 220' to form a patterned conductive layer 21, which is then retained by metallization. On the conductive layer u, the conductive layer is removed by electroplating the metal compared with the prior art. Since the metal material required for the electric ore line is not required to be formed in the open region 220, the removal of the metal layer can be avoided. When the resist layer 22 breaks the condition of the first circuit layer 23, and the first circuit layer 23 is formed by the chemical ore of the present invention, it is necessary to maintain the original design of the line, thereby effectively improving the yield of the line forming, and is easy to design. Fine pitch lines. As shown in FIG. 2H, an insulating protective layer 24 is formed on the substrate body 2 and the first wiring layer y, and the insulating protective layer 24 is formed in the same manner.
S 111378 201115694S 111378 201115694
緣保護層開孔240，以令該第一線路層A < °卩分表面休命 於各該絕緣保護層開孔240，俾供作為電性接觸墊 卜路 依上所述，亦可在形成該絕緣保護層24 ^ "^月’曹乂包 釗述步驟以形成具有複數線路層的增層4士播「+ 夂 °偁（未以圖式异 示），並於該增層結構之最外層形成絕緣保護層、 另外:可於各該電性接觸塾23G上形=面處理層 25 ’且形成該表面處理層25之材料係選自由電贫鎳/金 電鍍銀、電鍍錫、化鎳浸金（ENIG )、彳μ力自* J 化螺纪浸金 (ENEPIG)、化學鍍錫（lmmersion Tin)、化尊金 學銀及有機保劑（OSP)所組成之群组中之其中—者, 如第2H’圖所示，係第2H圖之另—態樣，即該基板 本體20為兩相對表面不具有銅箔之承載板或介電層的情 況’其製法與上述相同，故在此不加以贅述。 本發明復揭露一種封裝基板，係包括：基板本體2〇， 該基板本體具有兩相對之表面、以及設於該基板本體如 φ表面上之第一線路層23,該第一線路層23係為化鍍金屬 材所形成，且於該基板本體20與第一線路層23之間復具 有一導電層21，而該第一線路層23係完整包覆該導電層 21之上表面及側表面。 於上述之封裝基板中，該基板本體20可為兩相對表 面具有銅箔20a的銅箔基板（CCL)，且該第一線路層23 係完整包覆該銅箔20a之側表面、導電層之側表面及上 表面。 所述之基板本體20具有複數貫穿兩表面之導電通孔 111378 9 201115694 200,以藉該些導電通孔200電性連接設於該兩表面上之第 一線路層23，且各該導電通孔200係為該化鍍金屬材所形 成者。 所述之封裝基板復包括絕緣保護層2 4，係設於該基板 本體20及第一線路層23上，該絕緣保護層24並具有複數 絕緣保護層開孔240,以令各該第一線路層23之部分表面 外露於各該絕緣保護層開孔240，俾供作為電性接觸墊 230。 所述之封裝基板復包括表面處理層25,係設於各該電 性接觸墊230上，且形成該表面處理層25之材料係選自由 電鍍鎳/金、電鍍銀、電鍍錫、化鎳浸金（ENIG)、化鎳 名巴浸金（ENEPIG)、化學鑛錫（Immersion Tin)、化學 金、化學銀及有機保焊劑（OSP)所組成之群組中之其中一 者。 综上所述，本發明藉由該阻層之曝光、顯影形成圖案 化開口區，再移除該開口區中之導電層，以化鍍金屬於保 留下之導電層上，而製作出第一線路層；由於本發明不需 於該開口區中電鍍線路層，故本發明化鍍形成之第一線路 層不受剝除阻層及蝕刻導電層之影響，有效保持線路原 形，俾達到提高線路成型之良率之目的，且達到易於設計 細間距之線路之目的。 上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範疇下，對上述實施例進行修 10 111378 201115694 改。因此本發明之權利保護範圍，應如後述之申請專利範 . 圍所列。 . 【圖式簡單説明】 第1A至1D圖係為習知封裝基板之製法示意圖；以 及 第2A至2H圖係為本發明封裝基板之製法示意圖， 其中，第2A’圖係為第2A圖之另一態樣，第2H’圖係為第 2H圖之另一態樣。 •【主要元件符號說明】 10,20 基板本體 10a,20a 銅洛 100a，200a 通扎 100,200 導電通孔 11,21 導電層 12,22 阻層 120,220 開口區 13 線路層 23 第·一線路層 230 電性接觸墊 24 絕緣保護層 240 絕緣保護層開孔 25 表面處理層 11 111378a protective layer opening 240, so that the first circuit layer A < ° 卩 subsurface rests on each of the insulating protective layer openings 240, as described in the electrical contact pad Forming the insulating protective layer 24 ^ " ^月' Cao Yubao described the steps to form a build-up layer with a plurality of circuit layers, "X 夂 ° 偁 (not shown in the figure), and in the build-up structure The outermost layer is formed with an insulating protective layer. Further, the surface of the electrical contact layer 23G can be formed into a surface treatment layer 25' and the material forming the surface treatment layer 25 is selected from the group consisting of electroless nickel/gold electroplating silver, electroplating tin, Among the groups consisting of ENIG, ENEμ力, ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE ENE As shown in FIG. 2H', it is another aspect of FIG. 2H, that is, the substrate body 20 is a case where the opposite surfaces do not have a carrier or dielectric layer of copper foil, and the manufacturing method thereof is the same as the above. The present invention recloses a package substrate comprising: a substrate body 2〇, the substrate body having two The first circuit layer 23 is formed of a metallization material and is between the substrate body 20 and the first circuit layer 23, and a surface of the first circuit layer 23 disposed on the surface of the substrate, such as the surface of the substrate. The first circuit layer 23 completely covers the upper surface and the side surface of the conductive layer 21. In the above package substrate, the substrate body 20 may have copper foil 20a on opposite surfaces. a copper foil substrate (CCL), wherein the first circuit layer 23 completely covers the side surface of the copper foil 20a, the side surface and the upper surface of the conductive layer. The substrate body 20 has a plurality of conductive through holes penetrating through the two surfaces. 111378 9 201115694 200, the first circuit layer 23 disposed on the two surfaces is electrically connected to the conductive vias 200, and each of the conductive vias 200 is formed by the metallization material. The package substrate includes an insulating protective layer 24, which is disposed on the substrate body 20 and the first circuit layer 23. The insulating protective layer 24 has a plurality of insulating protective layer openings 240 to make the first circuit layer 23 Part of the surface is exposed to each of the insulating protective layer openings 240, As the electrical contact pad 230, the package substrate comprises a surface treatment layer 25, which is disposed on each of the electrical contact pads 230, and the material forming the surface treatment layer 25 is selected from the group consisting of electroplated nickel/gold and electroplated silver. Among the groups of electroplating tin, nickel immersion gold (ENIG), nickel immersion gold (ENEPIG), chemical tin (Immersion Tin), chemical gold, chemical silver and organic soldering agent (OSP) In summary, the present invention forms a patterned opening region by exposure and development of the resist layer, and then removes the conductive layer in the open region to form a metal on the remaining conductive layer, thereby producing The first circuit layer; since the present invention does not need to electroplat the circuit layer in the open region, the first circuit layer formed by the plating according to the present invention is not affected by the stripping resist layer and the etching conductive layer, and effectively maintains the original shape of the circuit. Improve the yield of the line forming, and achieve the purpose of easily designing fine pitch lines. The above-described embodiments are intended to illustrate the principles of the invention and its advantages, and are not intended to limit the invention. Any person skilled in the art can modify the above embodiment without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the patent application form described later. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1D are schematic views showing a method of manufacturing a conventional package substrate; and FIGS. 2A to 2H are diagrams showing a method of manufacturing a package substrate of the present invention, wherein the 2A' diagram is a 2A diagram. In another aspect, the 2H' map is another aspect of the 2H map. • [Main component symbol description] 10,20 substrate body 10a, 20a Tongluo 100a, 200a through 100,200 conductive via 11, 21 conductive layer 12, 22 resistive layer 120, 220 open region 13 circuit layer 23 first circuit layer 230 Contact pad 24 Insulating protective layer 240 Insulating protective layer Opening 25 Surface treatment layer 11 111378