201104812 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種封裝結構及其製法，尤指一種利於 細線路設計之封裝結構及其製法。 【先前技術】 隨著半導體封裝技術的演進，除了傳統打線式 cmdmg)半導體封裝技術以外，目前半導體裝置 .e職。nd⑽。r devke)已開發出不同的封裝型態例如直 接在一封裝基板（package substrate)中嵌埋並電性整人一 例如具有積體電路之半導艚B lL^+ ^ ° 主道邮千¥肢日日片，此種封裝件可縮減整體 半導肢裝置之體積並提昇電性 流。 ^玍功此，逐成為一種封裝的主 請參閱第1A至1Γ同 & & 音 圖，如為習知封裝結構之製法示 心圖。如弟1 A圖所示，担/吐R Λ- ,m 柃么、具有貝穿開口 100之第一承 載板】〇,於該第-承载板10 弟承 住該開σ 100之一端，再接徂且/第一承載板n，以封 祚用而再棱（、具有相對之作用面12a及非 作用面12b的半導 虹日日片12,且於該作用面12a上且右遴 數電極#120,而該非作用面d上具有複 導體晶片12固定"n b糟由黏者層13以將該半 第二I 1〇0中的第二承載板11上，·如 笫圖所不，接著， 上以熱壓貼覆介電層14 :二承二板10及該作用面12a 與半導體q丨2之_^ 14填人該開口 100 八+a 中；如第1C圖所示，再於哕201104812 VI. Description of the Invention: [Technical Field] The present invention relates to a package structure and a method of manufacturing the same, and more particularly to a package structure and a method for manufacturing the same. [Prior Art] With the evolution of semiconductor packaging technology, in addition to the conventional wire-type cmdmg) semiconductor packaging technology, the current semiconductor device. Nd(10). r devke) has developed different package types such as directly embedded in a package substrate and electrically integrated with a semi-conductor such as an integrated circuit B lL ^ + ^ ° main road thousand The limbs are daily, which can reduce the volume of the overall semi-limb device and increase the electrical flow. ^ 玍 此 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , As shown in Figure 1A, the first carrier plate with the opening of the opening 100, the first carrier plate with the opening of the opening 100, holds the one end of the opening σ 100. And the first carrier plate n is re-arranged for sealing (the semi-conducting rainbow Japanese wafer 12 having the opposite active surface 12a and the non-active surface 12b, and the right side of the active surface 12a Electrode #120, and the non-acting surface d has a complex conductor wafer 12 fixed "nb from the adhesive layer 13 to the second carrier plate 11 of the half second I 1 〇 0, Then, the dielectric layer 14 is thermally pressed; the second bearing plate 10 and the active surface 12a and the semiconductor q丨2 are filled in the opening 100 八+a; as shown in FIG. 1C, Again
”包層14中形成複數對 A 後於哼介★择l 了“各4电極墊120之盲孔14〇，之 …亥^層Μ上形成線路層15，且該線路層Μ具有位 111242 4 201104812 ::孔14。中之導電盲孔15。，以電性連接至各該電 惟’前述習知技術中，係先將該半導體晶片u設於 承载板中，再形成該線路層15，以藉由該導電盲孔⑼對 應電性連接該電極塾12〇. ^ 子 斜導體晶片12與開口 時，因間需預留間隙，當該介電層14進行熱塵合 中因素，易使該半導體晶片12於該開口 _ 亡孔= e’如第1Β圖所示’而此偏移e將造成該導電 、L 連接該電極塾120之對位偏差，甚至因偏差 ^而無法有效電性連接該電極墊120。 者如第1C圖所不，若要避免該導電盲孔150盘 '2〇之對位偏差，係可將該盲孔140之尺寸增大? 以露出所需之電極墊12〇之接觸面積，以確保該導電盲孔 =有效％性連接該電極塾12(};.准，藉由增加該導電盲孔 +亡之尺寸’雖可達到預期之電性連接功效，但卻因該導 電盲孔150佔用過多該介電層14之表面，導致該線路層 15之佈線設計難以達到細線路之目的。 a 、口此鑒於上述之問題，如何避免習知技術中之電性 及難以作細線路設計之問題’實已成目前亟欲解 【發明内容】 釔方、上述白知技術之種種缺失，本發明之一目的係提 供一種提升電性連接良率之封裝結構及其製法。 本發明之另—日沾及;上 的ίτ' &供一種利於細線路設計之封 5 ]1]242 201104812 裝結構及其製法。 為達上述及其他目的，本發明揭露一種封裝結構，係 包括：基板本體；半導體晶片，係嵌埋於該基板本體中， 且具有相對之作用面及非作用面，該作用面上具有複數電 極墊；異方性導電膠，係設於該半導體晶片之作用面及電 極墊上；以及線路層，係嵌設於該基板本體中且外露於該 基板本體表面’該線路層具有複數導電跡線及嵌設於該異 方性導電膠中之第一電性接觸墊，又各該第一電性接觸墊 形成晶片接置區，且至少一對第一電性接觸墊之間具有至 * 少一導電跡線，而該半導體晶片係結合至該晶片接置區， 該第一電性接觸墊之頂面積小於該電極墊之頂面積，並於 該電極墊與第一電性接觸墊之間的異方性導電膠形成導電 通路，以令各該電極塾措由該導電通路電性連接至各該弟 一電性接觸墊，又該線路層具有複數設於該晶片接置區外 圍之第二電性接觸墊，以形成焊墊區。 前述之封裝結構中，該基板本體係可由第一介電層及 參 第二介電層所組成，且該線路層係可為電鍍金屬材；該些 第一電性接觸墊係可藉由同一線路層之各該導電跡線導接 至相對應之第二電性接觸墊。 前述之封裝結構復可包括第一及第二防焊層，其中， 該第一防焊層係設於該基板本體上，而該第二防焊層係設 於該異方性導電膠及線路層上，且該第二防焊層中具有複 數開孔，以令各該第二電性接觸墊對應外露於各該開孔； 又該些第二電性接觸墊上可具有焊球；亦或，該些第二電 . 6 )))242 201104812 性接觸墊上可具有表面處理居 .料係可選自由化學鍍鎳/金/，且二成該表面處理層之材 .浸金⑽題）、化學、化_ 焊劑(OSP)所組成之群組中之一 ersi0n Tln)及有機锦 。 本發明復揭露—Ί 者° .承載板；於該承栽板上形成括：提供— 導電跡線及第1性接觸墊1 Μ線路層具有複數 晶片接置區，又讀線路層具 :弟-電性接觸藝形成 之第二電性接觸餐，以形成焊塾月接置區外圍 上形成異方性導電夥;於該異方性導電性接觸塾 電極墊之半導體晶片，令該此4 电I上壓合具有複數 膠中，且該電極塾之頂面積於該異方性導電 積，並且各該電極墊對應各該第—乂電性接觸塾之頂面 電極塾與第-電性接觸塾之間的塾，以令各該 路，俾使各該電極塾藉由該導 I膠形成導電通 電性接觸塾；於m板及半接至各該第一 體，以覆蓋該半導體晶片；以及二承tr—基板本 該線路層及第一電性接觸墊，且八 载板，以外露出 嵌埋於該基板本體中。 7 〇線路層及半導體晶片 耵述之製法中，於該承栽板上护 層，且該半導體晶片具有相對之作用’、了·电鍍形成該線路 該電極塾係設於該作用面上；非作用面，而各 由各該導電跡線導接至相對應之^弟+電性接觸墊係可藉 ifr -- . φ, .χ ^ $ —電性接觸墊。 述之衣Ο，該基板本體覆蓋該半導體晶片之製 Π1242 7 201104812After the complex pair A is formed in the cladding layer 14, the blind hole 14〇 of each of the four electrode pads 120 is selected, and the circuit layer 15 is formed on the layer of the layer, and the circuit layer has the bit 111242. 4 201104812 :: Hole 14. Conductive blind hole 15 in the middle. In the prior art, the semiconductor wafer u is first disposed in the carrier, and the circuit layer 15 is formed to electrically connect the conductive via (9). When the sub-angled conductor wafer 12 and the opening are separated, a gap is required, and when the dielectric layer 14 is subjected to thermal dusting, the semiconductor wafer 12 is easily placed in the opening _ dead hole = e' As shown in FIG. 1 , the offset e will cause the conductive, L to be connected to the electrode 120 to be offset, and even the electrode pad 120 cannot be electrically connected due to the deviation. If it is not shown in FIG. 1C, if the alignment deviation of the conductive blind hole 150 is not avoided, the size of the blind hole 140 can be increased to expose the contact area of the electrode pad 12〇 required. In order to ensure that the conductive blind hole=effectively connected to the electrode 塾12(.., by increasing the size of the conductive blind hole + dead size), although the expected electrical connection efficiency can be achieved, but due to the conductive blind hole 150 occupies too much surface of the dielectric layer 14, which makes the wiring design of the circuit layer 15 difficult to achieve the purpose of fine lines. a, mouth, in view of the above problems, how to avoid the electrical properties of the prior art and difficult to make fine circuit design The problem of the present invention has become a deficiencies of the present invention. One of the objects of the present invention is to provide a package structure for improving the electrical connection yield and a method for fabricating the same.日 及 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Semiconductor wafer, embedded The substrate body has an opposite active surface and a non-active surface, the active surface has a plurality of electrode pads; the anisotropic conductive adhesive is disposed on the active surface of the semiconductor wafer and the electrode pad; and the circuit layer is embedded Provided in the substrate body and exposed on the surface of the substrate body. The circuit layer has a plurality of conductive traces and a first electrical contact pad embedded in the anisotropic conductive paste, and each of the first electrical contact pads Forming a wafer connection region, and having at least one conductive trace between at least one pair of first electrical contact pads, and the semiconductor wafer is bonded to the wafer connection region, a top area of the first electrical contact pad An electrically conductive path is formed between the electrode pad and the first electrical contact pad to form a conductive path, so that each of the electrodes is electrically connected to each other by the conductive path. An electrical contact pad, the circuit layer having a plurality of second electrical contact pads disposed on a periphery of the wafer connection region to form a pad region. In the foregoing package structure, the substrate system may be a first dielectric layer And the second dielectric And the circuit layer can be an electroplated metal material; the first electrical contact pads can be connected to the corresponding second electrical contact pads by the conductive traces of the same circuit layer. The package structure may include first and second solder resist layers, wherein the first solder resist layer is disposed on the substrate body, and the second solder resist layer is disposed on the anisotropic conductive paste and the circuit layer And the second solder mask has a plurality of openings, so that the second electrical contact pads are correspondingly exposed to the openings; and the second electrical contact pads may have solder balls; or Some of the second electricity. 6))) 242 201104812 Sexual contact pads can be surface treated. The material can be selected from free electroless nickel/gold/, and two parts of the surface treatment layer. Immersion gold (10) questions, chemistry, One of the groups of _ flux (OSP) ersi0n Tln) and organic brocade. The invention is characterized in that: the carrier board is formed on the board: providing - a conductive trace and a first contact pad 1 Μ the circuit layer has a plurality of wafer connection areas, and the circuit layer is read: a second electrical contact meal formed by the electrical contact art to form an anisotropic conductive bond on the periphery of the solder joint month; in the semiconductor wafer of the anisotropic conductive contact electrode pad, The electric I is pressed into a plurality of glues, and the top area of the electrode is in the anisotropic conductive product, and each of the electrode pads corresponds to the top electrode 塾 and the first electric property of each of the first electric contact pads Contacting the crucibles between the crucibles so that each of the electrodes is formed by the conductive adhesive to form a conductive conductive contact; the m-plate and the half are connected to the first bodies to cover the semiconductor wafer And the second carrier tr-substrate, the circuit layer and the first electrical contact pad, and the eight carrier plates are exposed and embedded in the substrate body. In the method of describing the circuit layer and the semiconductor wafer, the protective layer is disposed on the carrier, and the semiconductor wafer has a relative function. The plating is formed on the surface of the electrode. The active surface, and each of the conductive traces is connected to the corresponding ^ electrical + electrical contact pad system by means of ifr -- . φ, .χ ^ $ - electrical contact pads. The substrate body covers the semiconductor wafer. 1242 7 201104812
法，係可㊁括·I 介電層a …亥承戰板上形成第一介電扃 曰卉有介電層開D，、 " ¾層，且該第一 介電層及該半導體晶片上=該半導體晶片；於該第一 二介電層與該第一介電弟二介電層，、及壓合該第 層結合成該基板本體二介電層與該第-介電 前迷之製法復可包導體晶片。 層’並於該異方性導電、〜板本體上形成第-防焊 該第二防焊層中形成複:路層上形成第二防焊層，且 對應外露於各該開孔；又=L ’以令各該第二電性接觸塾 形成烊J求； 或::該第括於各該第二電性接觸塾上. 且形成該表面處理層之H性接齡上形成表面處理層， 浸金（咖叫化賴浸H可選自由化•糾、化錄Method, the second dielectric layer I ... the first dielectric layer formed on the board, the dielectric layer is opened D, " 3⁄4 layer, and the first dielectric layer and the semiconductor wafer Up=the semiconductor wafer; combining the first two dielectric layers with the first dielectric dielectric layer, and pressing the first layer to form the dielectric layer of the substrate body and the first dielectric front fan The method of manufacturing can enclose a conductor wafer. a layer 'and forming a first anti-welding on the anisotropic conductive, ~ plate body, the second solder mask layer is formed in the second: a second solder resist layer is formed on the road layer, and correspondingly exposed to each of the openings; L' is formed so that each of the second electrical contacts is formed; or:: the second electrical contact is formed on each of the second electrical contacts, and the surface treatment layer is formed on the H-type age of the surface treatment layer , immersion gold (Cal is called immersion H optional liberalization; correction, record
Tin)及有機保焊劑（_)戶(NEPIG >化學㈣（ 由上可知，本發d且2之f組中之其中一者。 層，再將該半導體晶片對9於料載板切成該線路 該異方性導電膠之導 Μ第一電性接觸墊，以藉由 電極奐；相較於習知技術路：性連接該第-電性接觸墊與 產生鳴移，該頂面積較小^發明不論該半導體晶片是否 方性導電膠有效電性連接’―電性接觸塾均可藉由該異 提升電性連接良率之目的了7Μ面積較Α之電極整’以達到 再者，太私日3夕楚 墊之項面積，使各該第〜：性接觸墊之頂面積 小於該電極 用，縮小，可利：細：電性接觸塾於該基板本體上之佔 【貫地方式】 之°又°十與提兩佈線密度。 111242 8 201104812 以下藉由特定的具體實施例說明本發明之實施方 悉此技藝之人士可由本說明書所揭示之内容：易地 瞭解本發明之其他優點及功效。 閱第2A至21圖，係為本發明所揭露之— 結構之製法。 如弟2A圖所*，提供一承載板2〇 種類繁多，惟… ^ 们，艰載板之 准乃業界所周知，且其非本案技術特徵，故不 另迎’特此述明。 第2B圖所示，於該承載板2〇上形成線路層21， ^7複數導電跡線21。及第—電性接㈣ 又㈣Λ 接觸墊…陣列排成晶片接置區F， + 021具有複數設於該晶片接置區？外®之第一 二性接觸墊叫，以形成焊墊區s，較佳地，係 = 式形成該線路;S 2〗.々 卜 包經方 ,π θ 另外，各該第一電性接觸墊2la俜蕤 由同一層線路層21之各該導糸稭 二雷m㈣ °料电跡線…導接至相對應之第 乃業界所周7 然’有關於形成線路之技術繁多，惟 述明。1 °且其非本案技術特徵，故不再贅述，特此 Ξ之H 2C圖所不’於各該第—電性接㈣21a及苴朽 rA · + . 一導电跡線21c上形成異方性導電脒 A~〇pic 22之形成·係對應後續製程中之半導體^ 23 4 之異方性導電躍22主要由嶋二 粒子組成，其可提供兩種接合物體僅於單—方向作電= 川 24.2 [ 9 201104812 通，於本實施例中，係作垂直方向電性導通，而對於水平 方向則具有絕緣效果。 如第2D及2D’圖所示，於該異方性導電膠22上壓合 半導體晶片23,令該半導體晶片23结合至該晶片接置區F 上，而該半導體晶片23具有相對之作用面23a及非作用面 23b，於該作用面23a上具有複數電極墊230，且各該電極 墊230對應各該第一電性接觸墊21a，令該些電極墊230 嵌埋於該異方性導電膠22中，且該電極墊230之頂面積 S1大於該第一電性接觸墊21a之頂面積S2，以令各該電 極墊230與第一電性接觸墊21a之間的異方性導電膠22 形成導電通路24,俾使各該電極墊230藉由該導電通路24 電性連接至各該第一電性接觸墊21a。 如第2E圖所示，於該承載板20及半導體晶片23上 形成第一介電層25a，且該第一介電層25a具有介電層開 口 250，以收納該半導體晶片23且露出該非作用面23b ; 於該第一介電層25a及該半導體晶片23之非作用面23b 上形成第二介電層25b;其中，該第一介電層25a及第二 介電層25b例如為玻纖浸樹脂（Prepreg, PP)。 如第2F圖所示，熱壓合該第二介電層25b與第一介 電層25a，令該第二介電層25b與該第一介電層25a結合 成基板本體25 ^以覆蓋該半導體晶片23。 如第2G圖所示，移除該承載板20，以外露出該線路 層21，且令該半導體晶片23嵌埋於該基板本體25中，而 該線路層21嵌設於該基板本體25表面。 10 1Π242 201104812 於該基板本體25上形0 —防焊層 層2 6 b，且^導電膠2 2及線路層21上形成第二防焊 节第二〜5亥弟二防焊層勘中形成複數開孔260,以令各 各知Γί接觸塾21b對應外露於各該開孔;另外， /汗^260並未露出各該第一電性接觸墊21公。 個具^本21/所示，可切割該基板本體25，以形成複數 電性23之封裝結構單元;且可於各該第二 該第二+㈣ 成焊球27 ;如第21’圖所示，或於各 面處r里r2t_21b上形成表面處理層28,而形成該表 料係選自由化學鱗鎳/金、化錄浸金Tin) and organic flux-preserving agent (_) household (NEPIG > chemistry (4) (from the above, one of the groups of the present group d and 2, the layer, and then the semiconductor wafer pair 9 is cut into the carrier board The line of the anisotropic conductive paste guides the first electrical contact pad to pass the electrode 奂; compared with the conventional technology, the first electrical contact pad is connected and the sound is generated, and the top area is compared. Small ^Invented whether or not the semiconductor wafer is electrically conductively connected to the conductive adhesive. The electrical contact can be achieved by the purpose of increasing the electrical connection yield. Too private day 3 eves the area of the pad, so that the top area of the first:: sexual contact pad is smaller than the electrode, shrinking, profitable: fine: electrical contact on the substrate body The following is a description of the present invention by way of specific embodiments. And the effect. See Figures 2A to 21, which are disclosed in the present invention. — The method of structure. As shown in Figure 2A, there is a wide variety of carrier boards. However, the standard of the difficult board is well known in the industry, and it is not a technical feature of this case. As shown in Fig. 2B, a circuit layer 21, ^7 plurality of conductive traces 21 are formed on the carrier board 2, and a plurality of conductive traces 21 are formed. And the first electrical contacts (four) and (four) 接触 contact pads are arranged in a wafer arrangement area F, + 021 has a plurality of first two-contact pads disposed in the outer region of the wafer to form a pad region s. Preferably, the system forms the line; S 2〗. π θ In addition, each of the first electrical contact pads 2la俜蕤 is connected by the respective conductive traces of the same layer of the circuit layer 21 to the corresponding first stage of the industry. There are many techniques for forming a line, but it is stated that 1 ° and its technical characteristics are not described in this case. Therefore, the H 2C map is not the same as the first electrical connection (4) 21a and r decay rA · + The formation of the anisotropic conductive 脒A~〇pic 22 on a conductive trace 21c corresponds to the anisotropic conduction of the semiconductor in the subsequent process. 22 is mainly composed of bismuth particles, which can provide two kinds of joint objects only in the single-direction electricity = Chuan 24.2 [9 201104812 pass, in this embodiment, it is electrically conductive in the vertical direction, and for the horizontal direction Insulation effect. As shown in FIGS. 2D and 2D', the semiconductor wafer 23 is pressed onto the anisotropic conductive paste 22, and the semiconductor wafer 23 is bonded to the wafer receiving region F, and the semiconductor wafer 23 has a relative The active surface 23a and the non-active surface 23b have a plurality of electrode pads 230 on the active surface 23a, and each of the electrode pads 230 corresponds to each of the first electrical contact pads 21a, so that the electrode pads 230 are embedded in the different In the square conductive paste 22, the top surface area S1 of the electrode pad 230 is larger than the top surface area S2 of the first electrical contact pad 21a, so that the anisotropy between each of the electrode pads 230 and the first electrical contact pad 21a The conductive adhesive 22 forms a conductive path 24, and the electrode pads 230 are electrically connected to the first electrical contact pads 21a via the conductive vias 24. As shown in FIG. 2E, a first dielectric layer 25a is formed on the carrier 20 and the semiconductor wafer 23, and the first dielectric layer 25a has a dielectric layer opening 250 for receiving the semiconductor wafer 23 and exposing the non-active layer. a second dielectric layer 25b is formed on the first dielectric layer 25a and the non-active surface 23b of the semiconductor wafer 23; wherein the first dielectric layer 25a and the second dielectric layer 25b are, for example, glass fibers Impregnated resin (Prepreg, PP). As shown in FIG. 2F, the second dielectric layer 25b and the first dielectric layer 25a are thermocompression-bonded, and the second dielectric layer 25b and the first dielectric layer 25a are combined into a substrate body 25 to cover the second dielectric layer 25b. Semiconductor wafer 23. As shown in Fig. 2G, the carrier layer 20 is removed, the wiring layer 21 is exposed, and the semiconductor wafer 23 is embedded in the substrate body 25, and the wiring layer 21 is embedded on the surface of the substrate body 25. 10 1Π 242 201104812 Forming a 0-solderproof layer 2 6 b on the substrate body 25, and forming a second solder mask on the conductive paste 2 2 and the circuit layer 21 to form a second solder mask The plurality of openings 260 are formed so that the respective contacts 塾21b are correspondingly exposed to the respective openings; and the / sweat 260 does not expose the first electrical contact pads 21. As shown in FIG. 21/, the substrate body 25 can be cut to form a package structure unit of a plurality of electrical properties 23; and the second and second (four) solder balls 27 can be formed in each of the second and second portions; Or forming a surface treatment layer 28 on r2t_21b at each surface, and forming the surface material is selected from chemical scale nickel/gold, chemical immersion gold
Tin)及有機保焊_SP)所組成之群^ j ( 1随⑽_ 本發明係先於該承載板20上電/、中者。 再將該半導體晶片23對位各該成該線路層2卜 置，以藉由該異方性導電膠22之導電接觸墊21a而設 第一電性接觸墊2la與電極墊23〇;=1路24電性連接該 本發明之第二介電層25b與第一介^於習知技術’當 本體25肖，不論該半導體晶# 12灸:仏壓合成該基板 fS2較小之第—電性接觸塾21a均 > 產生偏移，該頂面 2有致電性連接該頂面積S1較大< 該異方性導電膠 “再者，請-併參閱第2J圖，係：、 圖’其中省略該第二防焊層施及焊圖之底視示意 二+導體晶片23產生偏移，則_ 7;若壓合過程中， 大於該第-電性接觸墊⑴:極备230之頂面積 ，積幻，故該電㈣ 111242 ]1 201104812The group consisting of Tin) and the organic soldering _SP) (1 with (10)_ The present invention is prior to the power supply of the carrier board 20. The semiconductor wafer 23 is aligned to form the circuit layer 2 The first electrical contact pad 21a and the electrode pad 23 are provided by the conductive contact pad 21a of the anisotropic conductive adhesive 22; the second channel 24b is electrically connected to the second dielectric layer 25b of the present invention. And the first method of the prior art 'when the body 25 shaws, regardless of the semiconductor crystal #12 moxibustion: the first synthesis of the substrate fS2 is smaller - the electrical contact 塾 21a> produces an offset, the top surface 2 There is a callable connection to the top area S1 is larger < the anisotropic conductive adhesive "again, please - and refer to the 2J figure, is: Figure" which omits the second solder mask and the bottom view of the soldering pattern It is indicated that the two + conductor wafer 23 is offset, then _ 7; if the pressing process is greater than the top surface of the first electrical contact pad (1): the top 230, the illusion, so the electricity (four) 111242 ] 1 201104812
Z JU 旁效對位該第一電性拯 性連接；因此’本發明藉由4觸ila’以保持良好之電 積S2小於該電極塾23 =1性接觸墊2U之項面 電性接觸塾叫於該基板之;^^之技術，使各該第〜 利於該線路層21作細線路之佈綠設言=占用面積縮小，俾有 本發明復提供一種封梦纴。 25a及第二介電肩 I，。構’係包括··由第-介電層 作用面Μ 叙基板本體25，·且有相對 作用面23a及非作用面23 八有相射之 基板本體25中，且該作用而^體日曰片23 ’係嵌埋於該 異方性導電膠22，/讲a 23a上具有複數電極墊23〇; 及電極塾23^上；以及又亥半導體晶片23之作用面23a 中且外露”基板本體於該絲本體25 電跡線〜及嵌設於該異方二^路層21具有複數導 墊叫’又各該第一電，心=中之第-電性接觸 F，且至少1第一電性接觸塾二::成晶片接置區 線叫，而該半導體晶片 p間具有至少-導電跡 第一電性接觸塾21a之頂面該晶片接置區F，該 積81，迷於該電極替23。心一+、錢極塾23〇之頂面 方性導電膠22形成導電通;;；7接觸塾2ia之間的異 由5亥導電通路24電性連 M令各該電極塾230藉 該線路層21具有複數電性接觸塾21a，又 :接觸藝叫，以形成焊：片接置區F外圍之第二電 件。 Q S，稭以導接至外部電子元 ~返之線路層21 電鍍金屬材，且各該第一i 1J1242 201104812 C導接 接觸墊21a係藉由同一線路層21之各該導電跡線21 至相對應之第二電性接觸墊21b，如第2J圖所示。 層 該封裝結構復包括設於該基板本體25上之第一防焊 p ，及設於該異方性導電膠22及線路層21上之第二 =層26b，且該第二防焊層26b中具有開孔，以令各 第=二電性接觸塾21b對應外露於各該開孔26。;又該些 ^接觸塾21b上具有焊球27或表面處理層Μ，且 養金^:處理層28之材料係選自由化學鑛鎳/金、化錄 、）及^他浸金（ENEPIG)、化學錄錫Μ— 綜=焊:K，組成之群組中之其中一者。 電麵墊對位該^ =封裝結構係藉由該了頁面積較大之 =導體晶片是否產之第—電性接觸藝，因而不論該 ^性導電膠有4:拉該第—電性接觸整均可藉由該 趣良率之目的。险連接該電極塾，以達到提升電性連 再者，本發明扣 ::頂面積’故j :性接觸墊之頂面積小於該 "積縮小，俾利(:線Γ接觸塾於該基板本體上以 致上述實施例係用以:^計與提高佈線密度。. 1非用於限制本㈣本發明之原理及其功 發明之精Cb項技藝之人士均可 =此本發明^ 對上述實施例進行修 【：列。 1圍，應如後述之申請專利範 L圖式簡單說明】 111242 13 201104812 其中 第〗A至1C圖係為習知封裝結構之穿去之 ，第1C，圖係為第1C圖之另-實施態樣\ 示意圖 其中 第2A至21圖係為本發明封裝結構之製法之示意圖； 弟2D圖係為弟2D圖之局部放大圖 ，第2Γ圖係為 第21圖之另一實施態樣；以及 第2J圖係為第21圖之底視示意圖。 【主要元件符號說明】 10 第一承載板 100 開口 11 苐一承載板 12,23 半導體晶片 12a，23a 作用面 12b，23b非作用面 120,230電極塾 13 點著層 14 介電層 140 盲孔 15,21 150 20 21a 21b 21c 線路層 導電盲孔 承载板 第一電性接觸墊 第二電性接觸墊 導電跡線 異方性導電膠 111242 22 201104812 24 導電通路 25 基板本體 25a 第一介電層 25b 第二介電層 250 介電層開口 26a 第一防焊層 26b 第二防焊層 260 開孔 27 焊球 28 表面處理層 e 偏移 S1,S2 頂面積 S 焊墊區 F 晶片接置區The Z JU side effect is aligned with the first electrical asymmetry connection; therefore, the present invention uses 4 touch ila' to maintain a good electrical product S2 which is smaller than the electrode 塾23 =1 sexual contact pad 2U. It is called the technology of the substrate; the technology of the ^^ is beneficial to the line layer 21 as a fine line of the green line = the area is reduced, and the present invention provides a kind of nightmare. 25a and second dielectric shoulder I,. The structure includes a substrate body 25, a substrate body 25, and a substrate body 25 having a phase of the opposite surface 23a and the non-active surface 23, and the function is The sheet 23' is embedded in the anisotropic conductive paste 22, or has a plurality of electrode pads 23A on the a 23a; and the electrodes 23; and the exposed surface of the semiconductor wafer 23 is exposed. The wire body of the wire body 25 and the embedded circuit layer 21 have a plurality of conductive pads called 'the first electric, the first electrical contact F in the heart=, and at least 1 first Electrical contact :2:: a wafer connection area line, and the semiconductor wafer p has at least a conductive trace of the first electrical contact 塾 21a top surface of the wafer connection area F, the product 81, which is fascinated by The electrode is replaced by 23. The top surface of the conductive layer 22 of the core one +, the money pole 〇 23〇 forms a conductive pass;; 7 the difference between the contact 塾 2ia 5 electrically conductive path 24 electrically connected to the electrode 令230, the circuit layer 21 has a plurality of electrical contacts 21a, and: contact with the art to form a second electrical component of the periphery of the chip attachment region F. QS, the straw is guided to the outside The circuit board 21 is plated with a metal material, and each of the first i 1J1242 201104812 C conductive contact pads 21a is formed by the respective conductive traces 21 of the same circuit layer 21 to the corresponding second electrical contact pads. 21b, as shown in FIG. 2J. The package structure includes a first solder resist p disposed on the substrate body 25, and a second layer 26b disposed on the anisotropic conductive paste 22 and the circuit layer 21. And the second solder resist layer 26b has an opening therein, so that each of the second electrical contact pads 21b is correspondingly exposed to each of the openings 26. The solder contacts 27b or the surface treatment are provided on the contact pads 21b. Layer Μ, and the gold layer: the material of the treatment layer 28 is selected from the group consisting of chemical mineral nickel/gold, chemical recording, and enamel gold (ENEPIG), chemical recording tin Μ - comprehensive = welding: K, the group One of the electric mats is in the position of the ^ = package structure by the larger area of the page = whether the conductor wafer produced the first - electrical contact art, so regardless of the conductive adhesive has 4: pull The first electrical contact can be used for the purpose of the interest rate. The electrode is connected to the battery to achieve the improvement of the electrical connection. The buckle of the present invention: the top area j: the top area of the sexual contact pad is smaller than the "product shrinkage, profit: (the wire is in contact with the substrate body so that the above embodiment is used to: measure and increase the wiring density. 1 is not used to limit the present (4) The principle of the present invention and the person skilled in the art of the invention can be = the present invention ^ The above embodiment is modified [: column. 1 circumference, should be as described later in the patent specification L diagram simple description] 111242 13 201104812 The first A to 1C diagram is worn by the conventional package structure, the 1C, the diagram is the other embodiment of the 1C diagram, and the 2A to 21 diagram is the package structure of the present invention. Schematic diagram of the manufacturing method; the 2D drawing is a partial enlarged view of the 2D drawing, the second drawing is another embodiment of the 21st drawing; and the 2J drawing is the bottom view of the 21st drawing. [Main component symbol description] 10 first carrier 100 opening 11 承载 a carrier 12, 23 semiconductor wafer 12a, 23a active surface 12b, 23b non-active surface 120, 230 electrode 塾 13 point layer 14 dielectric layer 140 blind hole 15, 21 150 20 21a 21b 21c circuit layer conductive blind hole carrier plate first electrical contact pad second electrical contact pad conductive trace anisotropic conductive adhesive 111242 22 201104812 24 conductive path 25 substrate body 25a first dielectric layer 25b Dielectric layer 250 dielectric layer opening 26a first solder mask 26b second solder mask 260 opening 27 solder ball 28 surface treatment layer e offset S1, S2 top area S pad area F wafer connection area
1Π2421Π242