TW201035781A - Root finding circuit - Google Patents

Abstract

A root finding circuit is suitable for detecting whether a nonzero element belongs to the root of an R-order polynomial. The root finding circuit comprises a computing device and a comparator. The computing device includes: (R-1) order calculators, each order calculator corresponding to one of the orders in the polynomial except a selected order and generating an order product based on the coefficient of the corresponding order; and a finite adder for receiving the order products generated by all order calculators and the coefficient of the selected order so as to form a numerical signal. The comparator is used for comparing a selected reference value related to the selected order with the numerical signal, so as to determine whether the nonzero element belongs to the root of the polynomial.

Description

201035781 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to an algebraic arithmetic technique, and more particularly to a root-seeking circuit for implementing Chien Search. [Prior Art] Ο ❹ The main purpose of the Qian search method is to find the root of the polynomial (r〇 is to facilitate the factorization of the polynomial. It is commonly used in Reed Solomon (RS) to correct random bit errors. The decoder analyzes the _ er^ polynomial to find the location where the error occurred. = Suppose the RS decoding ϋ receives an (n, k, d) coded signal whose code length is the bit 'the actual information length k bits, The error correctable capacity is and = where W represents: the largest positive integer less than or equal to X. Then the is2 solution can generate an error-loc polynomial with an order of up to R according to the coded signal, as in equation (1). Then, using the Qiangong search method, the Gallo-body GFO N non-zero elements (_· one generation) are tested to find out which non-zero elements belong to the root of the error location polynomial, and all the test operations are based on The finite body of the Galois body GF(2m), where m, η=0,1,2..·(Ν-1), and the constant term coefficient of the error location polynomial, the coefficients of each order are Λ·ι ' Λ2... Ο) λ(^ )= ΣΛ^ r=0 r See Figure 1 ' The circuit diagram for implementing equation (1) is shown. When a non-zero 201035781 element αη is introduced into the thunder, the non-zero element y is: Ρ can be combined by the finite body multiplier 71 and the number is calculated by the adder. The 72nd set is 1 to judge the 22nd-comparator 73 according to the numerical signal to determine the occurrence of the "two-two prime." is the root of the error location polynomial, t is the wrong position. Then the circuit of Figure i will In the following:: Another non-zero element α". However, such a circuit must take a period of time to complete all non-zero elements', and the decoding efficiency. + Lee proposed a parallelization concept for this technology (Figure 2 ), so that the non-zero element core of the towel is tested at the same time t to reduce the detection to the "giving 1 cycle, which represents the largest positive integer greater than or equal to χ. And the other technology is more Figure 2 is simplified in Figure 3, in an attempt to reduce the operating time per cycle. Unfortunately, the degree of improvement is limited. Figure 1~3 'It is not difficult to find: for each non-zero element ^, the comparator 73 waits until the calculation The value signal (containing the non- After the element ^'s dimension, the resulting value signal is compared to 1. This means that the comparators 73, 83, 93 have a relatively long waiting time, which affects the operation time of each cycle, and is also decoded. In addition, although the number of inspection cycles of the circuits of Figures 2 and 3 is reduced compared with Figure 5, the number of hardware circuits is almost p times that of Figure i, and the implementation cost is too high. In view of this, there are successively Other improvements have been proposed, such as:

Chen and Paihi share the arithmetic circuit in the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATWN (VLSI) SYSTEMS, 2004 with the combination of the Iterative Matching and the Group Matching method 201035781. For example: Cho and Sung / 五石五TRANSACTIONS ON CIRCUITS AND SYSTEMS-U, 2008 It is now a shifter to replace the finite-body multiplication. However, under the framework of Figures 2 and 3, these practices cannot effectively alleviate the pressure of implementation cost. [The present invention] Therefore, the object of the present invention is to provide a root-seeking method that can reduce the root-checking time and reduce the cost of the hardware circuit. Circuit. Therefore, the root-seeking circuit of the present invention is adapted to verify whether a non-zero element belongs to a root of an R-th order polynomial, comprising: a computing device comprising: (R_1) order operators, each of which corresponds to a polynomial Except for a first order of a selected order ', and generating a first-order product according to the coefficient of the corresponding order; and a finite body adder, receiving a multiplicative product generated by all the order operators and coefficients of the selected order, forming a And a comparator that compares the selected signal with the selected reference value to determine whether the non-zero element belongs to the root of the polynomial. The root-seeking circuit of the present invention is adapted to verify whether a non-zero element belongs to the root of an R-th order polynomial, and includes: a first computing device comprising: five-order arithmetic operators, each of the multi-dimensional operators corresponding to one of the polynomials Selecting one of the orders of the order, and generating a first-order product according to the coefficient of the corresponding order, 匕, and a finite body adder, receiving the step product generated by the s-order operators and the coefficients of the selected order, forming a first a second signal; a second & ten different device, comprising: (R_丨_S) order operators, each order operator corresponding to one of the selected orders in the polynomial, and according to the corresponding order The 201035781 coefficient produces a first order product; and a finite body adder receives the product of the (R_丨_s) order operator and a selected reference value for the selected order to form a second value signal And a comparator that compares the first value signal with the second value signal to determine whether the non-zero element belongs to the root of the polynomial. The above and other technical contents, features and effects of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention. Before the present invention is described in detail, it is to be noted that in the following description, similar elements are denoted by the same reference numerals. In order to shorten the waiting time of the comparator to reduce the operation time of each cycle, the present invention proposes a folding architecture, which divides the R-order of the polynomial into two parts and calculates for each part. A numerical signal is produced. The comparator then determines the binary signal. Referring to FIG. 4', the first preferred embodiment of the root-seeking circuit of the present invention is applicable to find the roots belonging to an R-order polynomial from N non-zero elements 加, yi ... yi of the Galois GF (2m). . The rooting circuit i includes a first computing device 11, a second computing device 12, and a comparator 13. The first computing device 11 includes S steps operator TCr and a finite body adder 14, and the second 6th computing device 12 includes (RS) order operators TCr and a finite body adder 14 ° where each step The operator TCr corresponds to the rth order of the polynomial, respectively, and 201035781 has a multiplexer 16, a 1SS <R, Μ, ° and - finite body constant multiplier 17, preferably, the time /2" The operation, and let the second count, device 11 negative Bech number ordering operation η / responsible for even-order operations in each cycle, the minimum V is the root of the polynomial. Under the forced arrangement, assuming non-zero elements They are Λ Λ ' and the multi-handle constant term coefficient \=1, the cut coefficient Σλχ1 r=l step, then the non-zero element ❹ satisfies the equation (2), and when further divided into the even order, the equation (3) is obtained. ^

V 4 νψι 1 (2) (3) ΣΛ<=1+ νΛί/

R.odd ^ rU r:even,r>2 Therefore, in the 'order operator Tcr, the finite body constant multiplier 17 will treat the multiplier as the multiplier "which multiplies the output of the multiplexer 16 to obtain the -th order product, and multiplex In the first self cycle is the coefficient Λ " for the output, and the remaining cycle is to select the register D output. And after the finite body constant multiplier 17 completes the multiplication operation, the step product is sent to the corresponding finite body adder 14, and it is also stored in the register D. And the register D will be delayed - the storage value will be output after one cycle. According to equation (3), the finite body adder 14 of the first computing device U adds up the product of all odd-order order operators TCr to obtain a first value t number 'the finite body of the first 5th computing device 12 The adder 14 obtains a second value signal by adding a step product of all the even-order order operators TCr and adding a value of the constant term coefficient 〇. 201035781 Then, the comparator 13 compares whether the first numerical signal matches the second numerical signal 'to determine whether the zero element y is really a polynomial: the root 7 is in detail 'when the two numerical signals match, the comparator 13 The non-zero element is indeed the root of the polynomial; if it is not coincident, then it is judged as of course. In another embodiment, the finite body adder 14 of the second computing device 12 can only add all the even orders. The step product of the operator TCf is used to obtain the second value signal. The ratio (4) 13 is based on the first-valued signal, the second numerical signal, and the constant term coefficient Λ〇=1, (4). ,. It is worth noting that, in the first cycle, the finite body constant multiplier 17 will produce a factor product due to the reception coefficient \, so the finite body adder 14 will form a numerical signal about the non-zero element at this time. For the comparator 13 to verify that the non-zero element is in the second period, each finite volume constant MU nt updates the order product Λ, 2' for receiving the step product 以, for the comparator 13 to verify the non-zero element y. And so on. It should be noted that the comparator 13 of the preferred embodiment only needs to wait for a period of time to calculate the odd-numbered first-valued signal (four), or wait for a period of time to calculate the second-order numerical signal covering the even-order order, so Conventional techniques substantially shorten the operating time of each cycle. More worthwhile; the idea is that 'when the preferred embodiment is applied to the Μ decoder, after = finding the location where the error occurred, it is necessary to calculate the error 胄r5j under the finite body operation according to the differentiation of the polynomial. The differential result belonging to the even order will be equivalent to 0'. Therefore, when the architecture of the odd-order separation is selected (as shown in Fig. 4), the first-value signal covering the odd-order order can be directly used to obtain the relevant error value, which is indirectly simplified. A circuit for calculating an error value. 201035781 Cover Three Cases The second preferred embodiment of the present invention includes a computing device 21 and a comparison 11 13 . The computing device 21 includes (R-1) order operations 11 Cr and a finite body adder 14. Here, each of the order operators TCr is similar to the step operator TCr of the first preferred embodiment, and the definition of r, which will be described later.

Since the per-order operator TCr has a finite-body multiplier 17 because of its multiplication, and the complexity of the multiplying circuit, the present example attempts to change the corresponding multiplier to reduce the circuit cost. Assuming that the non-zero element " is the root of the polynomial (see equation (2)), this example is to cause computing device 21 to receive a selected order u and divide equation (2). "Fantasy to find the equation (4) ΣΛ, factory (μ_ί_) η + R-

Au + ΣΛ«+Ι· in a (4) As such, the second preferred embodiment will change the multiplier with the selected order u, and omit the use of the order operator TCU 'that is,' the computing device 21 only It is necessary to include (R-1) order operators TCr,, Γ, = 1, 2, ... R but Γ '. At this time, the comparator 13 is compared by a selected reference value (10), which is different from the value of 1 selected for the first preferred embodiment. It is worth noting that because the finite body constant multiplier 17 is equivalent to a set of multiple adders, and multiplied by a different constant ' will correspond to a different number of adders. In this example, the multipliers of the finite body constant multipliers 17 are all 0; the power of the power is 'so different different stages can be replaced by 9 201035781 to minimize the adder (ie: mutual exclusion or (service) gate) The number of uses, which in turn reduces the circuit cost of the root-seeking circuit 2. - However, the rooting circuit 2 of this example may further include an area estimator 28 for providing the selected order, which will first take the absolute value of each "power square" in the equation (4), and then add all the absolute values to obtain - If the area index of the wire type (5) is selected, a plurality of u which reduce the area index are selected for replacement by the computing device 21. In addition, since the step operator % is omitted, the area index may not include _. 面衡曰标=wn| +丨-(“—加丨+...+仏_咖丨(5)=in the process of taking the absolute value, based on the background of the Galois field GF(2m) There is a relationship of QJ-H* γ „ (where vv> 2 -1), so when w>0' can be expressed as w - 2m + i. More notably, the comparator 13 is used for comparison selection. The reference value « is a pre-calculable value, and this value will change with (4). Of course, 'in another-real money, it is also possible to perform no calculation in advance, and (4) a comparison operator 29 to generate this value. The comparison operator 29 has a multiplexer 16, a register D, and a finite body constant multiplier 17, and the action mode is similar to the order operation. τ where the 'finite body constant multiplication n 17 is "multiplied by the multi-guard 16 output and the multiplex is output at the first period with the value of i. Therefore, when the root-seeking circuit 2 is not in the first-order test The zero element α, the limit body constant multiplication method will generate the selected reference value γ according to the output of the multiplex 1 16 (1 value), and in the 10th 201035781 multiplexer 16 will select the input of the register D. To update the selected reference value to two periods, check the non-zero element α2, and the finite body constant multiplier, etc. See Figure 6 'The second preferred embodiment integrates the spirit of the first two embodiments and will The fourth-order operator TCr is divided into two computing devices 31, 32 to reduce the operation time of each cycle, and the number of multipliers of the finite body constant multiplier 17 is changed to achieve the purpose of reducing the circuit cost. The third preferred embodiment of the third embodiment comprises substantially the same elements as the first preferred embodiment (Fig. 4) 'but there are three differences: • (a) the multiplier of the order operator TCr, (2) omitted The order operation n TCu, and the coefficient ΛιΛ is directly transmitted into the finite body plus 14. In the second computing device 32, the finite body adder 14 receives the output of all the even-order operators TCr, and receives the selected reference value 0. This point is different from the first-preferred implementation. In the example, the value of 1 is 0. In order to facilitate the description of the previous paragraph, Figure 6 is an odd number with R being an even number and u being greater than 3. However, in practice, R can be any positive integer, and for example, the value of u is also The architecture of the root-seeking circuit 3 can be equal to i, and the rooting circuit 3 is shown in Fig. 7. Further, a comparison operator 29 can be used as in the previous example to generate the reference value of 11 201035781. The exchangeability of the volume addition operation can also be changed to the first calculation device 31. . In the preferred embodiment, since the circuit implements the upper-order operators TCr and TCr, occupying most of the electric circuit area, and the finite body used in each of the level operators TCr and TCr' The constant multiplier 17 has a circuit structure that can be shared' so that it can be rooted based on the I-known overlap match (Iterative

Matching) way to share circuit components to effectively reduce circuit cost. The fourth preferred embodiment is that the fourth preferred embodiment introduces the concept of parallelization, and the structure of Fig. 7 is changed to Fig. 8, so that the verification of p non-zero elements y can be completed in a single cycle, P>;1. Compared with the third preferred embodiment, the fourth preferred embodiment of the root-seeking circuit 4 of the present invention further comprises OM) first sub-calculators V1_p, (IM) second sub-calculators V2_P& (Pi) comparisons JG-p, ρ=12, (ρ ι). Each of the first sub-calculators VI-P includes S, a rank operator TCr, and a finite body adder 14, and each of the second sub-calculators V2-p includes a collating operator Ep, (R-i_s' a rank operator TCr, and a finite body adder 14 ' and 1SS' < (r_i), r, = 12, r but r, laugh u. The order operator TCr of the 'sub-calculators Vl_p, V2-p, respectively, has a finite body constant multiplier 17 using a multiplier. On the other hand, it is worth noting that the step operator TCr of the computing devices 41, 42 is similar to the third preferred embodiment, but has a multiplexer 16, a register D, and a multiplier orp (〃). The finite body constant multiplier 17 of w). 12 201035781, Ie's more (four) 8 circuit as an example to illustrate the action 2 of the root-seeking circuit 4: two is a positive even number, and the order-operator TCr included in the first computing device 41 is an odd-order, the first _ , 5 τρ ^ θ The step operator TCr included in the sputum device is an even order. In the first cycle: the step operator TCr of the computing device 4, 42 will send the corresponding coefficient VIII by the multiplexer 16, and then the Ps operator TCr of all the sub-vibrators vi-p, v2, It will be multiplied. Also, the collation operator 29 sends a value of 1 for all the collating operators to multiply α-ρ. Next, for the computing device 41 and the first sub-calculator V1_p, the corresponding finite-body adder 14 assembles the correlation-order operator TCr to form a first value signal. For the computing device 42 and the second sub-calculator _P, the corresponding finite-body adder 14 combines the comparison operation 5| 29, Ep and the correlation-order operator TCr to form a second numerical signal.

Finally, the comparators 13, JG_p only have to wait for the computing device 41 and the first sub-calculator V1-P to collect the completion of the odd-order operator TCr, or wait for the computing device 42 and the second sub-clock V2. By collecting the rounds of the comparison operator 29' Ep and the even order operator TCr, it is possible to perform an alignment to determine whether or not the non-zero element W is the root of the polynomial. In the second cycle: 201035781

Tcr' will send ^8〃 by the order operator of the multiplexer 16 V1_P, V2_p, and then the sub-calculator TCr will multiply ap(r_- „). For all pairs, the comparison operator 29 will take the α-Ρ value operator to multiply the ^-factor. Finally, the comparator 13 ' JG element αΡ+ρ is the root of the polynomial A comparison is made to determine: non-zero and subsequent cycle operation, and so on, until all non-zero elements W-1 are fully tested. In summary, this example can reduce the number of overall inspection cycles as shown in Figure 3. The circuit, and the time of each cycle is halved by the separation of the odd-even steps. Of course, the practical application, the computing devices 41, 42 and the sub-processors, V2_p may not limit the configuration of all the order operators by the odd-even order' As long as the equal-order operation n TQ' is arranged in the two computing devices 41, 42 or in the sub-calculators V1_p, V2_p +, the effect of _short-period time can be achieved. The operator TCr receives the output of the same-multiplexer, so these orders The controller TCr can share the circuit components by the conventional group matching method. Similarly, the comparison operators 29 and Ep can be shared to reduce the use of the hardware circuit. Traveler 1 as shown in Figure 9, in order to reduce the use of the finite-body multiplier 17 14 201035781 The fifth preferred embodiment replaces the step operator TCr of the sub-calculators V1_p, V2-p with a shifter Compared with the fourth preferred embodiment, the main difference of the fifth preferred embodiment of the root-seeking circuit 5 of the present invention is that the first-order sub-calculators Vl-P and V2-P are used. There is only one shifter 58 to shift the output of the corresponding multiplexer to the left (r, _u) xp, and the bit length of the product of the order product is increased (r, _u) xp. Please note that this example shifter The shift length of 58 can indirectly affect the number of XORs used by the finite body adder 14 as a function of u, which is different from the conventional circuit of Fig. 3. () Sub-units Vl_p, V2_p except for the existing finite body adder 14 And the equal-order operator TCr, in addition, there is also a correction circuit Μ a set of correlation-order operators TCr in the finite-body adder 14 Thereafter, the signal corresponding to the adjustment value and the compensation bit length, to the comparator JG_p retransmission.

Next, explain the reasons for these two differences. There is a general knowledge in the field of the invention (4) solution: for the multiplication of GF(2m)" 70 γ of each non-zero element of 1 to π-1 has a closed property. That is, (four) non-zero ^ = Gain = Product result will be equivalent to one of the "non-zero ones, and the resulting product of the result of the product divided by T „ π Α κ is still m. This implies that Γ53 / binary (four) step, also It is necessary to cooperate with the correction power to the bit length result 1 to satisfy the function of the finite body constant 201035781 multiplication method ^ 17. How the correction circuit 53 compensates the output of the shifter % is a common knowledge in the art, so this article will not repeat them. In the sub-calculators V1_P, V2_p, the operation time and the realized area (number of jobs) of each finite-body adder 14 depend on the bit length after the shift of the correlation-order operator TCr'. The difference in the lengths of the elements increases, and the operation time of the corresponding finite body adder 14 is lengthened, and the area of the implementation is increased. Therefore, in this example, the step operator TCr of the ^R/2th order is preferably arranged. - a computing device 51 and a sub-calculator Vi-p towel, and (10) Step operator TQ of +1) to Rth order is arranged in the second calculation and the second sub-calculator V2_p. Further, in order to further reduce the length of the second sub-rectifier 四 (four) bit, the _+1 The order operation @ of the R order is reduced by (R/2)xp shift length, ie: reduced to (r, -R/2-u) Xp, and each second sub-calculator V2-P further includes - a common factor multiplication 3 54, receives the output of the corresponding correction circuit 53 to multiply 〇^/2, and then supplies it to the comparator. It is worth noting that the second sub-calculator V2_p adds the common factor multiplier 54 However, the second calculation crack 52 does not increase synchronously. Therefore, according to the exchange characteristic of the finite body addition, the comparison operators 29 and EP are moved to the first calculation device 51 and the first sub-calculator νι-p. Further, in the other embodiment, the comparison operators 29, Ep of the third to fifth embodiments may be electrically connected to the comparator 13' and the comparator 13 is changed by the output based on the comparison operator 29, EP. The first-value signal and the second value signal of 16 201035781 are used for the judgment. The embodiment divides the equal-order operators TCr, TG into two computing devices, 31~51, 12~52 or two sub-calculators Vim to reduce the operation time per cycle. Under such a configuration, the multiplier of the finite body constant multiplier 17 is changed, or the finite body constant multiplier 17 is replaced with the shifter 58 to reduce the hardware circuit, so that the object of the present invention can be achieved by breaking.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent change of the patent scope and the description of the invention in the present invention is Modifications are still within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a conventional circuit for implementing the Chien search method; FIG. 2 is a block diagram showing a conventional circuit of parallelization concept; FIG. 3 is a block diagram showing parallel 4 is a block diagram of a first preferred embodiment of the root-seeking circuit of the present invention; FIG. 5 is a block diagram of a second preferred embodiment of the root-seeking circuit of the present invention; FIG. 7 is a block diagram showing a fourth preferred embodiment of the present invention; FIG. 8 is a block diagram showing a fourth preferred embodiment of the root-seeking circuit of the present invention; Figure 9 is a block diagram of a fifth preferred embodiment of the root-seeking circuit of the present invention. 17 201035781 [Description of main component symbols] 1 to 5 Rooting circuits 31, 11 to 51 ... First computing device 32, -... 12 to 52 • Second computing device 53 13 Comparator 54' 14 ... Finite body adder 58 · 16 multiplexer D 17...'...finite body constant multiplier Ep-·· 21. calculation device JG_p 28*· area estimator TC 1 2 9 ° ^ comparison operator Vl_p 3, root finding circuit V2_p • first calculation Device. Second Computing Device Correction Circuit Common Factor Multiplier Shifter Register • Comparison Operator - Comparator Step Operator First Sub Calculator - Second Sub Calculator 18

Claims (1)

201035781 VII. Patent application scope: -丨· A root-seeking circuit, which is suitable for testing whether a non-zero element belongs to the root of an R-order polynomial, comprising: a computing device, comprising: (R-1) rank operators, each The order operator corresponds to the -order of the selected order in the polynomial, and generates a first-order product according to the coefficient of the corresponding order; and a finite body adder receives the 〇-order product generated by all the order operators and the selected order A coefficient forms a numerical signal; and a comparator aligns with the numerical signal with a selected reference value for the selected order to determine whether the non-zero element belongs to the root of the polynomial. 2. The root finding circuit according to the scope of the patent application scope, wherein when the selected order is u and 幺/?, the selected reference value is the (-u) power of the non-zero element; The operator has a finite body constant multiplier that multiplies the coefficient of the corresponding order by a multiplier to produce the product of the order and for the step operator of the relevant rth order, the multiplier is the (ru) power of the non-zero element Square, 1幺 3. According to the root-seeking circuit described in claim 2, it is more suitable to check whether another non-zero element belongs to the root of the polynomial, wherein each-order operator has: 'Receiving the 19 201035781 憝 product generated by the finite body constant multiplier and outputting after one cycle; and, - multiplexer, selecting to output the output of the register or the corresponding order coefficient for the limited The operation basis of the body constant multiplier: at the first cycle, each multiplexer is the coefficient of the corresponding order: the output '^ is the corresponding finite body constant multiplier to generate the product of the non-zero element', for the order product The finite body adder is formed The non-zero element ^ = 1⁄4 ' and the comparator is used to determine whether the non-zero element belongs to the root of the polynomial; ^ in the second cycle, the multiplexer is the finite material (four) method providing the register And the corresponding (4) constant multiplier produces a product of the order of the other non-love; each &# + non-zero, so that the comparator makes a judgment on the other non-zero element. 4. According to the root circuit described in claim 1 of the claim patent, a pair of ', , and from ' generates a selected reference value for the comparator to determine. 5. According to the patent application scope, the minority operation n has: a read circuit of the item material, and further includes a pair of - register holders to receive the selected reference value used by the comparator for judgment, and output after one cycle; 'selects the output of the register, or outputs a value of 1, a finite constant multiplier to update the selected reference value u) power; multiply the output of the multiplexer by a multiplication The multiplier is the non-zero element (- 20 201035781. In the first cycle, the multiplexer is a value of 1 and the finite body constant multiplier generates a '', and the benefit is about the non-zero element The selection is for the comparator to determine the root; whether the non-zero-prime belongs to the polynomial two cycles, the multiplexer selects the temporary storage and the finite body constant multiplier updates the selection Reference value, 6. The comparator makes a judgment on the other-non-zero element. VIII~:=艮 circuit 'applies to verify whether a non-zero element belongs to the root of _ r ming polynomial, comprising: a first computing device, comprising: S throttling devices, each ordering operator corresponding to the polynomial Except for the selected order of the order and generating a first-order product according to the coefficient of the corresponding order, 1^</?; and a finite body adder, receiving the product of the s-order operator and the selected order a coefficient of the first numerical signal; a second computing device comprising: (R-1-S) rank operators, each of the operators corresponding to a first order of the selected order of the polynomial, and Generating a first-order product according to the coefficient of the corresponding order; and a finite body adder 'receiving the product of the (r_ 1 _S) order operator and a selected reference value for the selected step to form a second value And a comparator that compares the first value signal with the second value signal 21 201035781 ' to determine whether the non-zero element belongs to the root of the polynomial. 7. The root-seeking circuit according to claim 6, wherein when the selected order is u and 沢, the selected reference value is a (-u) power of the non-zero element; each stage operator has a A finite body constant multiplier that multiplies the coefficient of the corresponding order by a multiplier to produce the product of the order, and for the order operator of the relevant second order, the multiplier is the power of the non-zero element, 1幺8. The root-seeking circuit according to claim 7 of the patent application scope is more suitable for testing whether another non-zero element belongs to the root of the polynomial, wherein each level operator further has: a register, receiving the finite body The multiplication product generated by the constant multiplier is output after one cycle; and the multiplexer 'selects the output of the register or the coefficient of the corresponding order for the operation basis of the finite body constant multiplier For output, the corresponding finite body constant multiplier produces a product of the order of the non-zero element, and 毋 毋 & ... ea . At the root of the polynomial; When the other donor is about the other, the multiplexer is to provide the output multiplier of the register, and the corresponding finite body constant multiplier produces a non-zero order product of the multiplicity, so that the comparator performs the pair 22 201035781 The judgment of this other non-zero element. • The root-seeking circuit described in item 6 of the scope of the patent application further includes a pair of knowers and operators for generating the selected reference value. 10. The root-seeking circuit according to item 8 of the patent application scope, further comprising a comparison operator, having: - a temporary register receiving the selected reference value and outputting after one cycle; a multiplexer, selecting to output the The output of the register, or the output 1 〇 value; - the finite body constant multiplier, multiplying the output of the multiplexer by a multiplier 'to update the selected reference value' and the multiplier is the non-zero element ( _ U) power square; • at the first cycle, the multiplexer outputs a value of 1 and causes the finite body constant multiplier to generate a selected reference value for the non-zero element for the finite body addition Forming a second value signal for the non-zero element, and causing the comparator to determine whether the non-zero element belongs to the root of the polynomial; in the second cycle, the multiplexer selects the output of the register, and The finite volume constant multiplier updates the selected reference value for the comparator to make a determination of the other non-zero element. 11. The root-seeking circuit according to item 6 of the patent scope is more suitable for simultaneously testing another-non-zero element, wherein when the selected order is U, the selected reference value is (_2u) of the non-zero element. a power of the power, and the multiplier used by the first- and second-order computing devices is a 2 (ru) power of the non-zero element 201035781, and the root-seeking circuit further includes: a first sub-calculator, The method includes: an S-order operator, respectively receiving an output of a corresponding multiplexer from the first computing device, and generating a first-order product; and a finite-body adder, receiving a step product generated by the s-order operators And a coefficient of the selected order to form a first value signal; a second sub-calculator comprising: (Ris) level operator, respectively receiving the output of the corresponding multiplexer from the second computing device, and according to To generate a first-order product; and 'a finite body adder, receiving a multiplicative product generated by the (r-u)th order operator and a selected reference value for the selected order to form a second numerical signal; and a comparison , the comparison comes from The first value signal of the second sub-routine and the second value signal from the first sub-calculator determine whether the other non-zero element belongs to the root of the polynomial. 12. The root-seeking circuit according to claim 5, wherein each of the two sub-calculators has a finite-body multiplier that multiplies the corresponding multiplexer by a multiplier The output produces the product of the order, where the multiplier is the (ru) power of the non-zero element. 13. The root-seeking circuit according to the scope of claim 5, wherein the two sub-calculators +, each-order operator has a shifter, shifting the output of the corresponding multiplexer to the left (r_u), and The length of the bit product 24 201035781 is increased (ru); the one sub-calculator further includes a correction circuit, which adjusts the corresponding numerical signal and compensates the bit after the corresponding finite body adder set related order operator The length is sent to the comparator. 14. The root-seeking circuit according to claim n, wherein the first §·[· computing device and the first-level calculator comprise a step-operator belonging to the first to the R/2th order, and The second computing device and the second arithmetic unit include a step operator belonging to the (r/2 + 1)~r order; and each of the first arithmetic operators has a shift Transmitting the output of the corresponding multiplexer to the left (r_u), and increasing the bit length of the step product by (ru); each second-level calculator has a shifter for the corresponding The output of the multiplexer is shifted to the left (r_R/2_u), and the bit length of the multiplicative product is increased (rR/2-u); and the second sub-calculator further includes a common factor multiplier for receiving the Dong The output of the circuit should be corrected by multiplying the (R/2) power of the non-zero element and then sent to the corresponding comparator. 15. The root-seeking circuit according to claim 6, wherein the first computing device includes an order operator, and the second computing device includes an order operator.