TW201036342A - Root-finding circuit - Google Patents
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201036342 六、發明說明: 【發明所屬之技術領域】 本發明是有關於一種代數運算技術,特別是指—種用 以實現錢氏搜尋法(Chien Search)的尋根電路。 【先前技術】 以 的 置201036342 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to an algebraic computing technique, and more particularly to a root-seeking circuit for implementing Chien Search. [prior art]
〇 錢氏搜尋法主要用途為:求出一多項式的根的), 利於多項式的因式分解。常見用於可更正隨機位元錯誤 李德所羅門(Reed Solomon,RS)解碼器,來分析一錯誤位 多項式而找出發生錯誤的位置。 個(n,k,d)編碼信號,其碼長η d~l 假設RS解碼器接收了 位元 位元’實際資訊長度k位元,可糾錯容量為及 其中L\l代表:小於等於I的最大正整數。那麼&s2解」碼器可 根據此編碼信號產生一階數最多為R的錯誤位置多項式 (error-locator p〇lynomial)w方程式(1)所示接著運用錢氏 搜尋法將加洛瓦體GF(n的N個非零元素(n〇nzer〇 element)iAQfl,a2—1 一一代入,來檢驗得知哪些非零元 素是屬於錯錄置乡項式的根’且所有檢驗運算都是建立 在為有限體的加洛瓦體GF(2m)上。其中,N=2mi, η=0,1,2··.(Ν-1),且錯誤位置多項式的常數項係數Λ〇 = ι,各 階係數分別為Λι、λ2...Λ/?。 r=〇 r=i 、丄’ ,閱圖1,其顯示了實現方程式(i)的電路圖。當一非零 3 201036342 元素β傳入這個 分別為該非零元 中,即可藉由R個有限體乘法器71 合相加成-數Jr且做運算,再由加法器72集 否為1來_心零元二較=會依據該數值信號是 進而決定發生料置㈣式的根, 期繼續驗證另—非零爾後’圖1的電路會在下-週 N個週期才能但是,這樣的電路必須耗費 於解碼效率成所有非零元素的檢測,相當不利 -個=二術提出了平行化的概念(如圈2>,使在 門大檢驗其巾?個非零元素6藉以將檢驗時 二敕愈減為㈣週期,其中Μ代表:大於等於X的最大 -。並且’另-習知技術更將圖2電路化簡成圖3,企 圖降低每-週期的操作時間。可惜,改善程度有限。 综觀圖1〜3,不難發現:針對每一非零元素比較器 73都是等到計算出該數值信號(含有該非零元素〆的第卜& 階)後’才將所得的數值信號與们做比較。這意味著,比 較器73、83、93的等待時間相當長,連帶地影響了每一週 期的操作時間,也是解碼效率低落的一大主因。主要 The main use of the Qian search method is to find the root of a polynomial, which is beneficial to the factorization of polynomials. Commonly used to correct random bit errors The Reed Solomon (RS) decoder analyzes an error bit polynomial to find out where the error occurred. (n, k, d) coded signal, its code length η d~l assumes that the RS decoder receives the bit bit 'actual information length k bits, the error correctable capacity is and its L\l represents: less than or equal The largest positive integer of I. Then the &s2 solution can generate an error-locator p〇lynomial w equation (1) according to the coded signal, and then use the Chiss search method to add the Galois body. GF (N non-zero elements of n (n〇nzer〇element) iAQfl, a2—1 are substituted one by one to verify which non-zero elements belong to the root of the misplaced homering term and all the test operations are It is based on the finite volume of Galois GF(2m), where N=2mi, η=0,1,2··.(Ν-1), and the constant term coefficient of the error location polynomial Λ〇= ι, the coefficients of each order are Λι, λ2...Λ/?. r=〇r=i, 丄', and Figure 1, which shows the circuit diagram for implementing equation (i). When a non-zero 3 201036342 element β Into this non-zero element, the R finite multipliers 71 can be combined and added to the number Jr and the operation is performed, and then the adder 72 is set to 1 or not. The value signal is then determined to determine the root of the material (4) type, and the period continues to verify another - non-zero after the circuit of Figure 1 will be in the next - week N cycles. However, such a circuit It is necessary to consume the decoding efficiency into the detection of all non-zero elements, which is quite unfavorable - one = two techniques put forward the concept of parallelization (such as circle 2), so that the inspection of the towel at the gate is a non-zero element 6 The recovery is reduced to a (four) cycle, where Μ represents: greater than or equal to the maximum of X. And 'other-known technology further simplifies the circuit of Figure 2 into Figure 3, in an attempt to reduce the operating time per cycle. Unfortunately, the improvement is limited. Looking at Figures 1 to 3, it is not difficult to find that for each non-zero element comparator 73, the numerical signal obtained after the calculation of the numerical value signal (containing the non-zero element 第 卜 & Compared with them, this means that the waiting time of the comparators 73, 83, and 93 is quite long, which affects the operation time of each cycle, and is also a major cause of the low decoding efficiency.
此外’雖然圖2和圖3電路的檢驗週期數目都較圖i 大為縮減,但是硬體電路數目幾乎是圖1的P倍,實現成 本過高。鑑於此,陸續也有其他改善方式被提出,譬如: Chen 矛〇 Parhi ^ IEEE TRANSACTIONS ON VERY LARGE SCAL五 /iV7^G/?A770A^V^/) 2卯4 中提出的以交 迭匹配(Iterative Matching)和群組匹配(Group Matching)方式 201036342 來共用運算電路’又譬如:Cho和Sung於/從五 TRANSACTIONS ON CIRCUITS AND SYSTEMS-Π, 2008 t it 議以移位器(shifter)來取代有限體的乘法運算。只是在圖2 、3的架構下,這些做法都無法有效地減輕實現成本的壓力 【發明内容】 因此’本發明之目的,即在提供一種可以縮減根檢驗 時間並降低硬體電路成本的尋根電路。In addition, although the number of inspection cycles of the circuits of Figs. 2 and 3 is much smaller than that of Fig. 1, the number of hardware circuits is almost P times that of Fig. 1, and the implementation cost is too high. In view of this, there are other improvements that have been proposed, such as: Chen Spears Parhi ^ IEEE TRANSACTIONS ON VERY LARGE SCAL V / iV7 ^ G / ? A770A ^ V ^ /) 2 卯 4 proposed in the overlap matching (Iterative Matching ) and group matching (Group Matching) method 201036342 to share the arithmetic circuit 'for example: Cho and Sung in / from five TRANSSACTIONS ON CIRCUITS AND SYSTEMS-Π, 2008 t it to replace the finite body with a shifter Multiplication operation. However, under the framework of FIG. 2 and FIG. 3, these practices cannot effectively alleviate the pressure of the implementation cost. [Inventive content] Therefore, the object of the present invention is to provide a root-seeking circuit capable of reducing the root-checking time and reducing the cost of the hardware circuit. .
於是,本發明尋根電路,適用於檢驗一非零元素是否 屬於-個R階多項式的根,包含:—第—計算裝置,包括 :S個階運算器,每—階運算器對應該多項式的其中一階, 且根據該對應階的係數產生_階乘積,及一個有 限體加法器,接收豸s個階運算器產生的階乘積,而形成 一第-數值信號,·-第二計算裝置,包括:(Rs)個階運算 器’每-階運算器對應該多項式的其中一階,且根據該對 應階的係數產生-階乘積;及—個有限體加法器,接收該 ㈣Μ固階運算器產生的階乘積,而形成―第:數值信號; 及一比較器’比對該第一數值信號與該第二數值信號,以 判斷該非零元素是否屬於該多項式的根。 【實施方式】 ,在 將可 有關本發明之前述及其他技術内容'特點盥〕 以下配合參考圖式之五個較佳實施例的詳細說明, 清楚的呈現。 5 201036342 在本發明被詳細描述之前,要注意的是,在以下的說 明内容中’類似的元件是以相同的編號來表示。 第一較佳膏施你丨 為了縮短比較器的等待時間以降低每一週期的操作時 間,本發明提出一摺疊(folding)架構,將多項柄r階區分 成兩部份,並為每-部份計算出一數值信號。再由比較器 比對該二數值信號來做判斷。Therefore, the root-seeking circuit of the present invention is adapted to verify whether a non-zero element belongs to the root of the -R-order polynomial, and includes: - a first computing device, comprising: S-order operators, each of which corresponds to a polynomial First order, and generating a _ order product according to the coefficient of the corresponding order, and a finite body adder, receiving a step product generated by the 豸s level operator to form a first-value signal, the second computing device, including : (Rs) rank operator 'per-step operator corresponds to one of the polynomials, and generates a -th order product according to the coefficient of the corresponding order; and a finite body adder receives the (four) Μ fixed-order operator The step product is formed to form a "first: value signal; and a comparator" compares the first value signal with the second value signal to determine whether the non-zero element belongs to the root of the polynomial. [Embodiment] The foregoing and other technical contents of the present invention will be clearly described in the following detailed description of the preferred embodiments with reference to the drawings. 5 201036342 Before the present invention is described in detail, it is to be noted that in the following description, similar elements are denoted by the same reference numerals. In order to shorten the waiting time of the comparator to reduce the operation time of each cycle, the present invention proposes a folding architecture, which divides the multi-step r-order into two parts, and for each part A numerical signal is calculated. The comparator then determines the binary signal.
參閱圖4,本發明尋根電路之第—較佳實施例適用於從 加洛瓦體叫2、N個非零元素« H 於一個R階多項式的根。該尋根電路i包含—第一叶算裝 置U、—第二計算裝置12及―比較器13。第 包括s個階運算芎Tc 寸异裒置 μ 有限體加法器14,而第二 ;4。= 括㈣)個階運算器%及-偏有限體加法器 ,、中,:-階運算器TCr分別對應多項 具有一多工器16、一暫在 立 …〜=1’2,』 及-有限體常數乘法器17, 較佳地,使S,/2」而令 的運算’並令第二 十异裝置11負貝奇數階 化每一週期的操作時間。在^負責偶數階的運算,能最小 ^是多項式的根,且多項^㈣的安排下’假設非零元素 分別為W那麼::數項係數八。=1,各階係數 丨麼非零疋素y合 .R 身 則可得方程式⑶0 ;、()田進 金八#771 = 1 r=l (2) 201036342Referring to Figure 4, a preferred embodiment of the root-seeking circuit of the present invention is applicable to the root of a R-order polynomial from the Galois body, 2, N non-zero elements «H. The rooting circuit i includes a first leaf computing device U, a second computing device 12, and a "comparator 13." The first includes s-order operations 芎Tc-inch 裒 μ μ finite body adder 14, and second; = (4)) The order operator % and the partial finite body adder, the middle, the --order operator TCR respectively correspond to a plurality of multiplexers 16, a temporary erection...~=1'2, 』 and - The finite body constant multiplier 17, preferably, makes the operation of S, /2" and causes the twentieth device 11 to negatively sequence the operation time of each cycle. In ^ is responsible for even-order operations, the smallest ^ can be the root of the polynomial, and the multiple ^ (four) arrangement under the assumption that the non-zero elements are respectively W:: number of coefficients eight. =1, the coefficients of each order 丨 非 非 非 非 y . . R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
R Σαα r:odd ι+ revert,r>2 (3) 四 rfrj 階運算器TCr中 虿隈體常數乘法器17 乘數並將其乘上多玉1116輸“得到-階_,且多工 器16在第-個週期是以係數“輪出,而其餘週期則是選 取暫存器D輸出。並且’有限體常數乘法器17完成乘法運 异後,會將階乘積送往對應的有限體加法_ 14,也會將其 oR Σαα r:odd ι+ revert,r>2 (3) Four rfrj-order operator TCr in the body constant multiplier 17 multiplier and multiply it by the multi-jade 1116 to get the -order _, and the multiplexer 16 is in the first cycle with the coefficient "round, while the rest of the cycle is to select the register D output. And after the finite body constant multiplier 17 completes the multiplication operation, the step product is sent to the corresponding finite body addition _ 14, which will also be o
存器D中。且暫存器D會延遲-個週期後再將储 存值輸出。 根據方程式⑶,第一計算裝置11的有限體加法器14 會加總所有奇數階之階運算器TQ的階乘積而得到—第一數 值信號;第二計算裝置12的有限體加法器14會在加總所 有偶數階之階運算H TCr的階乘積後,再加上常數項係數 Λ〇的1值而得到一第二數值信號。 然後’比較器13再比對第—數值信號是否吻合第二數 值信號’以判斷:非零元素y是否真的是多項式的根。詳 細來說,在兩數值信號吻合時,比較器13會判斷非零元素 V的確是該多項式的根;而不吻合時,則判斷為否。 當然’在另-實施例中,第二計算裝置12的有限體加 法器14可以只加總所有偶數階階運算器了^的階乘積,來 得到該第二數值信號。而比較器13則是基於第一數值信逯 、第二數值信號以及常數項係數Λ()=1,來進行比對判斷。, 值得注意的是,在第一個週期時,每一有限體常數乘 法器17會因為接收係數\而產生階乘積為八〆,所以此時 201036342 該有限體加法器14會形成關於非零元素y的數值信號,以 供比較13驗證非零元素αι。在第二個週期時,每一有限 體常數乘法器17會因為接收階乘積Λ〆而更新階乘積為 Ar« ,以供比較器13驗證非零元素α2。以此類推。 且值得注意的是,本較佳實施例的比較器13只需要等 候一段計算涵蓋奇數階之第一數值信號的時間,或是等候 一段計算涵蓋偶數階之第二數值信號的時間,因此能較習 知技術實質地縮短每一週期的操作時間。 更值得注意的是,當本較佳實施例應用於RS解碼器, 由於在找出發生錯誤的位置後,還需根據多項式的微分來 計算錯誤值。而在有限體的運算下,屬於偶數階的微分結 果會等效為0,所以當選取奇偶階分離的架構(如圖4)時, 更可以直接採用涵蓋奇數階之第一數值信號來求取相關錯 誤值,使間接地簡化了用以計算錯誤值的電路。 篇二較佳實施你丨 參閱圖5,本發明尋根電路之第二較佳實施例包含一計 算裝置21及一比較器13。計算裝置21包括個階運算 斋TCr’及一個有限體加法14。其中,每·一階運算号TC, 均類似於第一較佳實施例的階運算器TCr,而r,的定義會於 稍後說明。 由於每一階運算器TCr’所具有的有限體常數乘法器17 會因為其乘數,而決定乘法電路的複雜度,所以本例試圖 改變該等對應的乘數來降低電路成本。假設非零元素y是 201036342 多項式的根(見方程式(2)),本例是使計算裝置21接收一選 定階u ’並將將方程式(2)除以,(匕仏及)來求得方程式⑷ 〇 (4)In the D. The register D will be delayed by - one cycle before the stored value is output. According to equation (3), the finite body adder 14 of the first computing device 11 adds up the product of the order of all odd-order step operators TQ to obtain a first value signal; the finite body adder 14 of the second computing device 12 will After adding the order product of all even-order order operations H TCr , a value of 1 of the constant term coefficient Λ〇 is added to obtain a second value signal. The 'comparator 13 then compares the first-value signal to the second-numbered signal' to determine if the non-zero element y is really the root of the polynomial. In detail, when the two numerical signals match, the comparator 13 judges that the non-zero element V is indeed the root of the polynomial; if it does not match, it judges as no. Of course, in another embodiment, the finite volume adder 14 of the second computing device 12 may only add the order product of all even-order operators to obtain the second value signal. The comparator 13 performs the comparison determination based on the first numerical signal, the second numerical signal, and the constant term coefficient Λ()=1. It is worth noting that, in the first cycle, each finite body constant multiplier 17 will produce a factor product of eight 因为 due to the reception coefficient \, so at this time 201036342 the finite body adder 14 will form a non-zero element. The numerical signal of y for comparison 13 to verify the non-zero element αι. At the second cycle, each finite body constant multiplier 17 updates the order product to Ar« by receiving the step product Λ〆 for the comparator 13 to verify the non-zero element α2. And so on. It should be noted that the comparator 13 of the preferred embodiment only needs to wait for a period of time to calculate the first numerical signal covering the odd order, or wait for a period of time to calculate the second numerical signal covering the even order, so Conventional techniques substantially shorten the operating time of each cycle. More notably, when the preferred embodiment is applied to an RS decoder, the error value is calculated based on the differentiation of the polynomial after finding the location where the error occurred. In the case of finite-body operations, the differential result belonging to the even-order order is equivalent to 0, so when the architecture of the odd-even separation is selected (as shown in Fig. 4), the first numerical signal covering the odd-order order can be directly used to obtain The associated error value simplifies the circuit used to calculate the error value indirectly. The second preferred embodiment of the present invention includes a computing device 21 and a comparator 13. The computing device 21 includes a rank operation TCr' and a finite body addition 14. Here, each of the first-order operation numbers TC is similar to the order operator TCr of the first preferred embodiment, and the definition of r, which will be described later. Since the finite body constant multiplier 17 of each order operator TCr' determines the complexity of the multiplying circuit because of its multiplier, this example attempts to change the corresponding multiplier to reduce the circuit cost. Assuming that the non-zero element y is the root of the 201036342 polynomial (see equation (2)), this example is to cause the computing device 21 to receive a selected order u ' and divide the equation (2) by (匕仏) to find the equation. (4) 〇(4)
1=1 i=l K J 如此,第二較佳實施例將可隨選定階u改變乘數,並 能省略階運算器tcu的使用,也就是說,計算裝置21只需 包括(R-1)個階運算器TCr,,r,= 1,2,...R但r,扣。且此時, Ο 比較器13是以一選定參考值來做比對,這不同於第一 較佳實施例所選用的1值。 值得注意的是,因為有限體常數乘法器17等效於多個 加法器的集合,且依乘於不同的常數,會對應不同個數的 加法器數量。而本例巾,料有限體f數乘法^ 17的乘數 都是《的冪次方,所以可更換不同的選定階u(1,以 最小化加法器(即:互斥或(x〇R)閘)的使用數量,進而降低 尋根電路2的實現電路成本。 〇 當然,本例的尋根電路2還可包含—用以提供選定階u 的面積評估器28,會先對方程式⑷中每_α的幂次方數目 取絕對值,接著加總所有絕對值得到一如方程式(5)的面積 指標,再據以選出複數個使面積指標較小化的u來供計算1=1 i=l KJ As such, the second preferred embodiment will change the multiplier with the selected order u and can omit the use of the level operator tcu, that is, the computing device 21 only needs to include (R-1) The rank operator TCr,,r,= 1,2,...R but r, buckle. At this time, the Ο comparator 13 is compared by a selected reference value, which is different from the value of 1 selected for the first preferred embodiment. It is worth noting that since the finite body constant multiplier 17 is equivalent to a set of multiple adders and multiplied by different constants, it will correspond to a different number of adders. In this case, the finite body f-number multiplication ^ 17 multiplier is the power of the power, so you can replace the different selected order u (1, to minimize the adder (ie: mutual exclusion or (x〇R The number of gates used, which in turn reduces the circuit cost of the root-seeking circuit 2. 〇 Of course, the root-seeking circuit 2 of this example can also include an area estimator 28 for providing the selected order u, which will first be used in the other program (4) The number of powers of α takes the absolute value, then adds all the absolute values to obtain the area index of equation (5), and then selects a plurality of u which make the area index smaller.
裝置21更換選用。此外,因為省略了階運算器TCu,所以 面積指標也可以不包含卜—。 U = |- un\ + \-(u- l)n\ +... + |(i? - u)n\ ⑸ y 201036342 且在取絕對值的過程中,基於加洛瓦場GF(2m)的幕次 方計算,存在(其中的關係,所以當 w>o,I—叫可以表示為州-m。 更值得注意的是,比較器13用以比對的選定參考值 a疋個可預先计真的值,且此值會隨著η而改變。當然 ,在另一實例中,也可以不做預先的計算,而改用—個對 照運算器29來產生此值。 對照運算器29具有一多工器16、一暫存器!)及—有限 體常數乘法器17’且動作方式類似於階運算器TCr,。其中 ’有限體常數乘法H Π是以纩“乘上多工器16輸出,且多 工器16在第一個週期是以1值為輸出。因此,當尋根電路 2在第一個週期檢驗非零元素“,有限體常數乘法器η會 根據多工$ 16之輸出(1值)來產生選定參考值γ。而在第 二個週期檢驗非零元素,多卫器16會選擇暫存器D的輸 出,且有限體常數乘法器17會據以將選定參考值更新為 。以此類推。 一 * 第三較佳竇搞.你丨 參閱圖6,第三較佳實施例統合了前兩個實施例的精神 ,而將該等階運算器扣,區隔到兩個計算裝置Μ、%以降 低每-週期的操作時間,並改變有限財數乘法器17的乘 數來達成降低電路成本的目的。 本發明尋根電路3之第三較佳實施例所包含元件大致 10 201036342 _ 實㈣(圖4)’但其中 (. 、甲有二項不同處· (一) 階運算器TCr,的乘數為α(〜)。 (二) 省略了階運算器Tc 係數Λ„是直接傳入有限體 加法器14。 (三) 第二計算裝置32中,有限妒 负限體加法器14除了接收所 有偶數階階運算器TC ,的輅山 ^ i、,的輸出,更接收了選定參 考值α’。此點不同於笛 ^ U於弟—較佳實施例中所接收的 Ο 1值。 為了方便前段說明,圖6是取R為偶數,u為大於3的 奇數來緣製。但實際應用上,R可以是任意正整數且 。舉例來說’ U值也可以等於i,且此時尋根電路3, 的架構如圖7所示。 再者,也可以如前例般採用一對照運算器29來產生選 定參考值並且,基於有限體加法運算的交換性,對照 運算器29也能改成配置於第一計算裝置31中。 此外,第 第二較佳實施例中,由於電路實作上階運 算器TCr、TCr’佔用到大部份的電路面積,而在各個階運算 器TCr、TCr’中所使用的有限體常數乘法器17具有可共用 的電路結構’所以可以根據習知的交迭匹配(Itemive Matching)方式來共用電路元件以有效降低電路成本。 第四較佳實施例 第四較佳實施例則是引進了平行化的概念,而將圖7 11 201036342 架構更改成圖8,使得在單一週期内能完成P個非零元素y 的檢驗,P>1。 相較於第三較佳實施例,本發明尋根電路4之第四較 佳實施例更包含OM)個第—子計算器V1_p、(pi)個第二子 計算器V2_p及OM)個比較器JG_p,ρ=1,2,(ρι)。 每一個第一子計算器V1-P包括S,個階運算器TCr,及一 個有限體加法器14,而每一個第二子計算器V2—p包括一個 ,照運算n Ep、(R小s,)個階運算器Tcv及—個有限體加法 器 14,且 1《S’<(R-1),r,= 1,2,R 但 r,其u。 其中,子計算器V1-P、V2-P的階運算器TCr,分別具有 —採用乘數〜 > 的有限體常數乘法器17。另一方面,值得 注意的是’計算裝置41、42的階運算器瓜類似於第三較 佳實施例,而具有一多工器16、一暫存器D及一採用乘數 α ^ 的有限體常數乘法器17。 接下來,更以圖8電路為例來說明尋根電路4的動作 ,假設u=l、R為正偶數,且第一計算裝置41所包括的階 運算器Tcr,都是奇數階,第二計算裝置42所包括的階運算 器TCr,都是偶數階。 在第一個週期時: 計算裝置41、42的階運算器TCr,會藉由多工器16 送出對應的係數Ar, ’然後所有子計算器V1_p、V2_p 的階運算器TCr,會據以乘上。 並且,對照運算器29會送出丨值,以供所有對照 運算器Ep據以乘上“^。 12 201036342 著’對計算裝置41與第-子計算器νι ρ來^ 形成騎限體加法器14會集合相關階運算器%,而 vl 一第一數值信號。對計算裝置42與第二子計算器 二來說,對應有限體加法器14會集合對照運算器 。p與相關階運算器TCr,,而形成_第二數值信號 Ο 第後三比較器13、JG_P只須等待計算裝置41與 叶算器Vl_p收集完成奇數階階運算器τ ,或是等待計算裝置42與第二子計#3! V2 明 完成對日3 卞"卞异器V2一P收集 ,就」、、、運算II 29、Ep與偶數階階運算器扣的輪出 的根^料對㈣❹:料元素^否為多項式 在第二個週期時: 汁算裝置41、42的階運算器TCr,會藉由多工器 〇 送出’Μ人,,然後所有子計算器V1_p、V2』的階運 算器Tcr,會據以乘上〇rp(r_-M)。 並且,對照運算器29會送出值,以供所有對 照運算器Ep據以乘上α-ρ。 最後’再由比較器13、JG_p來比對判斷出:非零 元素〆+p是否為多項式的根。 且隨後週期的運作,以此類推,直到完全檢驗所有非 零元素。綜上,本例不但整體檢驗週期數目可減少 13 201036342 如圖3的習知電路,且每一 離而減半。 週期的時間更因為奇偶階的分 當然,實際應用中,計算裝置41、42和子計算器νι—p V2_p可;^限定以奇偶階來決定所有階運算器&的配置 ’、要使4等運算器TCr,配置於該兩個計算裝置4 i 或是配置於子計算器V1_P、V2_P中,即可達到縮短每 期時間的功效。 此外,屬於同一階的階運算器Tcr,都接收同一多工器 16的輸出’所以這些階運算器仏可以採用習知的群組匹 配:G:up Matching)方式來共用電路元件。同理,該等對照 運算™ 29、Ep也能共享而減少硬體電路的使用。 隹實施例 〃如圖9所示’為了減少有限體常數乘法器^的使用, 第五較佳實施例更將子計算器V1_p、V2_p的階運算器扣 置換成移位器(shifter)。 相較於第四較佳實施例,本發明尋根電路5之第五較 佳實施例的主要不同點有二: (―)子計算器VI 一p、V2_p的階運算器TCr,僅具有一移 位器58,使對應多工器之輸出向左移位(r,_u)xp, 而造成階乘積的位元長度增加(r,_u)xp。請注意, 本例移位器5 8的移位長度能隨u改變而間接影響 有限體加法H 14使用的x〇R數目,有別於習知 的圖3電路。 201036342 (二)子計算器V1 V2 一P除了既有的有限體加法器14 和該等階運算器TC,外,澴且女, Γ卜還具有一個修正電路53 /會在有限體加法器14集合相關階運算器TCr,之 隻調整對應的數值信號並補償位元長度,再送 往比較器JG_p。The device 21 is replaced. In addition, since the step operator TCu is omitted, the area index may not include the Bu-. U = |- un\ + \-(u- l)n\ +... + |(i? - u)n\ (5) y 201036342 and in the process of taking the absolute value, based on the Galloway field GF (2m The calculation of the scene is the existence of (the relationship, so when w>o, I-call can be expressed as state-m. More notably, the comparator 13 uses the selected reference value a for comparison. The value is pre-calculated, and this value will change with η. Of course, in another example, the pre-calculation may be used instead, and a comparison operator 29 is used to generate this value. It has a multiplexer 16, a register!) and a finite body constant multiplier 17' and operates in a manner similar to the order operator TCr. Wherein the 'finite body constant multiplication H Π is multiplied by the output of the multiplexer 16, and the multiplexer 16 is outputted with a value of 1 in the first cycle. Therefore, when the root-seeking circuit 2 checks the non-period in the first cycle The zero element ", the finite body constant multiplier η will produce the selected reference value γ according to the output of the multiplex $16 (1 value). While the non-zero element is checked in the second cycle, the multi-guard 16 selects the output of the register D, and the finite body constant multiplier 17 updates the selected reference value to . And so on. A third preferred sinus. You can refer to Figure 6, the third preferred embodiment integrates the spirit of the first two embodiments, and the equal-order operator is deducted to two computing devices Μ, % The purpose of reducing the circuit cost is achieved by reducing the operation time per cycle and changing the multiplier of the finite-value multiplier 17. The third preferred embodiment of the root-seeking circuit 3 of the present invention comprises approximately 10 201036342 _ real (four) (Fig. 4) 'but where (., A has two differences, (a) the order operator TCr, the multiplier is α(~). (b) The step operator Tc coefficient Λ is omitted and is directly transmitted to the finite body adder 14. (3) In the second calculating means 32, the finite 妒 negative body adder 14 receives all even orders. The output of the order operator TC, the output of the ^山^,, receives the selected reference value α'. This point is different from the Ο 1 value received in the preferred embodiment. Figure 6 is an odd number with R being an even number and u being greater than 3. However, in practice, R can be any positive integer. For example, the value of U can also be equal to i, and at this time, rooting circuit 3, The architecture is shown in Fig. 7. Further, a comparison operator 29 can be used to generate the selected reference value as in the previous example, and based on the exchangeability of the finite volume addition operation, the comparison operator 29 can also be changed to the first configuration. In the computing device 31. Further, in the second preferred embodiment, due to the circuit The upper-order operators TCr and TCr' occupy most of the circuit area, and the finite-body constant multiplier 17 used in each of the level operators TCr and TCr' has a circuit structure that can be shared'. The item matching matching method is used to share circuit components to effectively reduce the circuit cost. Fourth Preferred Embodiment The fourth preferred embodiment introduces the concept of parallelization, and changes the structure of FIG. 7 11 201036342 into a figure. 8. The check of P non-zero elements y can be completed in a single cycle, P > 1. Compared with the third preferred embodiment, the fourth preferred embodiment of the root-seeking circuit 4 of the present invention further comprises OM) - sub-calculator V1_p, (pi) second sub-calculators V2_p and OM) comparators JG_p, ρ = 1, 2, (ρι). Each first sub-calculator V1-P includes S, rank operation a TCr, and a finite body adder 14, and each of the second sub-calculators V2-p includes one, an operation n Ep, a (R small s) order operator Tcv, and a finite body adder 14, And 1 "S' < (R-1), r, = 1, 2, R but r, its u. Among them, sub-calculator V1-P The V2-P step operator TCr has a finite body constant multiplier 17 using a multiplier ~ > on the other hand, it is worth noting that the 'steps of the computing devices 41, 42 are similar to the third. In the preferred embodiment, there is a multiplexer 16, a register D, and a finite body constant multiplier 17 using a multiplier α^. Next, the operation of the root-seeking circuit 4 will be described by taking the circuit of FIG. 8 as an example. It is assumed that u=l, R is a positive even number, and the order arithmetic unit Tcr included in the first calculating means 41 is an odd order, and the order arithmetic unit TCr included in the second calculating means 42 are all even orders. In the first cycle: the step operator TCr of the computing devices 41, 42 will send the corresponding coefficient Ar by the multiplexer 16, and then the order operator TCr of all the sub-calculators V1_p, V2_p will be multiplied by on. Moreover, the comparison operator 29 sends a threshold value for all the comparison operators Ep to multiply "^. 12 201036342" to the computing device 41 and the -sub-calculator νι ρ to form the riding limiter adder 14 The correlation level operator % is assembled, and v1 is a first value signal. For the computing device 42 and the second sub-calculator two, the corresponding finite body adder 14 will collect the comparison operator. p and the associated order operator TCr, And forming the second value signal Ο, the third comparator 13, JG_P only has to wait for the computing device 41 and the controller Vl_p to collect the odd-order operator τ, or wait for the computing device 42 and the second sub-meter #3 ! V2 Ming completed the pair of 3 卞 " 器 器 V V V V V 就 就 就 就 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ In the second cycle: the step operator TCr of the juice calculating devices 41 and 42 will send the Μ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Upper rp (r_-M). Also, the collation operator 29 sends a value for all the collating operators Ep to multiply by α-ρ. Finally, the comparator 13 and JG_p are compared to determine whether the non-zero element 〆+p is the root of the polynomial. And then the operation of the cycle, and so on, until all non-zero elements are fully verified. In summary, the number of overall inspection cycles can be reduced in this example. 13 201036342 The conventional circuit of Figure 3 is halved. The time of the cycle is more because of the division of the odd-even steps. Of course, in practical applications, the computing devices 41, 42 and the sub-calculators νι-p V2_p can define the configuration of all-order operators & The operator TCr is disposed in the two computing devices 4 i or in the sub-calculators V1_P, V2_P, so as to achieve the effect of shortening the period of each period. Further, the step operators Tcr belonging to the same order all receive the output of the same multiplexer 16 so that these order operators can share the circuit elements by the conventional group matching: G: up Matching). Similarly, the comparison operations TM 29 and Ep can also be shared to reduce the use of hardware circuits.隹 Embodiment 〃 As shown in Fig. 9, in order to reduce the use of the finite-body multiplier, the fifth preferred embodiment replaces the step operator of the sub-calculators V1_p, V2_p with a shifter. Compared with the fourth preferred embodiment, the fifth preferred embodiment of the root-seeking circuit 5 of the present invention has two main differences: (-) the sub-calculator VI, the step operator TCr of p, V2_p, has only one shift. The biter 58 shifts the output of the corresponding multiplexer to the left (r, _u) xp, and causes the bit length of the product of the order to increase (r, _u) xp. Please note that the shift length of the shifter 58 of this example can indirectly affect the number of x〇R used by the finite body addition H 14 as the u changes, which is different from the conventional circuit of FIG. 201036342 (2) Sub-calculator V1 V2-P In addition to the existing finite body adder 14 and the equal-order operator TC, in addition, the female, the 还b also has a correction circuit 53 / will be in the finite body adder 14 The set correlation level operator TCr adjusts only the corresponding numerical signal and compensates the bit length, and then sends it to the comparator JG_p.
接下來1¾明绝兩項相異處的原由。本發明所屬技術 領0域Γ具有通常知識者都可以理解:對於具有非零元素 的有限體卿,)而言,每—非零元素的位元長度為 m,且乘法運算具有封祕的特質。亦即,任兩個非零元素 相乘所得到的唯—乘積結果會等效於這N個非零元素的其 中之-,且所得乘積結果的位元長度仍為m。這暗示著, 除了以移位器58來執行進位的步驟外,還需要配合修正電 路53,才能得到位元長度m的乘積結果,以滿足有限體常 數乘法器17的功用。而修正電路53如何補償移位器%的 輸出,是本領域的通常知識,所以本文不再贅述。The next 13⁄4 is the reason for the two differences. The technology of the present invention can be understood by those skilled in the art: for a finite body with a non-zero element, the length of each non-zero element is m, and the multiplication has a secret characteristic. . That is, the result of multiplication of any two non-zero elements is equivalent to the - of the N non-zero elements, and the resulting product result is still m in length. This implies that in addition to the step of performing the carry with the shifter 58, it is also necessary to cooperate with the correction circuit 53 to obtain the product of the bit length m to satisfy the function of the finite body constant multiplier 17. How the correction circuit 53 compensates for the output of the shifter % is a common knowledge in the art, so it will not be described in detail herein.
此外,子計算器Vl_p、V2_p中,各有限體加法器14 的運算時間與實現面積(x〇R數目),取決於相關階運算器 TCr’移位後的位元長度。當移位後的各個位元長度彼此差異 增大,對應有限體加法器14的運算時間會拉長,且實現面 積加大。 所以,較佳地,本例是使第l~R/2階的階運算器TCf 配置於第一計算裝置51和第一子計算器V1_p中,並使第 15 201036342 (R/2+1)~r階的階運算器TCr,配置於第二計算裝置μ和第 二子計算器V2_p中。 再者,為了進-步減少第二子計算器V2』的移位位元 長度,第(R/2+l)~R階的階運算器TCr,分別減少(R/2)xp移 位長度,即:減少成(r,-R/2_u)Xp。且每—個第二子計算器 V2—P更包括-個公因數乘法器54,接收對應修正電路幻 的輸出以乘上,然後再提供給比較器JG_p。 值得注意的是,第二子計算器V2_p增加了該等公因數 乘法器54,但是第二計算裝置52並沒有同步增加所以本 例根據有限體加法的交換特性,而將該等對照運算器Μ、 ΕΡ移動到第一計算裝置51與第一子計算器νι_ρ中。 μ此外在另實施態樣中,第三〜五實施例的對照運算 盗29、Ερ也可以是電連接到該比較器13,且比較器η改 由基於對照運算器29、Ερ的輸出、該等第—數值信號以及 該等第二數值信號,來做判斷。 紅上所述,前述較佳實施例將該等階運算器 區隔到兩個計算裝晋1〗、Μ ς , 欣抑 T异衮置U 31〜51、12〜52或區隔到兩個子計 异益Vl_p、V2一p,以降低每一週期的操作時間。也會在這 樣的架構下’改變有限體f數乘法器17的乘數、或是將有 限體常數乘法器17置換成移位器58,來減少硬體電路,故 確實能達成本發明之目的。 准以上所述者,僅為本發明之較佳實施例而已,當不 能以此限定本發明實施之範圍,即大凡依本發明申請:利 範圍及發月„兑明内谷所作之簡單的等效變化與修飾皆仍 16 201036342 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一方塊圖,說明實現錢氏搜尋法的習知電路; 圖2是一方塊圖,說明平行化概念的一習知電路; 圖3是一方塊圖,說明平行化概念的另一習知電路; 圖4是本發明尋根電路之第一較佳實施例的方塊圖; 圖 本發月尋根電路之第二較佳實施例的方塊圖; 0 本發月尋根電路之第三較佳實施例的方塊圖; 圖 7 β _+ 圖塊圖,說明第三較佳實施例的一態樣; 及 本發月尋根電路之第四較佳實施例的方塊圖; t發明哥根電路之第五較佳實施例的方塊圖。 17 201036342 【主要元件符號說明】 1 5 ...** β * ·尋根電路 31,… ··第一計算裝置 11-51 …第一計算裝置 3 2,f …第二計算裝置 12〜52 - 第二計算裝置 53 ·· -修正電路 1 ^ ^ β •比較器 54·"... •公因數乘法器 14 •有限體加法器 58^ …移位器 16 多工器 D……' 暫存器 η •有限體常數乘法器 F > ^ 對照運算器 21… 計算裝置 JG_p …比較器 28· *: ^ 面積評估器 TCl-R …階運算器 29 對照運算器 Vl_p …第一子計算器 2 ? …尋根電路 V2_p …第二子計算器 18Further, in the sub-calculators Vl_p, V2_p, the operation time and the realized area (the number of x 〇 R) of each finite-body adder 14 depend on the bit length after the shift of the correlation-order operator TCr'. When the lengths of the shifted individual bits are increased from each other, the operation time of the corresponding finite body adder 14 is lengthened, and the area is increased. Therefore, preferably, in this example, the step operator TCf of the l~R/2th order is disposed in the first computing device 51 and the first sub-calculator V1_p, and the 15th 201036342 (R/2+1) The order operator TCr of the ~r order is disposed in the second computing device μ and the second sub-calculator V2_p. Furthermore, in order to further reduce the shift bit length of the second sub-calculator V2, the order operator (TCr) of the (R/2+l)-Rth order is reduced by (R/2)xp shift length, respectively. , ie: reduced to (r, -R/2_u)Xp. And each of the second sub-calculators V2-P further includes a common-factor multiplier 54, receives the output of the corresponding correction circuit phantom, multiplies it, and then supplies it to the comparator JG_p. It is worth noting that the second sub-calculator V2_p adds the common factor multipliers 54, but the second computing means 52 does not increase synchronously. Therefore, in this example, according to the exchange characteristics of the finite body addition, the comparison operators are , ΕΡ moves to the first computing device 51 and the first sub-calculator νι_ρ. In addition, in another embodiment, the comparison operation thieves 29, Ερ of the third to fifth embodiments may be electrically connected to the comparator 13, and the comparator η is changed by the output based on the comparison operator 29, Ερ, The first-value signal and the second value signal are used for judgment. According to the above description, the preferred embodiment divides the equal-order operator into two computing devices, Μ ς, 抑 T T, and U 31 51, 12 to 52, or two to two. The sub-meters Vl_p, V2-p are used to reduce the operation time of each cycle. It is also possible to reduce the hardware of the finite-body f-number multiplier 17 or to replace the finite-body multiplier 17 with the shifter 58 under such a structure to reduce the hardware circuit, so that the object of the present invention can be achieved. . The above is only the preferred embodiment of the present invention, and the scope of the present invention cannot be limited thereto, that is, the application according to the present invention: the scope of the benefit and the simpleness of the month. The effect changes and modifications are still in the scope of the present invention. The following is within the scope of the present invention. [Fig. 1 is a block diagram showing a conventional circuit for implementing the Chien search method; Fig. 2 is a block diagram showing parallel FIG. 3 is a block diagram showing another conventional circuit of the concept of parallelization; FIG. 4 is a block diagram of a first preferred embodiment of the root-seeking circuit of the present invention; A block diagram of a second preferred embodiment of the present invention; a block diagram of a third preferred embodiment of the present invention; FIG. 7 is a block diagram showing a third preferred embodiment; A block diagram of a fourth preferred embodiment of the present invention; a block diagram of a fifth preferred embodiment of the invention. 17 201036342 [Description of main component symbols] 1 5 ... ** β * Rooting circuit 31, ...··first computing device 11-51 First computing device 3 2, f ... second computing device 12 - 52 - second computing device 53 · · - correcting circuit 1 ^ ^ β • comparator 54 · " ... • common factor multiplier 14 • finite body Adder 58^ ... shifter 16 multiplexer D...' register η • finite body constant multiplier F > ^ comparison operator 21... computing device JG_p ... comparator 28 · *: ^ area estimator TCl -R ...th order operator 29 comparison operator Vl_p ... first sub-calculator 2 ? ... rooting circuit V2_p ... second sub-computer 18
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