TW201036342A - Root-finding circuit - Google Patents

Abstract

A root-finding circuit is disclosed, which is applied in examining if a nonzero element belongs to a root of a Rth-order polynomial. It comprises: (1) a first computation device having (a) S (numbers of) order-computation devices corresponding to one order of the polynomial respectively, each of which generates an order-product based on the coefficient of its corresponding order, where 1 ≤ S < R; and (b) a finite field adder to receive the order-products generated by the S order-computation devices, thereby forming a first numerical signal; (2) a second computation device having (c) (R-S) (numbers of) order-computation devices, each order-computation device corresponding to one order of the polynomial and generating an order-product based on the coefficient of the corresponding order; and (d) another finite field adder to receive the order-products generated by the (R-S) order-computation devices, thereby forming a second numerical signal; and (3) a comparator to compare the two numerical signals for determining if the nonzero element belongs to the root of the polynomial.

Description

201036342 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to an algebraic computing technique, and more particularly to a root-seeking circuit for implementing Chien Search. [prior art]

主要 The main use of the Qian search method is to find the root of a polynomial, which is beneficial to the factorization of polynomials. Commonly used to correct random bit errors The Reed Solomon (RS) decoder analyzes an error bit polynomial to find out where the error occurred. (n, k, d) coded signal, its code length η d~l assumes that the RS decoder receives the bit bit 'actual information length k bits, the error correctable capacity is and its L\l represents: less than or equal The largest positive integer of I. Then the &s2 solution can generate an error-locator p〇lynomial w equation (1) according to the coded signal, and then use the Chiss search method to add the Galois body. GF (N non-zero elements of n (n〇nzer〇element) iAQfl, a2—1 are substituted one by one to verify which non-zero elements belong to the root of the misplaced homering term and all the test operations are It is based on the finite volume of Galois GF(2m), where N=2mi, η=0,1,2··.(Ν-1), and the constant term coefficient of the error location polynomial Λ〇= ι, the coefficients of each order are Λι, λ2...Λ/?. r=〇r=i, 丄', and Figure 1, which shows the circuit diagram for implementing equation (i). When a non-zero 3 201036342 element β Into this non-zero element, the R finite multipliers 71 can be combined and added to the number Jr and the operation is performed, and then the adder 72 is set to 1 or not. The value signal is then determined to determine the root of the material (4) type, and the period continues to verify another - non-zero after the circuit of Figure 1 will be in the next - week N cycles. However, such a circuit It is necessary to consume the decoding efficiency into the detection of all non-zero elements, which is quite unfavorable - one = two techniques put forward the concept of parallelization (such as circle 2), so that the inspection of the towel at the gate is a non-zero element 6 The recovery is reduced to a (four) cycle, where Μ represents: greater than or equal to the maximum of X. And 'other-known technology further simplifies the circuit of Figure 2 into Figure 3, in an attempt to reduce the operating time per cycle. Unfortunately, the improvement is limited. Looking at Figures 1 to 3, it is not difficult to find that for each non-zero element comparator 73, the numerical signal obtained after the calculation of the numerical value signal (containing the non-zero element 第 卜 &amp; Compared with them, this means that the waiting time of the comparators 73, 83, and 93 is quite long, which affects the operation time of each cycle, and is also a major cause of the low decoding efficiency.

In addition, although the number of inspection cycles of the circuits of Figs. 2 and 3 is much smaller than that of Fig. 1, the number of hardware circuits is almost P times that of Fig. 1, and the implementation cost is too high. In view of this, there are other improvements that have been proposed, such as: Chen Spears Parhi ^ IEEE TRANSACTIONS ON VERY LARGE SCAL V / iV7 ^ G / ? A770A ^ V ^ /) 2 卯 4 proposed in the overlap matching (Iterative Matching ) and group matching (Group Matching) method 201036342 to share the arithmetic circuit 'for example: Cho and Sung in / from five TRANSSACTIONS ON CIRCUITS AND SYSTEMS-Π, 2008 t it to replace the finite body with a shifter Multiplication operation. However, under the framework of FIG. 2 and FIG. 3, these practices cannot effectively alleviate the pressure of the implementation cost. [Inventive content] Therefore, the object of the present invention is to provide a root-seeking circuit capable of reducing the root-checking time and reducing the cost of the hardware circuit. .

Therefore, the root-seeking circuit of the present invention is adapted to verify whether a non-zero element belongs to the root of the -R-order polynomial, and includes: - a first computing device, comprising: S-order operators, each of which corresponds to a polynomial First order, and generating a _ order product according to the coefficient of the corresponding order, and a finite body adder, receiving a step product generated by the 豸s level operator to form a first-value signal, the second computing device, including : (Rs) rank operator 'per-step operator corresponds to one of the polynomials, and generates a -th order product according to the coefficient of the corresponding order; and a finite body adder receives the (four) Μ fixed-order operator The step product is formed to form a "first: value signal; and a comparator" compares the first value signal with the second value signal to determine whether the non-zero element belongs to the root of the polynomial. [Embodiment] The foregoing and other technical contents of the present invention will be clearly described in the following detailed description of the preferred embodiments with reference to the drawings. 5 201036342 Before the present invention is described in detail, it is to be noted that in the following description, similar elements are denoted by the same reference numerals. In order to shorten the waiting time of the comparator to reduce the operation time of each cycle, the present invention proposes a folding architecture, which divides the multi-step r-order into two parts, and for each part A numerical signal is calculated. The comparator then determines the binary signal.

Referring to Figure 4, a preferred embodiment of the root-seeking circuit of the present invention is applicable to the root of a R-order polynomial from the Galois body, 2, N non-zero elements «H. The rooting circuit i includes a first leaf computing device U, a second computing device 12, and a "comparator 13." The first includes s-order operations 芎Tc-inch 裒 μ μ finite body adder 14, and second; = (4)) The order operator % and the partial finite body adder, the middle, the --order operator TCR respectively correspond to a plurality of multiplexers 16, a temporary erection...~=1'2, 』 and - The finite body constant multiplier 17, preferably, makes the operation of S, /2" and causes the twentieth device 11 to negatively sequence the operation time of each cycle. In ^ is responsible for even-order operations, the smallest ^ can be the root of the polynomial, and the multiple ^ (four) arrangement under the assumption that the non-zero elements are respectively W:: number of coefficients eight. =1, the coefficients of each order 丨 非 非 非 非 y . . R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R

R Σαα r:odd ι+ revert,r&gt;2 (3) Four rfrj-order operator TCr in the body constant multiplier 17 multiplier and multiply it by the multi-jade 1116 to get the -order _, and the multiplexer 16 is in the first cycle with the coefficient "round, while the rest of the cycle is to select the register D output. And after the finite body constant multiplier 17 completes the multiplication operation, the step product is sent to the corresponding finite body addition _ 14, which will also be o

In the D. The register D will be delayed by - one cycle before the stored value is output. According to equation (3), the finite body adder 14 of the first computing device 11 adds up the product of the order of all odd-order step operators TQ to obtain a first value signal; the finite body adder 14 of the second computing device 12 will After adding the order product of all even-order order operations H TCr , a value of 1 of the constant term coefficient Λ〇 is added to obtain a second value signal. The 'comparator 13 then compares the first-value signal to the second-numbered signal' to determine if the non-zero element y is really the root of the polynomial. In detail, when the two numerical signals match, the comparator 13 judges that the non-zero element V is indeed the root of the polynomial; if it does not match, it judges as no. Of course, in another embodiment, the finite volume adder 14 of the second computing device 12 may only add the order product of all even-order operators to obtain the second value signal. The comparator 13 performs the comparison determination based on the first numerical signal, the second numerical signal, and the constant term coefficient Λ()=1. It is worth noting that, in the first cycle, each finite body constant multiplier 17 will produce a factor product of eight 因为 due to the reception coefficient \, so at this time 201036342 the finite body adder 14 will form a non-zero element. The numerical signal of y for comparison 13 to verify the non-zero element αι. At the second cycle, each finite body constant multiplier 17 updates the order product to Ar« by receiving the step product Λ〆 for the comparator 13 to verify the non-zero element α2. And so on. It should be noted that the comparator 13 of the preferred embodiment only needs to wait for a period of time to calculate the first numerical signal covering the odd order, or wait for a period of time to calculate the second numerical signal covering the even order, so Conventional techniques substantially shorten the operating time of each cycle. More notably, when the preferred embodiment is applied to an RS decoder, the error value is calculated based on the differentiation of the polynomial after finding the location where the error occurred. In the case of finite-body operations, the differential result belonging to the even-order order is equivalent to 0, so when the architecture of the odd-even separation is selected (as shown in Fig. 4), the first numerical signal covering the odd-order order can be directly used to obtain The associated error value simplifies the circuit used to calculate the error value indirectly. The second preferred embodiment of the present invention includes a computing device 21 and a comparator 13. The computing device 21 includes a rank operation TCr' and a finite body addition 14. Here, each of the first-order operation numbers TC is similar to the order operator TCr of the first preferred embodiment, and the definition of r, which will be described later. Since the finite body constant multiplier 17 of each order operator TCr' determines the complexity of the multiplying circuit because of its multiplier, this example attempts to change the corresponding multiplier to reduce the circuit cost. Assuming that the non-zero element y is the root of the 201036342 polynomial (see equation (2)), this example is to cause the computing device 21 to receive a selected order u ' and divide the equation (2) by (匕仏) to find the equation. (4) 〇(4)

1=1 i=l KJ As such, the second preferred embodiment will change the multiplier with the selected order u and can omit the use of the level operator tcu, that is, the computing device 21 only needs to include (R-1) The rank operator TCr,,r,= 1,2,...R but r, buckle. At this time, the Ο comparator 13 is compared by a selected reference value, which is different from the value of 1 selected for the first preferred embodiment. It is worth noting that since the finite body constant multiplier 17 is equivalent to a set of multiple adders and multiplied by different constants, it will correspond to a different number of adders. In this case, the finite body f-number multiplication ^ 17 multiplier is the power of the power, so you can replace the different selected order u (1, to minimize the adder (ie: mutual exclusion or (x〇R The number of gates used, which in turn reduces the circuit cost of the root-seeking circuit 2. 〇 Of course, the root-seeking circuit 2 of this example can also include an area estimator 28 for providing the selected order u, which will first be used in the other program (4) The number of powers of α takes the absolute value, then adds all the absolute values to obtain the area index of equation (5), and then selects a plurality of u which make the area index smaller.

The device 21 is replaced. In addition, since the step operator TCu is omitted, the area index may not include the Bu-. U = |- un\ + \-(u- l)n\ +... + |(i? - u)n\ (5) y 201036342 and in the process of taking the absolute value, based on the Galloway field GF (2m The calculation of the scene is the existence of (the relationship, so when w&gt;o, I-call can be expressed as state-m. More notably, the comparator 13 uses the selected reference value a for comparison. The value is pre-calculated, and this value will change with η. Of course, in another example, the pre-calculation may be used instead, and a comparison operator 29 is used to generate this value. It has a multiplexer 16, a register!) and a finite body constant multiplier 17' and operates in a manner similar to the order operator TCr. Wherein the 'finite body constant multiplication H Π is multiplied by the output of the multiplexer 16, and the multiplexer 16 is outputted with a value of 1 in the first cycle. Therefore, when the root-seeking circuit 2 checks the non-period in the first cycle The zero element ", the finite body constant multiplier η will produce the selected reference value γ according to the output of the multiplex $16 (1 value). While the non-zero element is checked in the second cycle, the multi-guard 16 selects the output of the register D, and the finite body constant multiplier 17 updates the selected reference value to . And so on. A third preferred sinus. You can refer to Figure 6, the third preferred embodiment integrates the spirit of the first two embodiments, and the equal-order operator is deducted to two computing devices Μ, % The purpose of reducing the circuit cost is achieved by reducing the operation time per cycle and changing the multiplier of the finite-value multiplier 17. The third preferred embodiment of the root-seeking circuit 3 of the present invention comprises approximately 10 201036342 _ real (four) (Fig. 4) 'but where (., A has two differences, (a) the order operator TCr, the multiplier is α(~). (b) The step operator Tc coefficient Λ is omitted and is directly transmitted to the finite body adder 14. (3) In the second calculating means 32, the finite 妒 negative body adder 14 receives all even orders. The output of the order operator TC, the output of the ^山^,, receives the selected reference value α'. This point is different from the Ο 1 value received in the preferred embodiment. Figure 6 is an odd number with R being an even number and u being greater than 3. However, in practice, R can be any positive integer. For example, the value of U can also be equal to i, and at this time, rooting circuit 3, The architecture is shown in Fig. 7. Further, a comparison operator 29 can be used to generate the selected reference value as in the previous example, and based on the exchangeability of the finite volume addition operation, the comparison operator 29 can also be changed to the first configuration. In the computing device 31. Further, in the second preferred embodiment, due to the circuit The upper-order operators TCr and TCr' occupy most of the circuit area, and the finite-body constant multiplier 17 used in each of the level operators TCr and TCr' has a circuit structure that can be shared'. The item matching matching method is used to share circuit components to effectively reduce the circuit cost. Fourth Preferred Embodiment The fourth preferred embodiment introduces the concept of parallelization, and changes the structure of FIG. 7 11 201036342 into a figure. 8. The check of P non-zero elements y can be completed in a single cycle, P &gt; 1. Compared with the third preferred embodiment, the fourth preferred embodiment of the root-seeking circuit 4 of the present invention further comprises OM) - sub-calculator V1_p, (pi) second sub-calculators V2_p and OM) comparators JG_p, ρ = 1, 2, (ρι). Each first sub-calculator V1-P includes S, rank operation a TCr, and a finite body adder 14, and each of the second sub-calculators V2-p includes one, an operation n Ep, a (R small s) order operator Tcv, and a finite body adder 14, And 1 "S' &lt; (R-1), r, = 1, 2, R but r, its u. Among them, sub-calculator V1-P The V2-P step operator TCr has a finite body constant multiplier 17 using a multiplier ~ &gt; on the other hand, it is worth noting that the 'steps of the computing devices 41, 42 are similar to the third. In the preferred embodiment, there is a multiplexer 16, a register D, and a finite body constant multiplier 17 using a multiplier α^. Next, the operation of the root-seeking circuit 4 will be described by taking the circuit of FIG. 8 as an example. It is assumed that u=l, R is a positive even number, and the order arithmetic unit Tcr included in the first calculating means 41 is an odd order, and the order arithmetic unit TCr included in the second calculating means 42 are all even orders. In the first cycle: the step operator TCr of the computing devices 41, 42 will send the corresponding coefficient Ar by the multiplexer 16, and then the order operator TCr of all the sub-calculators V1_p, V2_p will be multiplied by on. Moreover, the comparison operator 29 sends a threshold value for all the comparison operators Ep to multiply "^. 12 201036342" to the computing device 41 and the -sub-calculator νι ρ to form the riding limiter adder 14 The correlation level operator % is assembled, and v1 is a first value signal. For the computing device 42 and the second sub-calculator two, the corresponding finite body adder 14 will collect the comparison operator. p and the associated order operator TCr, And forming the second value signal Ο, the third comparator 13, JG_P only has to wait for the computing device 41 and the controller Vl_p to collect the odd-order operator τ, or wait for the computing device 42 and the second sub-meter #3 ! V2 Ming completed the pair of 3 卞 &quot; 器 器 V V V V V 就 就 就 就 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ In the second cycle: the step operator TCr of the juice calculating devices 41 and 42 will send the Μ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Upper rp (r_-M). Also, the collation operator 29 sends a value for all the collating operators Ep to multiply by α-ρ. Finally, the comparator 13 and JG_p are compared to determine whether the non-zero element 〆+p is the root of the polynomial. And then the operation of the cycle, and so on, until all non-zero elements are fully verified. In summary, the number of overall inspection cycles can be reduced in this example. 13 201036342 The conventional circuit of Figure 3 is halved. The time of the cycle is more because of the division of the odd-even steps. Of course, in practical applications, the computing devices 41, 42 and the sub-calculators νι-p V2_p can define the configuration of all-order operators &amp; The operator TCr is disposed in the two computing devices 4 i or in the sub-calculators V1_P, V2_P, so as to achieve the effect of shortening the period of each period. Further, the step operators Tcr belonging to the same order all receive the output of the same multiplexer 16 so that these order operators can share the circuit elements by the conventional group matching: G: up Matching). Similarly, the comparison operations TM 29 and Ep can also be shared to reduce the use of hardware circuits.隹 Embodiment 〃 As shown in Fig. 9, in order to reduce the use of the finite-body multiplier, the fifth preferred embodiment replaces the step operator of the sub-calculators V1_p, V2_p with a shifter. Compared with the fourth preferred embodiment, the fifth preferred embodiment of the root-seeking circuit 5 of the present invention has two main differences: (-) the sub-calculator VI, the step operator TCr of p, V2_p, has only one shift. The biter 58 shifts the output of the corresponding multiplexer to the left (r, _u) xp, and causes the bit length of the product of the order to increase (r, _u) xp. Please note that the shift length of the shifter 58 of this example can indirectly affect the number of x〇R used by the finite body addition H 14 as the u changes, which is different from the conventional circuit of FIG. 201036342 (2) Sub-calculator V1 V2-P In addition to the existing finite body adder 14 and the equal-order operator TC, in addition, the female, the 还b also has a correction circuit 53 / will be in the finite body adder 14 The set correlation level operator TCr adjusts only the corresponding numerical signal and compensates the bit length, and then sends it to the comparator JG_p.

The next 13⁄4 is the reason for the two differences. The technology of the present invention can be understood by those skilled in the art: for a finite body with a non-zero element, the length of each non-zero element is m, and the multiplication has a secret characteristic. . That is, the result of multiplication of any two non-zero elements is equivalent to the - of the N non-zero elements, and the resulting product result is still m in length. This implies that in addition to the step of performing the carry with the shifter 58, it is also necessary to cooperate with the correction circuit 53 to obtain the product of the bit length m to satisfy the function of the finite body constant multiplier 17. How the correction circuit 53 compensates for the output of the shifter % is a common knowledge in the art, so it will not be described in detail herein.

Further, in the sub-calculators Vl_p, V2_p, the operation time and the realized area (the number of x 〇 R) of each finite-body adder 14 depend on the bit length after the shift of the correlation-order operator TCr'. When the lengths of the shifted individual bits are increased from each other, the operation time of the corresponding finite body adder 14 is lengthened, and the area is increased. Therefore, preferably, in this example, the step operator TCf of the l~R/2th order is disposed in the first computing device 51 and the first sub-calculator V1_p, and the 15th 201036342 (R/2+1) The order operator TCr of the ~r order is disposed in the second computing device μ and the second sub-calculator V2_p. Furthermore, in order to further reduce the shift bit length of the second sub-calculator V2, the order operator (TCr) of the (R/2+l)-Rth order is reduced by (R/2)xp shift length, respectively. , ie: reduced to (r, -R/2_u)Xp. And each of the second sub-calculators V2-P further includes a common-factor multiplier 54, receives the output of the corresponding correction circuit phantom, multiplies it, and then supplies it to the comparator JG_p. It is worth noting that the second sub-calculator V2_p adds the common factor multipliers 54, but the second computing means 52 does not increase synchronously. Therefore, in this example, according to the exchange characteristics of the finite body addition, the comparison operators are , ΕΡ moves to the first computing device 51 and the first sub-calculator νι_ρ. In addition, in another embodiment, the comparison operation thieves 29, Ερ of the third to fifth embodiments may be electrically connected to the comparator 13, and the comparator η is changed by the output based on the comparison operator 29, Ερ, The first-value signal and the second value signal are used for judgment. According to the above description, the preferred embodiment divides the equal-order operator into two computing devices, Μ ς, 抑 T T, and U 31 51, 12 to 52, or two to two. The sub-meters Vl_p, V2-p are used to reduce the operation time of each cycle. It is also possible to reduce the hardware of the finite-body f-number multiplier 17 or to replace the finite-body multiplier 17 with the shifter 58 under such a structure to reduce the hardware circuit, so that the object of the present invention can be achieved. . The above is only the preferred embodiment of the present invention, and the scope of the present invention cannot be limited thereto, that is, the application according to the present invention: the scope of the benefit and the simpleness of the month. The effect changes and modifications are still in the scope of the present invention. The following is within the scope of the present invention. [Fig. 1 is a block diagram showing a conventional circuit for implementing the Chien search method; Fig. 2 is a block diagram showing parallel FIG. 3 is a block diagram showing another conventional circuit of the concept of parallelization; FIG. 4 is a block diagram of a first preferred embodiment of the root-seeking circuit of the present invention; A block diagram of a second preferred embodiment of the present invention; a block diagram of a third preferred embodiment of the present invention; FIG. 7 is a block diagram showing a third preferred embodiment; A block diagram of a fourth preferred embodiment of the present invention; a block diagram of a fifth preferred embodiment of the invention. 17 201036342 [Description of main component symbols] 1 5 ... ** β * Rooting circuit 31, ...··first computing device 11-51 First computing device 3 2, f ... second computing device 12 - 52 - second computing device 53 · · - correcting circuit 1 ^ ^ β • comparator 54 · &quot; ... • common factor multiplier 14 • finite body Adder 58^ ... shifter 16 multiplexer D...' register η • finite body constant multiplier F &gt; ^ comparison operator 21... computing device JG_p ... comparator 28 · *: ^ area estimator TCl -R ...th order operator 29 comparison operator Vl_p ... first sub-calculator 2 ? ... rooting circuit V2_p ... second sub-computer 18

Claims (1)

201036342 VII. Patent application scope: 1. A root-seeking circuit, which is suitable for testing whether a non-zero element belongs to the root of an R-order polynomial, comprising: a first computing device, comprising: s-order operators, each order operation Corresponding to the first order of the polynomial, and generating a first-order product according to the coefficient of the corresponding order, 1&lt;S&lt;R; ^ finite body adder 'receives the; the 5th-order operator produces a step product of 〇, and forms a first numerical signal; a second computing device comprising: (Rs) a rank operator, each step operator corresponding to a middle order of the polynomial, and generating a first order product according to the coefficient of the corresponding order: and a finite body An adder receiving the step product generated by the (R_S)th order operator to form a second value signal; and a comparator comparing the first value signal with the second value signal to determine the non-zero element Whether it belongs to the root of the polynomial 2. According to the root-seeking circuit described in the scope of the patent application, wherein each stage operator has a finite body constant multiplier, which is multiplied by a multiplier The order product is generated by the coefficient of the corresponding order, and the multiplication operation $' for the correlation order is the power of the non-zero element, l&lt;r&lt;R. 3. The root-seeking circuit according to item 2 of the scope of the patent application is more suitable for testing whether another non-zero element belongs to the root of the polynomial, wherein '19 201036342 each level operator has: : register register receives the The product of the order produced by the finite-body constant multiplier, and output after one cycle; and ^. Selecting the output of the bin-chamber register or the coefficient of the corresponding-order order for the operation basis of the finite-body constant multiplier In the first cycle, a multiplicity of coefficients is used to output the coefficients of the corresponding order: the output, and the corresponding finite body constant multiplier produces a product of the order of the non-zero elements' and the comparator compares the non-zero elements The first value signal and the second number ^#^4唬 determine whether the non-zero element belongs to the root of the polynomial; in the (5)th cycle, the multiplexer provides the output of the register. The finite body is a number multiplier, and the corresponding finite body constant multiplier is produced with respect to the step product of the other non-zero 70 elements, so that the comparator makes a judgment on the other non-zero element. According to the root-seeking circuit described in the first paragraph of the patent scope of the invention, wherein the step-by-step calculation units included in the first-calculation device are all odd-order, and . The order operators included in the first-leaf calculation device are all even orders. 20