WO2010054526A1

WO2010054526A1 - Rs decoding device and key multinomial solving device used by rs decoding device

Info

Publication number: WO2010054526A1
Application number: PCT/CN2009/000742
Authority: WO
Inventors: 王帅
Original assignee: 中兴通讯股份有限公司
Priority date: 2008-11-11
Filing date: 2009-07-01
Publication date: 2010-05-20
Also published as: CN101741397A

Abstract

A RS decoding device and a key multinomial solving device used by the RS decoding device are disclosed. The decoding device comprises an adjoint computing module for processing the input codes sequentially, a key multinomial solving module and a fault location searching and fault value computing module. The key multinomial solving module comprises a difference computing module used to compute the fault value multinomial coefficients and a fault location updating module used to compute the fault location multinomial. The difference computing module comprises 2t stages increment difference computing basic units PEi which is connected sequentially and a controller.

Description

RS decoding device and key polynomial solving device used thereby

Technical field

The present invention relates to an RS decoding apparatus and a key polynomial solving apparatus therefor. Background technique

The RS code is a class of BCH codes with strong error correction capability. It is also a typical algebraic geometry code. It was first constructed in 1960 by Reed and Solomon. RS codes are widely used in communication systems such as deep space communications, wireless systems, and data storage systems. The current high rate of data transmission requirements has facilitated the development of high speed RS decoding devices.

The whole process of RS decoding can be divided into three steps (as shown in Figure 1): The first step is to complete the calculation of the companion matrix (101): After receiving the codeword, the RS decoding system is calculated by the received code group. 2t (for RS (n, k) decoding, t = ( nk ) 12 ) adjoint polynomial coefficients; the second step applies an iterative method to solve the key polynomial (102 ): using the 2t coefficients obtained in the first step through the BM The iterative algorithm respectively obtains the error location polynomial and the coefficient of the error value polynomial, and the highest power of the two polynomials is t; the third step searches for the error position estimation error value (103): Substituting all the values representing the codeword position into the error position Polynomial, if the error position polynomial result is 0, it indicates that the position is the error position, and then the corresponding error value is calculated for the found error position. The key to the above RS decoding process lies in the second step of solving the key polynomial (102). In this respect, the BM algorithm is simple and easy to implement, but due to the finite field inversion operation in the BM iterative algorithm, the inverse operation consumes a large amount of hardware. The resource is slow in operation. If it is applied to the BM iterative operation, it will cause a large critical path delay. Therefore, the IBM algorithm without inversion is developed. Although this algorithm improves the performance of the decoding system, it is relatively Euclidean. The algorithm still has the disadvantage that the critical path is long and the hardware structure is irregular. Summary of the invention The object of the present invention is to overcome the deficiencies of the prior art, to improve the IBM algorithm architecture of the RS decoding apparatus, and to disclose an RS decoding apparatus and a key polynomial solving apparatus therefor.

The present invention discloses an RS decoding apparatus, including an accompanying matrix calculation module 101 for sequentially processing input code words, a key polynomial solving module 102, and an error position search and error value calculation module 103; the key polynomial solving module 102 further The difference calculation module 201 for calculating the error value polynomial coefficient and the error position update module 202 for calculating the error position polynomial; the difference calculation module 201 includes the incremental difference calculation basic unit PEi and the controller 402, i of the 2t order The value range is 0, 1, ... 2t-l; 0, the initial value of the intermediate variable and the incremental difference is input from the (2t-l)-level basic unit, and the control signal ⁽ and the adjoint polynomial coefficient S are input in parallel for each stage). The basic unit, the feedback generated by the level 0 basic unit is returned to the controller 402, and the incremental difference ^W, the calculated intermediate quantity, and the control signal are encoded for _RS ( _n , k), where t = (nk) /2, where = The input of the incremental difference calculation base unit PEi is the intermediate variable W, the incremental difference and ^ W , the output is the intermediate variable ? ^], the incremental difference and ^ W ; and both pass the first multiplier The obtained product and the sum of the product of the W and the intermediate variable obtained by the second multiplier are input to the first register 311, thereby obtaining ' _i+1 (r) and (r) are also controlled by the selector signal ^M by a second choice. The W strobe then generates an intermediate variable input second multiplexer through the second register 321.

Further, the error value polynomial coefficient output by the difference calculation module 201 is input to the error location update module 202, and the error location update module 202 outputs the updated error location polynomial, and the output of the difference calculation module 201 and the error location update module 202. The error location search and error value calculation module 103 is further input to calculate the error position and the error value.

Further, the difference calculation module 201 calculates the incremental difference according to the input adjoint polynomial coefficient S and the error position polynomial coefficient (W), and then the control module 204 Generating a corresponding calculation intermediate amount and control signal to the error location update module 202; the error location update module 202 calculates an updated error location polynomial coefficient ( ^Λ . . . ( W ) feedback to the difference calculation Module 201, the above process is iterated 2t times, and the final error position polynomial coefficient (...^) and the corresponding incremental difference ( ^r ) are obtained.

Further, the RS decoding apparatus further includes an error correction module, wherein the input codeword is input to the error correction module through the buffer and the output of the error location search and error value calculation module 103, respectively, to obtain decoding. Output.

The invention discloses a key polynomial solving device used by an RS decoding device, comprising a difference calculating module 201 for solving an error value polynomial coefficient and an error position updating module 202 for calculating an error position polynomial coefficient; the difference calculating module 201 comprises a 2t level The incremental difference calculation of the basic unit PEi and the controller 402, the range of values of the i is 0, 1, ... 2t-l; 0, the initial value of the intermediate variable and the incremental difference from the (2t-l) The basic unit input, the control signal ^ and the accompanying polynomial coefficient S are input in parallel to each level of the basic unit, and the generated by the 0th level basic unit is fed back to the controller 402 to generate an incremental difference ^W, an intermediate quantity, and a control Signal ^M cW ; for RS ( n, k ) coding, there is t = ( nk ) 12, where = ; the input of the incremental difference calculation basic unit PEi is intermediate variable ^], incremental difference ") and ^ W, The output is an intermediate variable ^], an incremental difference ^] and ^ W; wherein the sum of the product obtained by the first multiplier and the sum of the W and the intermediate variable obtained by the second multiplier is input to the first register _{31 1} to obtain, _{i + 1} (r) (r) through a second election by the selector control signal ^M cW gate 321 then generates a second intermediate variable input register through a second multiplier.

Further, the difference calculation module 201 calculates the incremental difference according to the input adjoint polynomial coefficient S and the error position polynomial coefficient ( ^Λ . ( W ) and then generates a corresponding calculation intermediate amount and control by the control module 204. Signal, sent to the error location update module The error location update module 202 calculates an updated error location polynomial coefficient ( ^Λ . . . ( W ) is fed back to the difference calculation module 201 , and the above process is iterated 2 times to obtain a final error location polynomial coefficient ( . .. ... ^ ) and the corresponding incremental difference ( ^r ). The key polynomial solving device disclosed by the invention realizes the calculation of the polynomial coefficient of the error value in the process of RS decoding by using the IBM algorithm, and the structural rule is adopted by the simple basic The unit (PEi) is extended and flexibly constructed into decoders with different decoding modes. When constructing RS decoders with different error correction capabilities, only a corresponding number of processing units (PEi) can be added. The RS decoding device has high-speed processing performance and has a small critical path delay, which can meet the needs of a higher system operating frequency.

BRIEF abstract

Figure 1 is a hardware block diagram of an RS decoding device;

2 is a hardware block diagram of an implementation of an IBM algorithm in the prior art;

3 is a basic block diagram of a difference calculation module of the present invention;

4 is a block diagram of a difference calculation module of the present invention;

Figure 5 is a block diagram of an improved IBM algorithm circuit application in the RS decoder.

Preferred embodiment of the invention

The present invention will be further described in detail below in conjunction with the drawings and specific embodiments. The conventional RS decoder device is shown in FIG. 1. The key of the entire RS decoding system is to solve the key polynomial solving module 102 of the key equation. Therefore, the implementation of this module becomes the key to affect the performance of the entire RS decoding device. Because the classical BM iterative algorithm requires complex finite field inversion, and the finite field inversion operation consumes hardware resources and the operation speed is slow, it has a great influence on the critical path delay of the system. Although the IBM algorithm eliminates the inversion operation, it still has the disadvantages of long critical path and irregular hardware architecture. The present invention therefore provides an improved IBM law architecture. The traditional IBM algorithm structure is shown in Figure 2 (a), which includes a difference calculation module 201 and an error location update module 202. The structure of the difference calculation module 201 is as shown in FIG. 2(b).

2, the difference calculation module 201 according to an initial incremental difference value calculating polynomial coefficients S and the associated error location polynomial coefficients (W ...... ^(r)) is input, then generated by the control module 204 and the corresponding ^ The control signal is sent to the error location update calculation module 202 (the control module 204 is part of the difference calculation module 201), and the error location update module 202 calculates and updates the error location polynomial coefficient (...W) and feeds it back to the difference calculation module 201. Process iteration 2t (for RS (n, k) encoding, t = (nk) /2) times, yielding the final error location polynomial coefficients ( ^A . ( ^r ) ...... ) and their corresponding incremental differences ^^).

As shown in FIG. 2(b), a difference calculation module 201 includes a t-stage shift memory group 203 (Reg

(0) , Reg ( 1 ) , -Reg (t-1 ) ) , the adjoint polynomial coefficient S is input from the first stage Reg (0) of the shift register group 203, the error position polynomial coefficient ( ^) ..... Each of ^At ( ^r ) ) is multiplied by the output of the corresponding register, and the resulting product is input to the addition tree, the addition of the addition tree and the input control module 204, to obtain the corresponding incremental difference ^W, the calculated intermediate amount ^ And the control signal M _c ^. As can be seen from the difference calculation module 201 of Fig. 2 (b), the conventional IBM algorithm structure has two disadvantages: 1. The number of register groups 203 will vary with the error correction capability of the system. Change and change, thus requiring the hardware design of module 201 to be greatly adjusted with different RS decoding methods. Second, the key path shown in Figure (b) is relatively long (including a multiplier and addition tree), which is not Conducive to the implementation of high-speed RS decoding devices.

The present invention is improved from the algorithm, as shown in the conventional IBM algorithm shown in Fig. 2, the incremental difference is obtained by multiplying and accumulating the adjoint coefficient S and the error position polynomial coefficient ( ... ()), which results in a longer Multiply and accumulate key paths, and the structure is irregular. The improved algorithm structure uses the same hardware structure to iteratively derive the incremental difference ^ and the error location polynomial system. The number ( ^A. ^(r ) ......) eliminates the long multiply-accumulate critical path that exists in the traditional IBM algorithm, and also obtains a regular hardware structure. The algorithm improvements are as follows:

The error position polynomial coefficient update calculation module 202 in the original algorithm has the following formula:

A(r + 1, ) = (r) * A(r, x)-x* S(r) * B(r, x) ( ) where r = 0,l,....,2t-l

Where)) is the calculated intermediate quantity of the output of 201, which is the intermediate quantity of the auxiliary calculation ^ ^{+ 1} , ^x ). The calculation of ^ in the traditional IBM algorithm 201 can also be obtained by the following formula:

λ{τ, X) * S(x) = D{r, x) = S ₀ {r) + S _l {rYx + ....S _r {rYx ^r +.. ( ₂ ) is the polynomial ^D ( ^r The value of the rth term of ^x , is the value. The relationship between ^D ( ^r , ^x ) and i(r, x) represented by equation (2) can be derived from an iterative calculation formula similar to (1):

D(r + 1, ) = γ(τ) * D(r, x)-x*S _r (r) * θ(τ, x) ( 3 ) can be obtained from equation (2) as (, x) The _rth coefficient, so in the iteration, you need to select the coefficients of different positions for subsequent operations. In order to make the hardware connection fixed as follows, let (r) = d _l+r (r) ^ (r) = e _i+r (r) _M . δι + 1) = S _M+r (r + \) = y(r) * S _M+r (r)― S _r (r) * 0 _1+r (r) = y(r ) * δ _Μ (r)― (r) * Θ, (r)

(4)

Where i=0, 1, 2, .....2t-l. Equation (4) is an improved IBM algorithm that uses an iterative method to find incremental differences.

(ie), its corresponding hardware framework is shown in Figure 3.

Figure 3 (a) shows the basic unit of the incremental difference calculation of the present invention, which greatly reduces the delay of the critical path due to the elimination of the addition tree. In the figure, the input of the basic unit of the incremental difference calculation module is ^{+1 (} ),

, the output is the product of both &W, ) and <3⁄4( ; versus. The sum of the product of W and the intermediate variable is input to the first register 311, thereby obtaining 'W; S _M (r) and ^ (r) are also gated by the control signal ^M c W through the second selector and then passed through the second register 321 Generate the intermediate variable ^W.

Figure 3 (b) is a simplified block diagram of the basic unit of the incremental difference calculation module of the present invention, as shown in the figure, the i-th level basic unit PEi, the input amount, and the sum. After W processing, output 'W, ) and . W , and is gated by the control signal ^M c W , and outputs 'W. FIG. 4 is a hardware block diagram of a difference calculation module of the improved IBM algorithm according to the present invention, including a basic unit (PE0...PE2t-l) and a controller 402 connected in sequence of 2t levels; 0, and ^ from the second (2t) -l) level basic unit input, control signal ⁽ and accompanying polynomial coefficient S are input in parallel to each level of basic unit, feedback generated by level 0 basic unit is returned to controller 402, generating incremental difference ^, calculating intermediate quantity and control signal ^M c (r)

The present invention proposes an improved implementation of the IBM algorithm in the RS decoder, which has the following features:

(1) The RS decoding device implemented by this circuit has a small critical path delay and can meet the needs of a higher system operating frequency.

(2) The circuit has the characteristics of structural rules. When constructing RS decoders with different error correction capabilities, only a corresponding number of processing units (PEi) can be added.

The improved IBM algorithm proposed by the present invention implements an RS decoder device, which can be flexibly constructed by a simple basic unit (PEi) and configured into decoders of different decoding modes. And the decoding device has the performance of high speed processing.

If the system performs RS (240, 224) decoding, as shown in Figure 5 is a block diagram of the improved IBM algorithm circuit application in the RS decoder. First, the input codeword is used to calculate the adjoint polynomial coefficients, and the input is simultaneously input. The code words are sequentially saved to the buffer register 505, when the calculation is 16 (at this time) After t=(240-224) /2=8) coefficients of the adjoint polynomial ( ), the 16 adjoint polynomial coefficients are input from -1 to the difference calculation module 502. The calculation process in the difference calculation module 502 is shown in FIG. 4, and the workflow is as follows: setting the register group (.( ^r )... ^2i- ) and (^.( ^r )...) in the basic processing unit of PE0 to PE2t-1 The values are all (... -1), and then 16 iterations are performed as shown in Fig. 4. Each iteration operation control unit 402 generates corresponding δ{τ) and M according to the calculated ( ^r ) value. _c (r) The control signal is output to the error position update calculation module 202 (as shown in Fig. 2 (a)), so that it performs an operation update coefficient (AW - ^W), and thus repeats 16 times (the algorithm specifies iteration 2t times) At this time, t=(240-224) /2=8) The iterative operation yields an error value polynomial coefficient. After the end of the iteration, the obtained coefficient of the error value polynomial is output to the error position search and error value calculation module 504 to perform the search of the error position and the calculation of the error position corresponding error value, and output to the error position update module 503 to obtain the error position. Polynomial ( W ... ^{A r} ) ). After each time a position is detected is detected and the corresponding error value is calculated, the corresponding input code word stored in 505 is error-corrected by 506, and the corresponding decoded code word is output, when After the codeword is corrected, the entire RS decoding operation is completed. The above scheme can be completely used in the design of the RS decoding system, and can be implemented by the FPGA hardware, realizing the real-time processing of the decoding. The detailed description of the embodiments is provided to enable any person skilled in the art to use or utilize the invention. The present invention is applicable not only to the embodiments shown herein, but also to the design of different modes and RS decoding systems that require higher system operating frequencies.

Industrial applicability

The RS decoding apparatus disclosed by the present invention can be flexibly constructed into decoders of different decoding modes by a simple basic unit (PEi), and the decoder has high-speed processing performance and has Smaller critical path delays can meet the needs of higher system operating frequencies. The key polynomial solving device disclosed by the invention realizes the calculation of the error value polynomial coefficient in the process of RS decoding by using the IBM algorithm, and has the characteristics of structural rules. Therefore, the present invention solves the shortcomings of the prior art RS decoding process, such as slow operation speed, large critical path delay, and irregular hardware structure.

Claims

An RS decoding apparatus, comprising an accompanying matrix calculation module for sequentially processing input code words

(101), a key polynomial solving module (102), and an error location search and error value calculating module (103); wherein:

The key polynomial solving module (102) further includes a difference calculating module (201) for calculating an error value polynomial coefficient and an error position updating module (202) for calculating an error position polynomial; the difference calculating module (201) includes a 2t order connection The incremental difference is calculated by the basic unit PEi and the controller (402), and the value range of i is 0, 1, ... 2t-l; 0, the initial value of the intermediate variable and the incremental difference is from the (2t-l) The level basic unit input, the control signal and the accompanying polynomial coefficient S are input in parallel to each level of the basic unit, the feedback generated by the 0th level basic unit is returned to the controller (402), the incremental difference ^"), the calculated intermediate amount), and The control signal for RS (n, k) coding has 1 = (nk) /2, where (r) = _+r (r) ;

The input of the incremental difference calculation basic unit PEi is an intermediate variable ? , an incremental difference ^ ) and r) , and the output is an intermediate variable W, an incremental difference ^ and ^ W; wherein the two are obtained by the first multiplier Product and. The sum of the product of W and the intermediate variable obtained by the second multiplier is input to the first register (311), thereby obtaining ' _i+1 (r) and (r) are also gated by the control signal ^M cW through the second selection selector An intermediate variable is input to the second multiplier by the second register ( ₃₂₁ ).

The RS decoding device according to claim 1, wherein the error value polynomial coefficient output by the difference calculation module (201) is input to an error location update module (202), and the error location update module (202) Outputting an updated error location polynomial, the output of the difference calculation module (201) and the error location update module (202) being input to the error location search and error value calculation module (103) to calculate the error location and the error value .

The RS decoding apparatus according to claim 2, wherein the difference calculation module (201) calculates the increase according to the input adjoint polynomial coefficient S and the error position polynomial coefficient (W...W). The amount difference is then generated by the control module (204) to generate a corresponding calculated intermediate amount and control signal. (), sent to the error location update module (202); the error location update module (202) calculates an updated error location polynomial coefficient (W ... W) feedback to the difference calculation module (201), The above process is iterated 2t times to get the final error location polynomial system. Number ( AW ... ( ^r ) ) and the corresponding incremental difference ^ ^r ).

4. The RS decoding apparatus according to claim 2, further comprising an error correction module, wherein the input codeword passes through the buffer and the output of the error location search and error value calculation module (103) respectively At the same time, the error correction module is input to obtain a decoded output. 5. A key polynomial solving apparatus for use in an RS decoding apparatus, comprising: a difference calculation module (201) for solving an error value polynomial coefficient; and an error position updating module (202) for calculating an error position polynomial coefficient; wherein: the difference The calculation module (201) comprises a 2t-level incremental difference calculation basic unit PEi and a controller (402), wherein the value range of i is 0, 1, ... 2t-l; 0, intermediate variables and incremental differences The initial value is input from the (2t-l)th basic unit, and the control signal ⁽ and the adjoint polynomial coefficient S are input in parallel to each level of the basic unit, and the feedback generated by the 0th basic unit is returned to the controller (402), generating Quantity difference ^"), calculation of the intermediate amount) and control signals for RS (n, k) encoding,

= S _1+r (r); The input of the incremental difference calculation base unit PEi is an intermediate variable ? , an incremental difference ^ ) and an output as an intermediate variable? ^], incremental difference ^〕 and ^ W; where and the product sum of the two obtained by the first multiplier. w and the sum of the products of the intermediate variables obtained by the second multiplier are input to the first register (311), thereby obtaining ' _i+1 (r) and (r) are also gated by the control signal ^M cW through the second selection selector An intermediate variable is input to the second multiplier by the second register ( ₃₂₁ ). The RS decoding key using the apparatus as claimed in claim 5, wherein the polynomial solving means, wherein, said difference calculation module (201) associated polynomial coefficients according to the error location polynomial coefficients and S ^(Lambda input. (.. .... W) calculating the incremental difference and then generating a corresponding calculated intermediate amount and control signal by the control module (204), and transmitting the error to the error location update module (202); the error location update module (202) calculates The updated error position polynomial coefficient ( ^Λ . ( ... ( ^r ) ) is fed back to the difference calculation module ( 201 ), and the above process is iterated 2t times to obtain the final error position polynomial coefficient ( . . . ) And the corresponding incremental difference ^r ).