TWI457751B - Tandem fault tolerant device - Google Patents

Description

Tandem fault tolerant multiplying device

The present invention relates to a tandem fault-tolerant multiplying apparatus, and more particularly to a tandem fault-tolerant multiplying apparatus that implements error correction of a multiplication operation based on an operation result of a prediction detecting unit and an actual detecting unit.

Galois Field (GF) or Finite Field (Arithmetic Field) arithmetic is often applied to error correction codes and public key cryptosystems, especially public key cryptosystems that require arithmetic operations in finite fields, such as ellipses. (elliptic) and hyperelliptic cryptosystem (hyperelliptic cryptostsyems curve).

With the continuous growth and popularity of computer networks, communication technologies and digital information, how to ensure the security and correctness of data transmission is becoming more and more important. However, since the implanted error-based attack method has been proven to break asymmetric and symmetric cryptosystems, how to prevent hackers from cracking the cryptosystem has become an important issue.

A 2 ^m element is included in the finite field (Finite Field) GF(2 ^m ), where m is a positive integer, which can be expressed as a Polynomial Basis (PB). These multiplications are constructed in special indecomposable polynomials, including all-one polynomial (AOP), equidistant polynomial (ESP), and trinomial polynomial.

In the ultra-large integrated circuit (VLSI) design, the GF(2 ^m ) systolic array structure distributed in the finite field field is suitable for fast calculation, and relies on regular circuits to perform arithmetic operations. The common property of the circuit is Structural characteristics of rules such as consistency, input/output balance, simple and regular design. From the perspective of VLSI technology, although semiconductor manufacturers strive to ensure that their products are reliable, it is almost impossible to generate no errors at any time in a system; therefore, in the known time cycle, environment and prescribed methods In a system function, it is very important to construct a reliable computing environment.

Therefore, how to design a tandem fault-tolerant multiplying device that can provide instant error correction capability to GF(2 ^m ) bit-serial output multipliers has become the goal of related manufacturers and related R&D personnel.

The present inventors have actively developed the conventional in-line fault-tolerant multiplying device because of the inability to provide immediate error correction for the GF(2 ^m ) bit string-output multiplier, in order to improve the above-mentioned existing Disadvantages, after continuous experimentation and efforts, the present invention has finally been developed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a tandem fault tolerant multiplying device that provides instant error correction capability to a GF (2 ^m ) bit tandem output type multiplier.

In order to achieve the above object, the tandem fault-tolerant multiplying device of the present invention comprises: a register B storing a second element B of a finite field GF(2 ^m ); a series of multiplication units, Connected to the register B, the first element A of the finite field GF(2 ^m ) is multiplied by the second element B to obtain a third element C, wherein the first element A, The second element B and the third element C are expressions of the polynomial base {1, x, ..., x ^m-1 }, and all coefficients are 0 or 1; a register C, The serial multiplication unit is connected, and stores the third element C; a prediction detection unit is connected to the serial multiplication unit and the register C, and calculates the detection according to the product operation result of the serial multiplication unit The value includes a prediction row detection circuit, a prediction column detection circuit, and a prediction diagonal detection circuit; an actual detection unit is connected to the serial multiplication unit, the prediction detection unit, and the temporary register C, and is based on The product operation result of the serial multiplication unit calculates the actual detection value, which includes an actual a detection circuit, an actual column detection circuit and an actual diagonal detection circuit; a calculation error location unit connected to the prediction detection unit and the actual detection unit, and the detection value calculated according to the prediction detection unit and the actual detection The unit calculates the actual detected value, and calculates the error value of the product operation result; a register E is connected to the calculated error position unit, and stores the error value of the product operation result; an error correction unit is associated with the The register C and the register E are connected, and correct the third element C according to the error value of the product operation result; and an alpha module circuit is connected to the error correction unit, the alpha module circuit It consists of m 2-input AND gates and m 2-input XOR gates, and calculates C _i =C _i-1 x mod F(x).

Through the system described above, the present invention provides instant error correction for GF(2 ^m ) bit string output multipliers.

The preferred embodiments of the present invention are described in detail below with reference to the drawings.

Referring to the first, second, third and seventh figures, the tandem fault tolerant multiplying device (1) of the present invention comprises: a register B (10) storing a finite field GF (2 ^m ) a second element B; a serial multiplication unit (11) connected to the register B (10), one of the first element A and the second element of a finite field GF (2 ^m ) B performs a product operation to obtain a third element C, wherein the first element A, the second element B, and the third element C are polynomial bases {1, x, ..., x ^m-1 } Expression, and all coefficients are 0 or 1; a register C (12) is connected to the serial multiplication unit (11), and stores the third element C; a prediction detection unit (13) Connected to the serial multiplication unit (11) and the register C(12), and according to the product operation result of the serial multiplication unit (11), the detection value is calculated, and includes a prediction line detection circuit (130) a prediction column detection circuit (131) and a prediction diagonal detection circuit (132); an actual detection unit (14), the serial multiplication unit (11), the prediction detection unit (13), and the temporary storage C (12) is connected, and according to the The result of the product operation of the serial multiplication unit (11) calculates an actual detection value, which includes an actual line detection circuit (140), an actual column detection circuit (141), and an actual diagonal detection circuit (142); The error location unit (15) is connected to the prediction detection unit (13) and the actual detection unit (14), and is calculated according to the detection value calculated by the prediction detection unit (13) and the actual detection unit (14). The actual detected value is used to calculate the error value of the product operation result; a register E (16) is connected to the calculated error position unit (15), and stores the error value of the product operation result; an error correction unit ( 17) is connected to the register C (12) and the register E (16), and corrects the third element C according to the error value of the product operation result; and an alpha module circuit (18) Connected to the error correction unit (18), which consists of m 2-input AND gates and m 2-input XOR gates. And calculate C _i =C _i-1 x mod F(x).

Please refer to the fourth to sixth diagrams, wherein the predicted row detection circuit (130) is defined as The prediction column detection circuit (131) is defined as The predicted diagonal detection circuit (132) is defined as An auxiliary polynomial is expressed as W _i = w _{i , 0} + w _{i , 1} x +...+ w _{i , n -1} x ^{n -1} , and w _{i , j} = c _{i , nj + n -1} , It is the k-th cyclic displacement of the auxiliary polynomial W.

Referring to Figures 8 to 10, the actual line detection circuit (140) is defined as The actual column detection circuit (141) is defined as The actual diagonal detection circuit (142) is defined as , P _Cj is a detection byte, which includes n= One bit, the detection byte is defined as follows:

In a preferred embodiment of the present invention, the tandem fault-tolerant multiplying device (1) of the present invention further includes a row symptom value, a column symptom value, a pair of angle symptom values, and a calculation error polynomial, and the calculation error The polynomial calculates the result of the product calculation, C _i , which is defined as .

The line symptom value is defined as , the column symptom value is defined as , the diagonal symptom value is defined as .

The calculation error polynomial calculates the error value of each bit of the product operation result of the serial multiplication unit (11) according to the line symptom value, the column symptom value, and the diagonal symptom value. . Error Correction The i-th loop calculation C _i is based on the equation C _i =C _i +E _{Ci to} complete the error correction.

Please refer to the first, second, fourth to sixth and eighth to thirteenth drawings. In order to make it easier for your review board to understand the tandem fault-tolerant multiplying device (1) of the present invention, an embodiment is described as follows:

The finite field GF(2 ^m ) is composed of an indecomposable polynomial The resulting polynomial base representation where x is the root of F ( x ), N = {1, x , x ² , ..., x ^{m -1} } is GF(2 ^m ).

The first element , the second element And the serial multiplication unit (11) performs a product operation on the first element A and the second element B, and the obtained third element It can be expressed as follows: C = AB = ( a ₀ + a ₁ x + a ₂ x ² +... + a _{m -1} x ^{m -1} ) B = a ₀ B + a ₁ Bx + a ₂ Bx ² +...+ a _{m -1} Bx ^{m -1} =(...(( a _{m -1} B ) x + a _{m -2} B ) x +... a ₁ B ) x + a ₀ B (Equation 1)

The equation 1 is the most significant bit (MSB) multiplication algorithm, and the multiplication structure includes m loop operations. According to the equation 1, the most significant bit multiplication algorithm is a multiplication algorithm, and the multiplication algorithm is: input: A, B GF(2 ^m ) Output: C=AB mod F ( x )1 C ₀ =0 2 For i=1 to m 3 C _i = C _{i -1} x + a _{m - i} B mod F ( x ) (Equation 2) 4 End for 5 Return C _m

Equation 2 is the core operation of the most significant bit multiplication algorithm, F(x)= x ^m + f _{m -1} x ^{m -1} + f _{m -2} x ^{m -2} +...+ f ₁ x + f ₀ is the generator polynomial of the finite field GF(2 ^m ). In order to represent the bit operation program in detail, the equation 2 can be expressed as: C _i = C _{i -1} x + a ^{m -1} B mod F ( x ) (equation 3) = c _{i -1, 0} x + c _{i - 1,1} x ² +...+ c _{i -1, m -2} x ^{m -1} + c _{i -1, m -1} ( f _{m -1} x ^{m -1} + f _{m -2} x ^{m -2} +...+ f ₁ x + f ₀ ) + a _{m - i} ( b ₀ + b ₁ x + b ₂ x ² +... + b _{m -1} x ^{m -1} ) = c _{i , 0} + c _{i , 2} x + c _{i , 2} x ² +...+ c _{i , m -1} x ^{m -1} where c _{i ,0} = c _{i -1, m -1} f ₀ + a _{m - i} b ₀ ; Suppose K = k ₀ + k ₁ x +...+ k _{m -1} x ^{m -1} is an element K in which all coefficients are 1 or 0. A parity detection function can be defined to detect the coefficient of the element K: P _k = k ₀ + k ₁ +...+ k _{m -1} mod 2 (Equation 5) For example, K = x + x ² + x ⁵ , the detected value P _k = 3 mod 2 = 1; if K = x + x ² + x ⁴ + x ⁵ , the detected value P _k = 4 mod 2 = 0 is obtained. In order to verify the correctness of the output of the element K, the element K can be estimated by the following certainty: assuming K=AB mod F(x), where A and B are the first of the finite field GF(2 ^m ), respectively. Element A and the second element B. Let P _{k be} the actual detected value of the element K, obtained by the actual detecting unit (14), and The predicted detection value for this element K is obtained by the prediction detecting unit (13). If , indicating that the element K is correct; otherwise, , indicating that the element K is wrong.

For example, if the element K is K=x+ x ² + x ⁵ , the actual detected value P _k =1 can be obtained by the actual detecting unit (14). If the calculated element K is K=x+ x ² + x ⁴ + x ⁵ , the actual detected value can be obtained by the actual detecting unit (14). . When P _k and After calculation, the result is , that is, the calculation result of the element K is implanted with an error value.

Then, according to the multiplication procedure of the algorithm, it is assumed that the calculation result of the third element C is C= c ₀ + c ₁ x +...+ c _{m -1} x ^{m -1} , and the result of the third element C is preset Arrange in a two-dimensional array, such as the following equation:

Where m=n ² .

According to the detection structure defined by the equation 5, the matrix arrangement method of the equation 6 can define three groups of detection bits, which are respectively a column of detection bits. One-line detection byte And a pair of angle detection bytes And each detection byte contains n bits. The definition of each detection byte is as follows:

For example, if the third element C is C= c ₀ + c ₁ x +...+ c ₈ x ⁸ , according to Equation 7a to Equation 7c, the detection bits in the three directions can be calculated as follows:

Column detection byte:

Row detection byte:

Diagonal detection byte:

Based on the calculation procedure of the multiplication algorithm, the calculation procedure of the three detection bytes of each loop is as follows:

(a) Calculate the row detection byte

Detecting a byte according to the definition of Equation 8, the second element B = ( b ₀ , b ₁ , ..., b _{m -1} ), The row detection byte of C _i =( c _{i ,0} , c _{i ,1} ,..., c _{i , m -1} ) can be expressed as:

among them Based on the definition of the above-mentioned row detection byte, an auxiliary polynomial W needs to be defined to simplify Calculation.

Definition 1: According to the structure of the equation 6, an element C _{i is} arranged into a two-dimensional matrix, and the last column of the two-dimensional matrix is used to define an auxiliary polynomial W _i = w _{i , 0} + w _{i , 1} x +... + w _{i , n -1} x ^{n -1} , where w _{i , j} = c _{i , nj + n -1} .

Definition 2: Assume that W _i = w _{i , 0} + w _{i , 1} x +...+ w _{i , n -1} x ^{n -1} is a auxiliary polynomial, and the k-th cyclic displacement of the auxiliary polynomial W _i can be expressed as

From the multiplication algorithm, the equation 3 is the core operation of the multiplication, that is, C _i = C _{i -1} x + a _{m - i} B mod F ( x ), and the row detection bit group for calculating the element C _i can represent to make From the polynomial base representation relationship, C _{i -1} x can be expressed as

In a preferred embodiment of the invention, the equation 11 can be calculated using m 2-input AND gates and m 2-input multiplex gates (XOR gates).

among them

Calculate using the matrix representation of Equation 6 The following relationships can be obtained:

Therefore, with Equation 12, Equation 10 can be simplified to:

(b) Calculate column detection bytes

Detecting a byte according to the definition of Equation 7, the second element B = ( b ₀ , b ₁ , ..., b _{m -1} ), , the column detection byte of C _i =( c _{i ,0} , c _{i ,1} ,..., c _{i , m -1} ) can be expressed as

among them According to the calculation of the row detection byte, as in Equation 14, we can directly derive the column detection byte. The relationship is as follows: Second, we observe the polynomial (as in Equation 11) is the cyclic displacement of the polynomial C _{i -1} once, ie (Equation 16) Using the matrix representation of Equation 6, we can get as follows: Therefore, column detection bytes The following equation can be obtained

(c) Calculate the diagonal detection byte

Detecting a byte according to the definition of Equation 7, the second element B = ( b ₀ , b ₁ , ..., b _{m -1} ), The diagonal detection byte of C _i =( c _{i ,0} , c _{i ,1} ,..., c _{i , m -1} ) can be expressed as:

among them According to the calculation of the row detection byte as in Equation 13, we can directly derive the diagonal detection byte The relationship is as follows: Observing the matrix representation of Equation 6, we can get as follows: among them (Equation 22) Therefore, the diagonal detection byte The following equation can be obtained

Finally, after each loop calculation, the actual detecting unit (12) calculates the actual detecting byte according to the equation 7. and And calculating the prediction detection byte according to the equations 13, 18, and 23, respectively. and . Assuming that the three sets of symptom values S ⁽⁰⁾ , S ⁽¹⁾ and S ⁽²⁾ are the line symptom value, the column symptom value, and the diagonal symptom value, then the three groups of syndrome values are calculated:

The calculated error position unit (15) is used to evaluate the error position of each loop operation result C _i = c _{i , 0} + c _{i , 1} x + ... + c _{i , m -1} x ^{m -1} a position error polynomial for C _i , where The error value of the i-th position of the multiplication result C _i . From the equation 7, the calculated error position unit (15) can obtain three sets of syndrome values and position error polynomials The coefficient relationship and the relationship with the error position value of c _i are as follows:

If the third element C is multiplied , the position error polynomial of the third element C can be expressed as So each Yes can be expressed as follows:

From the above equation, the calculated error location unit (15) can be found Exist in three detection bits such as . Based on the above characteristics, a vector can be defined To represent the error condition of c ₀ bit, this vector is the error position vector. According to this vector relationship, the error condition of c ₀ bit is analyzed as follows:

Case 1. When the error location occurs at c ₀ bits, you can get =(1,1,1).

Case 2. When the error location occurs in c ₁ bit, you can get = (1,0,0).

Case 3. When the error location occurs in c ₀ and c ₁ bits, you can get = (0, 1, 1).

In case 1. and condition 3., vector There are at least two "1"s; and in the case of case 2., the vector There is only one "1". Under these three conditions, the error conditions for determining the occurrence of c ₀ bits are (1) and (3). Therefore, in order to satisfy these three conditions, the majority voting method is used to determine the possible error values of c ₀ bits as follows:

If (0,1,1), the error value of c ₀ bit is =1.

If When =(0,1,1), the error value of c ₀ bit is =1.

If When =(1,0,1), the error value of c ₀ bit is =1.

If When =(1,1,0), the error value of c ₀ bit is =1.

If When =(0,0,1), the error value of c ₀ bit is =0.

If When =(0,1,0), the error value of c ₀ bit is =0.

If When =(1,0,0), the error value of c ₀ bit is =0.

If When =(0,0,0), the error value of c ₀ bit is =0.

From the above characteristics, we can directly calculate the error value of c ₀ by using the following equation

Similarly, due to the position error polynomial of the third element C, the error position vector of c ₁ is , available . Position error polynomial After the calculation is completed, the error correction unit (17) can use the following program to implement the error correction ith loop calculation C _i .

In a preferred embodiment of the invention, the equation 28 can be calculated using m 2-input AND gates and m 2-input multiplex gates (XOR gates).

Referring to the second figure, in a preferred embodiment of the present invention, the serial multiplication unit (11) is mutually exclusive by m 2-input AND gates and m 2-inputs. The gate (XOR gate) is composed to calculate C _i = C _i + b _{m - i} A .

In another preferred embodiment of the present invention, the calculated error location unit (15) includes a nine-input XOR gate and a nine-degree decision (MV) (not shown). The components of each MV circuit are composed of three-input AND gates and two-input XOR gates (not shown) to calculate the error value of the result of the multiplication of the bits.

Through the above apparatus and method, the present invention can provide instant error correction capability for a GF (2 ^m ) bit serial output type multiplier. Moreover, its structural form is not easily reached by those skilled in the art, and it is novel and progressive.

Through the above detailed description, it can fully demonstrate that the object and effect of the present invention are both progressive in implementation, highly industrially usable, and are new inventions not previously seen on the market, and fully comply with the invention patent requirements. , 提出 apply in accordance with the law. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the invention. All changes and modifications made in accordance with the scope of the invention shall fall within the scope covered by the patent of the invention. I would like to ask your review committee to give a clear explanation and pray for it.

(1)‧‧‧Inline fault-tolerant multiplying device

(10) ‧‧‧Storage B

(11)‧‧‧ Serial multiplication unit

(12) ‧‧‧Storage C

(13) ‧‧‧predictive detection unit

(130)‧‧‧Predicted line detection circuit

(131)‧‧‧Predicted column detection circuit

(132)‧‧‧Predicted diagonal detection circuit

(14) ‧‧‧ actual detection unit

(140) ‧‧‧ Actual line detection circuit

(141)‧‧‧ Actual column detection circuit

(142) ‧‧‧ Actual diagonal detection circuit

(15)‧‧‧Computed error location unit

(16) ‧‧‧Storage E

(17)‧‧‧Error correction unit

(18)‧‧‧α module circuit

The first figure is a system architecture diagram of the tandem fault tolerant multiplying device of the present invention.

The second figure is a logic circuit diagram of the serial multiplication unit of the present invention.

The third figure is an architectural diagram of the predictive detection unit of the present invention.

The fourth figure is a circuit diagram of the predictive line detecting circuit of the present invention.

The fifth figure is a circuit diagram of the predictive column detecting circuit of the present invention.

Figure 6 is a circuit diagram of the predicted diagonal detection circuit of the present invention.

The seventh diagram is an architectural diagram of the actual detection unit of the present invention.

The eighth figure is a circuit diagram of the actual line detecting circuit of the present invention.

The ninth drawing is a circuit diagram of the actual column detecting circuit of the present invention.

The tenth figure is a circuit diagram of the actual diagonal detecting circuit of the present invention.

The eleventh drawing is a circuit diagram of the calculation error position unit of the present invention.

The twelfth figure is a circuit diagram of the error correction unit of the present invention.

The thirteenth drawing is a circuit diagram of the alpha module circuit of the present invention.

(1)‧‧‧Inline fault-tolerant multiplying device

(10) ‧‧‧Storage B

(11)‧‧‧ Serial multiplication unit

(12) ‧‧‧Storage C

(13) ‧‧‧predictive detection unit

(130)‧‧‧Predicted line detection circuit

(131)‧‧‧Predicted column detection circuit

(132)‧‧‧Predicted diagonal detection circuit

(14) ‧‧‧ actual detection unit

(140) ‧‧‧ Actual line detection circuit

(141)‧‧‧ Actual column detection circuit

(142) ‧‧‧ Actual diagonal detection circuit

(15)‧‧‧Computed error location unit

(16) ‧‧‧Storage E

(17)‧‧‧Error correction unit

(18)‧‧‧α module circuit

Claims (7)

A serial fault-tolerant multiplying device includes: a register B storing a second element B of a finite field GF (2 ^m ); and a serial multiplication unit connected to the register B, Performing a product operation on the first element A and the second element B in the finite field GF(2 ^m ) to obtain a third element C, wherein the first element A, the second element B, and the first The three-element C is a representation of the polynomial base {1, x, ..., x ^m-1 }, and all coefficients are 0 or 1; a register C is connected to the serial multiplication unit, and Storing the third element C; a prediction detecting unit is connected to the serial multiplication unit and the register C, and calculating a detection value according to a product operation result of the serial multiplication unit, which includes a prediction line detection a circuit, a prediction column detection circuit and a prediction diagonal detection circuit; an actual detection unit is connected to the serial multiplication unit, the prediction detection unit, and the register C, and is operated according to the product of the serial multiplication unit As a result, the actual detected value is calculated, which includes an actual line detecting circuit and an actual column detecting circuit. And an actual diagonal detection circuit; a calculation error location unit, connected to the prediction detection unit and the actual detection unit, and based on the detection value calculated by the prediction detection unit and the actual detection value calculated by the actual detection unit, Calculating the error value of the product operation result; a register E is connected to the calculation error location unit, and storing the error value of the product operation result; an error correction unit, and the register C and the temporary storage The device E is connected, and corrects the third element C according to the error value of the product operation result; and an alpha module circuit is connected to the error correction unit, wherein the α module circuit is composed of m 2-inputs and gates (AND gate) and m 2-input mutexes or XOR gates, and calculate C _i =C _i-1 x mod F(x). The tandem fault tolerant multiplying device of claim 1, wherein the actual row detecting circuit is defined as The actual column detection circuit is defined as The actual diagonal detection circuit is defined as , P _Cj is a detection byte, which includes n= One bit, the detection byte is defined as follows: The tandem fault tolerant multiplying device of claim 1, wherein the predicted row detecting circuit is defined as The predicted column detection circuit is defined as The predicted diagonal detection circuit is defined as The auxiliary polynomial is expressed as W _i = w _{i , 0} + w _{i , 1} x +...+ w _{i , n -1} x ^{n -1} , and w _{i , j} = c _{i , nj - n -1} , It is the k-th cyclic displacement of the auxiliary polynomial W. The tandem fault-tolerant multiplication device according to claim 1, further comprising a line symptom value, a column symptom value, a pair of angle symptom values, and a calculation error polynomial, wherein the calculation error polynomial system calculates the product operation calculation The result C _i , which is defined as . The tandem fault tolerant multiplying device of claim 4, wherein the line symptom value is defined as , the column symptom value is defined as , the diagonal symptom value is defined as . The tandem fault tolerant multiplication apparatus according to claim 5, wherein the calculation error polynomial calculates the serial multiplication unit according to the line symptom value, the column symptom value, and the diagonal symptom value. The error value of each bit of the result of the product operation . The tandem fault tolerant multiplying apparatus of claim 4, wherein the error correction ith loop calculation C _i is based on the equation C _i =C _i +E _{Ci to} complete the error correction.