CN114124107A - Method and device for calculating cyclic redundancy check - Google Patents

Method and device for calculating cyclic redundancy check Download PDF

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CN114124107A
CN114124107A CN202111294892.7A CN202111294892A CN114124107A CN 114124107 A CN114124107 A CN 114124107A CN 202111294892 A CN202111294892 A CN 202111294892A CN 114124107 A CN114124107 A CN 114124107A
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crc
coefficient matrix
cyclic redundancy
redundancy check
matrix
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梁伟杰
何代明
杨磊
李成武
贾莹莹
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Tianjin Zhaoxun Electronic Technology Co ltd
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    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
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    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/727—Modulo N arithmetic, with N being either (2**n)-1,2**n or (2**n)+1, e.g. mod 3, mod 4 or mod 5

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Abstract

The invention discloses a method and a device for calculating cyclic redundancy check. The calculation method comprises the following steps: (1) constructing a coefficient matrix F according to a generating polynomial G (x) of the cyclic redundancy check; (2) find FNThen taking a module 2, wherein the obtained matrix is a CRC coefficient matrix A; (3) judging the size relation between the width M of the input data and the number N of generating polynomial, and when N is more than or equal to M, comparing FNTaking a module 2, and obtaining a DATA coefficient matrix B from the first M columns of the CRC coefficient matrix A; when (X-1) N<When M is less than or equal to XN, for FN、F2N、F3N…FXNRespectively taking the model 2 and FXNThe last M- (X-1) N column of (C) is spliced at { F(X－1)N，…，F3N，F2N，FNBefore the matrix is multiplied, a DATA coefficient matrix B is obtained; (4) and obtaining a CRC calculation result according to a calculation formula of the cyclic redundancy check. The invention adopts a special algorithm which is specially designed, and can meet the calculation requirements of cyclic redundancy check of different polynomials.

Description

Method and device for calculating cyclic redundancy check
Technical Field
The invention relates to a Cyclic Redundancy Check (CRC) calculation method, and also relates to a corresponding calculation device, belonging to the technical field of digital communication.
Background
The cyclic redundancy check is a hash function check method for generating a short check code according to file data, and is mainly used for checking errors which may occur after data transmission or storage. The verification process comprises the following steps:
(1) selecting a divisor for performing division operation on a received frame when a receiving end is used for checking;
(2) according to the selected divisor binary digit number (assumed as K bits, K is a positive integer), then adding K-1 bits of '0' to the data frame to be transmitted (assumed as m bits, m is a positive integer), and dividing the new frame added with K-1 '0' (totally m + K-1 bits) by the divisor in a mode of 'modulo 2 division', wherein the obtained remainder (also binary bit string) is the CRC check code of the frame, which is also called FCS (frame check sequence);
(3) and finally, dividing the new frame by the divisor selected previously in a mode of 'modulo-2 division' at the receiving end, wherein if no remainder exists, the frame is indicated to have no error in the transmission process, and otherwise, the error occurs.
In chinese patent application with application publication No. CN112350735A, a method and system for calculating cyclic redundancy check are disclosed, in which an initial value of an initial setting register and a value of a polynomial setting register are configured according to software, and the value of the polynomial setting register is input into a CRC operation register to satisfy CRC polynomial operation; inputting data to be calculated into a CRC operation register for operation, wherein the CRC operation register comprises N CrcCal operation units, and the N CrcCal operation units sequentially perform iterative operation through Tap signals; if the input register inputs a first byte for the operation of the CRC operation register, the initial value configured by the initial setting register is input into the first CrcCal operation unit, and if the input register inputs a non-first byte for the operation of the CRC operation register, the Nth Tap signal is input into the first CrcCal operation unit. According to the technical scheme, the CRC polynomial and the initial calculation value are configured through software, and a digital circuit is used for meeting CRC calculation of different polynomials.
However, the implementation of existing CRC algorithms in digital circuits is based on different classifications of each CRC algorithm's polynomial. Different polynomial CRC algorithms need to be implemented using different digital circuits. For different application scenarios, a plurality of CRC algorithms with different polynomials may be required, so that the CRC digital circuit implemented in this way has poor adaptability in different application scenarios, and it is also difficult to design a digital circuit corresponding to the CRC algorithm of each polynomial in an actual product, so that related products are limited in application scenarios.
Disclosure of Invention
The invention provides a method for calculating cyclic redundancy check.
Another technical problem to be solved by the present invention is to provide a cyclic redundancy check calculation apparatus.
In order to achieve the purpose, the invention adopts the following technical scheme:
according to a first aspect of the embodiments of the present invention, there is provided a method for calculating a cyclic redundancy check, including the steps of:
(1) constructing a coefficient matrix F according to a generating polynomial G (x) of the cyclic redundancy check;
(2) find FNThen taking the modulus 2, the obtained matrix is a CRC coefficient matrixA；
(3) Judging the size relation between the width M of the input data and the number N of generating polynomial, and when N is more than or equal to M, comparing FNTaking a module 2, and obtaining a DATA coefficient matrix B from the first M columns of the CRC coefficient matrix A; when (X-1) N<When M is less than or equal to XN, for FN、F2N、F3N…FXNRespectively taking the model 2 and FXNThe last M- (X-1) N column of (C) is spliced at { F(X－1)N，…，F3N，F2N，FNBefore the matrix is multiplied, a DATA coefficient matrix B is obtained; wherein X is a positive integer and X is more than or equal to 2;
(4) obtaining CRC calculation result CRC according to the following calculation formula of cyclic redundancy checkout：
crcout＝A*crcin⊕B*datain
Wherein, A is CRC coefficient matrix, B is DATA coefficient matrix, ^ is logic XOR operation, CRCinData for the last CRC calculationinIs the input data to be verified.
Preferably, in the step (1), the coefficient matrix F is constructed according to a generator polynomial g (x):
Figure BDA0003336257800000021
wherein, G' is a polynomial matrix corresponding to the generator polynomial G (x), and E is an identity matrix.
Wherein preferably, in the step (4), crcinFor crc in digital circuitsoutDelaying the output result of one period.
Preferably, in the step (4), the binary multiplication is implemented by '&' and the modulo-2 operation is implemented by exclusive or '^' according to bit.
According to a second aspect of the embodiments of the present invention, there is provided a cyclic redundancy check calculation apparatus, including a processor and a memory, the processor reading a computer program in the memory to perform the following operations:
(1) constructing a coefficient matrix F according to a generating polynomial G (x) of the cyclic redundancy check;
(2) find FNThen taking a module 2, wherein the obtained matrix is a CRC coefficient matrix A;
(3) judging the size relation between the width M of the input data and the number N of generating polynomial, and when N is more than or equal to M, comparing FNTaking a module 2, and obtaining a DATA coefficient matrix B from the first M columns of the CRC coefficient matrix A; when (X-1) N<When M is less than or equal to XN, for FN、F2N、F3N…FXNRespectively taking the model 2 and FXNThe last M- (X-1) N column of (C) is spliced at { F(X－1)N，…，F3N，F2N，FNBefore the matrix is multiplied, a DATA coefficient matrix B is obtained; wherein X is a positive integer and X is more than or equal to 2;
(4) obtaining CRC calculation result CRC according to the following calculation formula of cyclic redundancy checkout：
crcout＝A*crcin⊕B*datain
Wherein, A is CRC coefficient matrix, B is DATA coefficient matrix, ^ is logic XOR operation, CRCinData for the last CRC calculationinIs the input data to be verified.
Compared with the prior art, the method and the device for calculating the cyclic redundancy check provided by the embodiment of the invention adopt the specially designed matrix multiplication and the column shift algorithm to be compatible with all cyclic redundancy check calculations on the premise of not increasing the hardware cost, so that a digital circuit can be used, and the calculation requirements of the cyclic redundancy check of different polynomials can be met.
Drawings
Fig. 1 is a flowchart of a method for calculating a cyclic redundancy check according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a cyclic redundancy check calculation apparatus according to an embodiment of the present invention.
Detailed Description
The technical contents of the invention are described in detail below with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, a method for calculating Cyclic Redundancy Check (CRC) provided in the embodiment of the present invention at least includes the following steps:
(1) constructing a coefficient matrix F according to a generating polynomial G (x) of the cyclic redundancy check;
specifically, it is assumed that the order of the generator polynomial is N and the width of the input data is M (M, N is a positive integer, the same applies hereinafter). Constructing a coefficient matrix F according to the generator polynomial G (x):
Figure BDA0003336257800000041
wherein, G' is a polynomial matrix corresponding to the generator polynomial G (x), and E is an identity matrix.
(2) Find FNThen taking a module 2, wherein the obtained matrix is a CRC coefficient matrix A;
(3) judging the size relation between the width M of the input data and the number N of generating polynomial, and when N is more than or equal to M, comparing FNTaking a modulus 2, and obtaining a DATA coefficient matrix B from the first M columns of the obtained matrix (namely, a CRC coefficient matrix A); when N is present<When M is less than or equal to 2N, to FNAnd F2NRespectively taking the model 2 and F2NThe last M-N column of (C) is spliced at FNBefore the matrix, a DATA coefficient matrix B can be obtained; when 2N is present<When M is less than or equal to 3N, for FN、F2N、F3NRespectively taking the model 2 and F3NThe last M-2N column of (C) is spliced at { F2N，FNBefore matrix, the DATA coefficient matrix B … … can be obtained similarly when (X-1) N<When M is less than or equal to XN, for FN、F2N、F3N…FXNRespectively taking the model 2 and FXNThe last M- (X-1) N column of (C) is spliced at { F(X－1)N，…，F3N，F2N，FNBefore the matrix is multiplied, a DATA coefficient matrix B can be obtained; wherein X is a positive integer and X is not less than 2;
(4) obtaining CRC calculation result CRC according to the following calculation formula of cyclic redundancy checkout：
crcout＝A*crcin⊕B*datain (2)
Wherein, A is CRC coefficient matrix, B is DATA coefficient matrix, ^ is logic XOR operation, CRCinIs as followsThe result of a CRC calculation of one time, i.e. CRC in a digital circuitoutDelaying the output result, data, of one cycleinIs the input data to be verified.
In the following, we use the polynomial g (x) ═ x8+x7+x4+x3+x1The case of +1 will be specifically described.
In this embodiment, the polynomial degree N is 8, and the data width M is 8; the corresponding coefficient matrix F is shown as:
Figure BDA0003336257800000042
for the coefficient matrix F, F is obtainedNThen, taking the modulus 2 to obtain the matrix as the CRC coefficient matrix A. Next, F can be found through the rule after matrix operationNThe first M columns after modulo-2 are equal to the DATA coefficient matrix B, so the DATA coefficient matrix B can be obtained by the above method.
Specifically, in the above-described embodiment, the CRC coefficient matrix a is (F)NTaking 2) ═ F8Taking a model 2, wherein N is 8); DATA coefficient matrix B ═ FNTaking 2) ═ F8Taking the model 2, wherein N is 8).
That is to say that the first and second electrodes,
F2taking the model 2 to obtain
Figure BDA0003336257800000051
F3Taking the model 2 to obtain
Figure BDA0003336257800000052
F3Taking the model 2 to obtain
Figure BDA0003336257800000053
……
F8Taking the model 2 to obtain
Figure BDA0003336257800000054
And so on, matrix FnExpressed in the form of a matrix of columns, namely:
Figure BDA0003336257800000055
Figure BDA0003336257800000056
the induction method can obtain that:
Figure BDA0003336257800000057
Figure BDA0003336257800000058
wherein the content of the first and second substances,
Figure BDA0003336257800000059
Figure BDA0003336257800000061
Figure BDA0003336257800000062
Figure BDA0003336257800000063
Figure BDA0003336257800000064
Figure BDA0003336257800000065
Figure BDA0003336257800000066
Figure BDA0003336257800000067
in digital circuit, binary multiplication is used'&'implementation, modulo-2 arithmetic is implemented with bitwise XOR'. A two-dimensional array of 8x8, known matrix F,
Figure BDA0003336257800000068
can be described by a hardware language by a recursive description method
Figure BDA0003336257800000069
In this way we can obtain the CRC coefficient matrix a. In the same manner, the DATA coefficient matrix B can be obtained.
Therefore, the corresponding CRC calculation formula can be described as:
crcout＝A&crcin^B&datain (3)
here, the polynomial g (x) x is still used8+x7+x4+x3+x1+1 for example, the CRC coefficient matrix a ═ F8Taking the mold 2, i.e.
Figure BDA00033362578000000610
Therefore, the CRC calculation result can be expressed as follows:
crcout[7]＝ crcin[0]^crcin[1]^crcin[2]^crcin[6]^datain[0]^datain[1]^data in[2]^datain[6]
crcout[6]＝crcin[2]^crcin[5]^crcin[6]^datain[2]^datain[5]^datain[6]
crcout[5]＝ crcin[1]^crcin[4]^crcin[5]^datain[1]^datain[4]^datain[5]
crcout[4]＝crcin[0]^crcin[3]^crcin[4]^datain[0]^datain[3]^datain[4]
crcout[3]＝ crcin[0]^crcin[1]^crcin[3]^crcin[6]^crcin[7]^datain[0]^datai n[1]^datain[3]^datain[6]^datain[7]
crcout[2]＝crcin[1]^crcin[5]^datain[1]^datain[5]
crcout[1]＝ crcin[0]^crcin[4]^crcin[7]^datain[0]^datain[4]^datain[7]
crcout[0]＝ crcin[0]^crcin[1]^crcin[2]^crcin[3]^crcin[7]^datain[0]^datai n[1]^datain[2]^datain[3]^datain[7]
when M, N have different values, the CRC calculation result can also be obtained according to the calculation method described above. Here, we use the polynomial g (x) ═ x8+x7+x4+x3+x1+1, the polynomial degree N is 8, and the data width M is 12, in which case N is the example<M≤2N。
Then the CRC coefficient matrix a is (F)nTaking 2) ═ F8Taking a mould 2);
DATA coefficient matrix B ═ F2nModulus 2) splicing M-N rows after modulusnBefore taking the mold 2), i.e. F16Taking the mold 2, splicing the last 4 rows at F8Before taking the matrix of modulo 2.
Will matrix FnExpressed in the form of a matrix of columns:
Figure BDA0003336257800000071
Figure BDA0003336257800000072
the induction method can obtain that:
Figure BDA0003336257800000073
Figure BDA0003336257800000074
Figure BDA0003336257800000075
wherein the content of the first and second substances,
Figure BDA0003336257800000076
Figure BDA0003336257800000077
Figure BDA0003336257800000078
Figure BDA0003336257800000081
Figure BDA0003336257800000082
Figure BDA0003336257800000083
Figure BDA0003336257800000084
Figure BDA0003336257800000085
Figure BDA00033362578000000815
Figure BDA0003336257800000086
Figure BDA0003336257800000087
Figure BDA0003336257800000088
Figure BDA0003336257800000089
Figure BDA00033362578000000810
Figure BDA00033362578000000811
Figure BDA00033362578000000812
F8taking the modulus 2, the corresponding CRC coefficient matrix is as follows:
Figure BDA00033362578000000813
F16taking the modulus 2, the corresponding CRC coefficient matrix is as follows:
Figure BDA00033362578000000814
splicing the four rows after taking the mixture in F8Before, then the DATA coefficient matrix is as follows:
Figure BDA0003336257800000091
therefore, the CRC calculation result can be expressed as follows:
crcout[7]＝ crcin[0]^crcin[1]^crcin[2]^crcin[6]^datain[0]^datain[1]^data in[2]^datain[6]^datain[11]
crcout[6]＝ crcin[2]^crcin[5]^crcin[6]^datain[2]^datain[5]^datain[6]^dat ain[10]
crcout[5]＝ crcin[1]^crcin[4]^crcin[5]^datain[1]^datain[4]^datain[5]^dat ain[9]^datain[11]
crcout[4]＝ crcin[0]^crcin[3]^crcin[4]^datain[0]^datain[3]^datain[4]^dat ain[8]^datain[10]^datain[11]
crcout[3]＝ crcin[0]^crcin[1]^crcin[3]^crcin[6]^crcin[7]^datain[0]^datai n[1]^datain[3]^datain[6]^datain[7]^datain[9]^datain[10]
crcout[2]＝ crcin[1]^crcin[5]^datain[1]^datain[5]^datain[8]^datain[9]
crcout[1]＝ crcin[0]^crcin[4]^crcin[7]^datain[0]^datain[4]^datain[7]^dat ain[8]
crcout[0]＝ crcin[0]^crcin[1]^crcin[2]^crcin[3]^crcin[7]^datain[0]^datai n[1]^datain[2]^datain[3]^datain[7]。
on the basis of the above calculation method of cyclic redundancy check, the present invention further provides a calculation apparatus of cyclic redundancy check. As shown in fig. 2, the computing device includes one or more processors 21 and memory 22. Wherein the memory 22 is coupled to the processor 21 and is configured to store one or more programs, when the one or more programs are executed by the one or more processors 21, the one or more processors 21 implement the calculation method of the cyclic redundancy check as in the above embodiments.
The processor 21 is configured to control the overall operation of the computing apparatus to complete all or part of the steps of the above-mentioned cyclic redundancy check calculation method. The processor 21 may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a Digital Signal Processing (DSP) chip, or the like. Memory 22 is used to store various types of data to support operation of the computing device, and such data may include, for example, instructions for any application or method operating on the computing device, as well as application-related data. The memory 22 may be implemented by any type or combination of volatile or non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, and the like.
In an exemplary embodiment, the computing device may be implemented by a computer chip or an entity, or a product with a certain function, and is used for executing the above-mentioned calculation method of cyclic redundancy check, and achieving the technical effect consistent with the above-mentioned method. One typical embodiment is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a vehicle-mounted human-computer interaction device, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
In another exemplary embodiment, the present invention further provides a computer readable storage medium including program instructions, which when executed by a processor, implement the steps of the method for calculating a cyclic redundancy check in any of the above embodiments. For example, the computer readable storage medium may be the memory including program instructions executable by the processor of the computing device to perform the above-described method for calculating cyclic redundancy check, and achieve the same technical effects as the above-described method.
Compared with the prior art, the method and the device for calculating the cyclic redundancy check provided by the embodiment of the invention adopt the specially designed matrix multiplication and the column shift algorithm to be compatible with all cyclic redundancy check calculations on the premise of not increasing the hardware cost, so that a digital circuit can be used, and the calculation requirements of the cyclic redundancy check of different polynomials can be met.
It will be clear to those skilled in the art that although the present invention provides method steps as described in the examples or flowcharts, more or fewer steps may be included based on conventional or non-inventive means. The order of steps recited in the embodiments is merely one manner of performing the steps in a multitude of orders and does not represent the only order of execution. When an actual apparatus or end product executes, it may execute sequentially or in parallel (e.g., parallel processors or multi-threaded environments, or even distributed data processing environments) according to the method shown in the embodiment or the figures.
In the present invention, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It should be noted that all the embodiments of the present invention are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment is mainly described as a difference from the other embodiments. In particular, for the embodiments of the computing device and the computer-readable storage medium, since they are substantially similar to the embodiments of the method, the description is simple, and the relevant points can be referred to the partial description of the embodiments of the method.
The method and apparatus for calculating cyclic redundancy check provided by the present invention are described in detail above. It will be apparent to those skilled in the art that any obvious modifications thereof can be made without departing from the spirit of the invention, which infringes the patent right of the invention and bears the corresponding legal responsibility.

Claims (8)

1. A method for calculating Cyclic Redundancy Check (CRC), comprising the steps of:
(1) constructing a coefficient matrix F according to a generating polynomial G (x) of the cyclic redundancy check;
(2) find FNThen taking a module 2, wherein the obtained matrix is a CRC coefficient matrix A;
(3) judging the size relation between the width M of the input data and the number N of generating polynomial, and when N is more than or equal to M, comparing FNTaking a module 2, and obtaining a DATA coefficient matrix B from the first M columns of the CRC coefficient matrix A; when (X-1) N<When M is less than or equal to XN, for FN、F2N、F3N…FXNRespectively taking the model 2 and FXNThe last M- (X-1) N column of (C) is spliced at { F(X－1)N，…，F3N，F2N，FNBefore the matrix is multiplied, a DATA coefficient matrix B is obtained; wherein X is a positive integer and X is more than or equal to 2;
(4) obtaining CRC calculation result CRC according to the following calculation formula of cyclic redundancy checkout：
Figure FDA0003336257790000012
Wherein A is a CRC coefficient matrix, B is a DATA coefficient matrix,
Figure FDA0003336257790000013
for logical XOR operations, crcinData for the last CRC calculationinIs the input data to be verified.
2. The method of calculating a cyclic redundancy check of claim 1, wherein:
in the step (1), a coefficient matrix F is constructed according to a generator polynomial g (x):
Figure FDA0003336257790000011
wherein, G' is a polynomial matrix corresponding to the generator polynomial G (x), and E is an identity matrix.
3. The method of calculating a cyclic redundancy check of claim 1, wherein:
in the step (4), crcinFor crc in digital circuitsoutDelaying the output result of one period.
4. The method of calculating a cyclic redundancy check of claim 1, wherein:
in the step (4), binary multiplication is realized by '&' and modulo-2 operation is realized by bitwise exclusive-or '^' operation.
5. A cyclic redundancy check calculation apparatus comprising a processor and a memory, the processor reading a computer program in the memory for performing the following operations:
(1) constructing a coefficient matrix F according to a generating polynomial G (x) of the cyclic redundancy check;
(2) find FNThen taking a module 2, wherein the obtained matrix is a CRC coefficient matrix A;
(3) judging the size relation between the width M of the input data and the number N of generating polynomial, and when N is more than or equal to M, comparing FNTaking a module 2, and obtaining a DATA coefficient matrix B from the first M columns of the CRC coefficient matrix A; when (X-1) N<When M is less than or equal to XN, for FN、F2N、F3N…FXNRespectively taking the model 2 and FXNThe last M- (X-1) N column of (C) is spliced at { F(X－1)N，…，F3N，F2N，FNBefore the matrix is multiplied, a DATA coefficient matrix B is obtained; wherein X is a positive integer and X is more than or equal to 2;
(4) obtaining CRC calculation result CRC according to the following calculation formula of cyclic redundancy checkout：
Figure FDA0003336257790000023
Wherein A is a CRC coefficient matrix, B is a DATA coefficient matrix,
Figure FDA0003336257790000022
for logical XOR operations, crcinData for the last CRC calculationinIs the input data to be verified.
6. The apparatus for calculating a cyclic redundancy check of claim 5, wherein:
in the step (1), a coefficient matrix F is constructed according to a generator polynomial g (x):
Figure FDA0003336257790000021
wherein, G' is a polynomial matrix corresponding to the generator polynomial G (x), and E is an identity matrix.
7. The apparatus for calculating a cyclic redundancy check of claim 5, wherein:
in the step (4), crcinFor crc in digital circuitsoutDelaying the output result of one period.
8. The apparatus for calculating a cyclic redundancy check of claim 5, wherein:
in the step (4), binary multiplication is realized by '&' and modulo-2 operation is realized by bitwise exclusive-or '^' operation.
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CN116861493A (en) * 2023-08-31 2023-10-10 上海芯联芯智能科技有限公司 Verification code generation method, processor and electronic equipment
CN116861493B (en) * 2023-08-31 2024-03-29 上海芯联芯智能科技有限公司 Verification code generation method, processor and electronic equipment

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