TW200641665A - Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability - Google Patents
Systolic array dual-basis multiplier having parallel output bits with on-line error detection capabilityInfo
- Publication number
- TW200641665A TW200641665A TW095131462A TW95131462A TW200641665A TW 200641665 A TW200641665 A TW 200641665A TW 095131462 A TW095131462 A TW 095131462A TW 95131462 A TW95131462 A TW 95131462A TW 200641665 A TW200641665 A TW 200641665A
- Authority
- TW
- Taiwan
- Prior art keywords
- error detection
- line error
- output bits
- parallel output
- systolic array
- Prior art date
Links
Abstract
This invention relates to a systolic array dual-basis multiplier having parallel output bits with on-line error detection capability. The multiplexer includes multiplying and transforming units. The multiplying unit includes (m+1)xm circuits that correspond to (m+1)xm cells in a form of (m+1)xm arrays, and each cell at least includes three input signal lines, three output signal lines, an AND gate, an XOR gate, and three single-bit latches. The circuit structure of the transforming unit includes a tree-like 2-input XOR gate. With these configurations, an on-line error detection algorithm can be realized, and all single-cell faults of single-function can be detected.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW095131462A TW200641665A (en) | 2006-08-25 | 2006-08-25 | Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW095131462A TW200641665A (en) | 2006-08-25 | 2006-08-25 | Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200641665A true TW200641665A (en) | 2006-12-01 |
TWI325560B TWI325560B (en) | 2010-06-01 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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TW095131462A TW200641665A (en) | 2006-08-25 | 2006-08-25 | Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability |
Country Status (1)
Country | Link |
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TW (1) | TW200641665A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI457751B (en) * | 2012-07-13 | 2014-10-21 | Univ Feng Chia | Tandem fault tolerant device |
TWI465958B (en) * | 2012-06-08 | 2014-12-21 | Univ Lunghwa Sci & Technology | Error detection of finite field multiplication devices |
-
2006
- 2006-08-25 TW TW095131462A patent/TW200641665A/en not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI465958B (en) * | 2012-06-08 | 2014-12-21 | Univ Lunghwa Sci & Technology | Error detection of finite field multiplication devices |
TWI457751B (en) * | 2012-07-13 | 2014-10-21 | Univ Feng Chia | Tandem fault tolerant device |
Also Published As
Publication number | Publication date |
---|---|
TWI325560B (en) | 2010-06-01 |
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MM4A | Annulment or lapse of patent due to non-payment of fees |