TW200641665A - Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability - Google Patents

Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability

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Publication number
TW200641665A
TW200641665A TW095131462A TW95131462A TW200641665A TW 200641665 A TW200641665 A TW 200641665A TW 095131462 A TW095131462 A TW 095131462A TW 95131462 A TW95131462 A TW 95131462A TW 200641665 A TW200641665 A TW 200641665A
Authority
TW
Taiwan
Prior art keywords
error detection
line error
output bits
parallel output
systolic array
Prior art date
Application number
TW095131462A
Other languages
Chinese (zh)
Other versions
TWI325560B (en
Inventor
Chiou-Yng Lee
Qi-Wen Qiu
Original Assignee
Univ Lunghwa Sci & Technology
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Publication date
Application filed by Univ Lunghwa Sci & Technology filed Critical Univ Lunghwa Sci & Technology
Priority to TW095131462A priority Critical patent/TW200641665A/en
Publication of TW200641665A publication Critical patent/TW200641665A/en
Application granted granted Critical
Publication of TWI325560B publication Critical patent/TWI325560B/zh

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Abstract

This invention relates to a systolic array dual-basis multiplier having parallel output bits with on-line error detection capability. The multiplexer includes multiplying and transforming units. The multiplying unit includes (m+1)xm circuits that correspond to (m+1)xm cells in a form of (m+1)xm arrays, and each cell at least includes three input signal lines, three output signal lines, an AND gate, an XOR gate, and three single-bit latches. The circuit structure of the transforming unit includes a tree-like 2-input XOR gate. With these configurations, an on-line error detection algorithm can be realized, and all single-cell faults of single-function can be detected.
TW095131462A 2006-08-25 2006-08-25 Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability TW200641665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW095131462A TW200641665A (en) 2006-08-25 2006-08-25 Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095131462A TW200641665A (en) 2006-08-25 2006-08-25 Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability

Publications (2)

Publication Number Publication Date
TW200641665A true TW200641665A (en) 2006-12-01
TWI325560B TWI325560B (en) 2010-06-01

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Family Applications (1)

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TW095131462A TW200641665A (en) 2006-08-25 2006-08-25 Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI457751B (en) * 2012-07-13 2014-10-21 Univ Feng Chia Tandem fault tolerant device
TWI465958B (en) * 2012-06-08 2014-12-21 Univ Lunghwa Sci & Technology Error detection of finite field multiplication devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI465958B (en) * 2012-06-08 2014-12-21 Univ Lunghwa Sci & Technology Error detection of finite field multiplication devices
TWI457751B (en) * 2012-07-13 2014-10-21 Univ Feng Chia Tandem fault tolerant device

Also Published As

Publication number Publication date
TWI325560B (en) 2010-06-01

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