TW201032230A - System and method for resolving request collision in a single-port SRAM - Google Patents

Abstract

A system and method for resolving request collision in a single-port static random access memory (SRAM) are disclosed. A first SRAM part and a second SRAM part of the single-port SRAM are accessed in turn. When request collision occurs, data is temporarily stored in a first or second shadow bank associated with the first or the second SRAM part which is under access. The temporarily stored data is then transferred, at a later time, to an associated one of the first/second SRAM parts while the other one of the first/second SRAM parts is being accessed.

Description

201032230 VI. Description of the Invention: [Technical Field] The present invention relates to a static random access memory (SRAM), and more particularly to a system for solving a request collision of a single-port SRAM and method. [Prior Art] Static Random Access Memory (SRAM) is a kind of semiconductor memory. Because it does not need to be periodically refreshed, the speed is faster than that of dynamic random access memory (DRAM). SRAM is often used as a video memory for flat panel displays (such as liquid crystal displays). SRAM can be divided into single-port SRAM and multi-port SRAM. The former has only a single read/write 埠' and the latter has two or more read/write 埠' to allow multiple requesters to access at the same time. Since multi-turn SRAMs occupy a large wafer area and consume more power, 單埠SRAM is more commonly used in portable or handheld electronic devices, such as mobile phones. However, 'high-capacity and low-power SRAMs will cause a sudden drop in speed when they encounter a request collision or multiple requests for 201032230 in the same clock cycle. The first A diagram illustrates a timing diagram of a request collision of a conventional 單埠sram. In the figure, a host (h〇st) sends an external request EXT_REQUEST to sequentially write data (data 1, data 2, data 3, data 4) to the 單埠SRAM. However, within the same period 1 internal request (internai reqUest) INT-RD also requires reading data. In other words, internal requests and external requests have a request conflict for material 1. In order to solve this problem, the sram ru sequencer provides the correction timing as shown in the first b diagram, where the signal RAM CLK is derived from the external request EXT-REQUEST' and the signal RAM-LE is internally requested. Exported by iNT_RD. When data 1 is written to SRAM in cycle 1, the next cycle (ie, cycle 2) allows the internal request to be used exclusively. The external request for data 2 is deferred to the next cycle (i.e., cycle 3), while the remaining data 3 and 4 are also delayed by one cycle. As mentioned above, 'request conflicts can be resolved by delaying the cycle of all requests, however this will cause the speed of the traditional 單埠SRAM to drop sharply (that is, each time a request collision occurs, it will be accompanied by a delay of one cycle) . In view of this, it is urgent to propose a novel 單埠SRAM architecture and method for achieving speed performance. SUMMARY OF THE INVENTION In view of the above, one of the objects of the present invention is to provide a system and method that can improve the speed performance and maintain its high capacity at the same time when the request conflict occurs in the SRAM without delaying its cycle. And low power winter

According to an embodiment of the invention, the 單埠SRAM includes a first SRM portion and a first SRAM portion that are sequentially accessed. The SRM further includes a first temporary storage area and a second temporary storage area for temporarily storing at least a material address, wherein the first temporary storage area corresponds to the first _SRAM part, and the third temporary storage area corresponds to the first SRAM part. The SRAM controller generates control signals for managing the flow of data into and out of the SRAM. The sequencer compiles the money according to the control signal of the controller, and (4) controls the timing of the first/second sram part and the second/second temporary storage area. The first bus bar allows the first sram portion, the first temporary storage area to communicate with the sequencer, and the second bus bar allows the second SRAM portion, the second temporary storage area, and the serializer to communicate with the present embodiment. When a collision occurs, the data is temporarily stored in the first/second temporary storage area corresponding to the first/second SRAM portion of the access being accessed. During the subsequent period 'when one of the first/second SRAM sections is faceted, the temporary data is simultaneously transferred to the other of the first/second SRAM sections. [Embodiment] The block diagram of 201032230 and the second figure shows a system 1 for solving a request conflict of a single-port static random access memory (SRAM) 100 in the embodiment of the present invention. In this embodiment, the system i is suitable for a flat panel display (for example, a liquid crystal display) driver of a portable or handheld electronic device (for example, a mobile phone). However, the system i disclosed in the embodiment is equally applicable to other systems. In an electronic device. • SRAM 100 is usually divided into two parts: a first SRAM part (or SRAM left part) 10A and a second SRAM part (or SRAM right part) 10B. - These logic circuits (not shown in the figure) are arranged in the middle of the two parts (10A, 10B) for better timing. Each portion of 10A/1GB typically contains - or multiple banks of memory. In the present embodiment, the first SRAM portion ι0Α and the second SRAM portion 〇B are sequentially accessed. For example, the first material is written to the first SRAM portion ❹ 10A'. Next, the second data is written to the second sj^M portion (7). Next, the second data is written to the first SRAM portion 1A, and then the fourth data is written to the second SRAM portion ΐ0Ββ. In this embodiment, the first (left) temporary storage area (also known as the shadow temporary) The storage area, shad〇wbank) 12Α corresponds to the S-SRAM partial seam, and the second (right) temporary storage area (also known as the shadow bank) 12B corresponds to the second Sram part; L〇Be where, A temporary storage area 12A can temporarily store at least one data and address, and the second temporary storage area 12B can also temporarily store at least one data and address. 201032230 In the architecture of System 1, SRAM controller 14 is used to manage the flow of data into and out of SRAM 100. For example, the sram controller 14 can communicate with the host of the mobile phone via the data line, the address line, and the (external) request input. Thereby, the 'SRAM controller 14 generates a control signal and transmits it to the sequencer (seqUencer) 16 of the SRAM 100. For example, when the host transmits an external request to write data to the SRAM 100, the SRAM controller φ 14 generates an external request EXT_REQUEST. When the display needs to display the data, an internal request INT_RD is issued and input to the sequencer 16. The signal Dummy_Request_Enable and the signal Active-Window_〇dd will be described later. Next, the sequencer 16 generates sequence signals according to the control number of the SRAM controller 14 for controlling the timing of the first/second SRam portion ❹10A/10B and the first/second temporary storage regions 12A/12B. . /, in the upper signal, the signal RAM-CLK is derived from the external one request

EXT-REQUEST, while the signal RAM_LE ij leads free A 1 Shao request INT-RD. The signal SHADOW_CLK provides the clock to the first/temporary buffer area 12A/12B. – Two SRAM sections (left address line first SRAM section/temporary storage area 10A/12A and minute/temporary storage area 10B/12B by first busbar 201032230 (address-L), left dataline (data-L) )) and the second bus (right address line (address-R), right data line (data_R)) communicate with the sequencer 16, respectively. The first SRAM section 10A and the second SRAM section 10B each have their decoder (not shown in the drawing). The SRAM 100 also includes a first latch UA and a second flash lock 11B that correspond to the first/second SRAM portions 10A/10B, respectively. • When the internal request INT-RD is sent from the host, the latch (iatch) 11A/11B is used to read and store the entire line of display data from the first/second SRAM section 10A/10B. The third A diagram shows a timing chart of the first request collision example of the SRAM 100 of the present embodiment. In the figure, the host transmits an external request EXT_REQEUST to sequentially write the data (data 1, data 2, data 3, data 4) to the corresponding corresponding period (cycle 1, cycle 2, cycle 3, cycle 4) to SRAM 1〇〇. However, in cycle 1, the internal request INT__RD also requires reading data. Therefore, internal requests and external requests have a request conflict for material i. To solve this problem, the sequencer 16 provides a modified timing as shown in Figure 3B, in which the signal RAM_CLK is derived from the external request EXT_REQUEST and the signal raM-LE is derived from the internal request INT-RD. When the data 1 is written to the first SRAM portion 10A in cycle 1 (by the left data line (data-L)), the next cycle (ie, 201032230)

In case of 2), the internal request LE is exclusively used. At the same time, under the control of the temporary sector clock SHADOW-CLK, the data 2 is written into the second temporary storage area 12B. In the next cycle 3, data 3 (by the left data line (data_L)) is directly written to the first SRAM portion 1A, and at the same time 'data 2 is transferred from the second temporary storage area 12B to the second SRAM. Part 10B. The rest of the information (ie, Data 4 and subsequent information) is written in accordance with its original cycle. According to this embodiment, the timing of the third B graph does not require a delay period to resolve the request collision problem, and the timing of the first B graph requires a delay period. Thereby, the speed of the embodiment of the present invention is not affected. The fourth A diagram shows a timing chart of the second request collision example of the real example S RAM 10 0. The timing diagram is similar to the third eight diagram. The difference is that the data 2 is the last data, and there is no data 3 or data 4. Figure 4B shows the timing of the correction proposed to solve the request conflict problem in Figure 4A. After the data 2 is written to the first temporary storage area 12B in the cycle 2, the SRAM controller 14 generates a dummy request Dummy_Request_Enable so that the material 2 can be transferred from the second temporary storage area 12B to the second SRAM portion 10B. In general, the SRAM controller 14 generates a virtual request Dummy-Request-Enable at time t when one of the following conditions is met: when leaving a host request active window, or leaving the memory 11 201032230 When accessing a command (memory access command). In the present specification, the above-mentioned "active window" is determined by the host to notify the update area required by the SRAM 100. The fifth A diagram shows a host request active window 50 of the third request collision example of the SRAM 100 of the present embodiment. The host request active window 50 is determined by the SRAM controller 14. In this example, the last data (data 3) of the active window 50 is an odd sequence. The last data in the first line (information 3) and the first data in the second line (information 4) also correspond to the same SRAM portion (i.e., the first to the SRAM portion l〇A). If the request conflict occurs before the material 3, the data 3 is temporarily stored in the first temporary storage area 12A in the period 3. Since the data 4 also corresponds to the first SRAM portion l〇A, the data 3 and the data 4 cannot be simultaneously written to the first-SRAM portion l〇A at the same time. In order to solve this problem, as shown in the correction timing shown in FIG. 5B, the data 3 is kept in the first temporary storage area 12A until the data is transmitted after two cycles (that is, at the time of the cycle 5). To the first SRAM part 1〇8, and the data 5 is simultaneously written to the second SRAM^1〇BeJ^ odd sequence data 3 access system is controlled by the active (Active)-WindQw-cap (active window odd A sequence) signal, which is generated by the SRAM controller 14. 12 201032230. Fig. 6A shows a host request active window 60 of the fourth request collision example of the SRAM 100 of the present embodiment. In this example, the last data (information 4) of the active window 60 is an even sequence of data. The last data in the first line (information 4) and the first data in the second line (information 5) correspond to different SRAM portions (i.e., the second SRAM portion 10B and the first SRAM portion i0A, respectively). If the request conflict occurs before the data 4, the data 4 is temporarily stored in the second temporary storage area 12B. Since the material 5 corresponds to the first SRAM portion 1A, the data 4 and the data 5 can be simultaneously transferred/written to the second SRA1V at the same time [the portion 10B and the first SRAM portion 10A, as shown in the sixth B-picture). Timing diagram. The access of the even sequence data 4 described above is controlled by a de-asserted Active-Window-Odd (Active Window Odd Sequence) signal, which is generated by the SRAM controller 14. 13 201032230 . [Simple description of the diagram] The first A diagram illustrates the timing diagram of the request collision of the conventional 單埠SRAM. The first B-picture shows a modified timing diagram for resolving the first picture request collision. The block diagram of the second diagram shows a system for resolving the conflict of requests of the SRAM in accordance with an embodiment of the present invention. The third A diagram shows a timing chart of the first request collision example of the SRAM of this embodiment. Figure 2B shows a revised timing diagram for resolving the request conflict problem of Figure A. The fourth A diagram shows a timing chart of the second request collision example of the SRAM of this embodiment. Figure 4B shows a revised timing diagram for resolving the request conflict problem of Figure 4A.第五 FIG. 5A shows the host request active window of the third request conflict example of the SRAM of the embodiment. Figure 5B shows a revised timing diagram for resolving the request conflict problem of Figure 5A. Figure 6A shows the host request active window of the fourth request conflict example of the SRAM of this embodiment. Figure 6B shows a revised timing diagram for resolving the request conflict problem of Figure 6A. 201032230 [Description of main component symbols] 1 System 10A that resolves SRAM request conflicts First SRAM section (SRAM left part) 10B Second SRAM section (SRAM right part) 11A First latch 11B Second latch 12A First ( Left) temporary storage area 12B second (right) temporary storage area 16 sequencer 14 SRAM controller

100 SRAM EXT_REQUEST external request INT_RD internal request

RAM_CLK External request export signal RAM_LE Internal request export signal

Dummy a Request_Enable virtual request

Active-Window_Odd SHADOW-CLK (the first _ active window odd sequence signal / second) temporary storage area clock data_L left data line data_R right data line 15 201032230

addressJL address R left address line right address line

16

Claims (1)

201032230 VII. Patent application scope: 1. A system for solving a request collision of a single-port static random access memory (SRAM), comprising: a first SRAM portion and a second SRAM portion, which are a first temporary storage area and a second temporary storage area for temporarily storing at least one data and an address, wherein the first temporary storage area corresponds to the first sram part, and the second temporary The storage area pairs the second SRAM portion, the SRAM controller 'used to manage the data stream entering and exiting the 單埠sram', and the SRAM controller generates a control signal; the sequence state 'is based on the control signal of the SRAM controller to derive the sequence a signal for controlling a timing of the first/second SRAM portion and the first/second temporary storage area; and a first catching row and a second bus bar, wherein the first bus bar So that the SRAM part, the first temporary storage area can communicate with the sequencer, and the (four) (four) letter; - the part, the second temporary storage area can be temporarily stored in the first / the first The second _ _ points correspond to the first / / second temporary storage area, and 17 20103 2230. During the subsequent period, when one of the first/second SRAM sections is accessed, the temporary data is simultaneously transferred to the other of the first/second SRAM sections. 2. The system for resolving the request conflict of the SRAM as described in claim 1 of the patent application, further comprising at least one latch corresponding to the first/second SRAM portion for the first/first The two SRAM sections read and store the display data of the φ entire line. 3. The system for resolving the request conflict of the SRAM as described in claim 1 of the patent scope, wherein, in the last data, the SRAM controller generates a virtual request, so that the temporary data is transmitted to the corresponding first Or the second SRAM section. ❹ 4. A system for resolving a request conflict of a SRAM as described in claim 1 wherein the sequencer derives an external request signal based on an external request issued by a host for writing data to the first One or second SRAM section. 5. A system for resolving a request conflict of a SRAM as described in claim 4, wherein the host issues an internal request to the sequencer for requesting no data. 18 201032230 6·The system of claim conflict resolution as described in Shen 6 of the Stomach of the Stomach. The above-mentioned SRAM_^-active window, with = to inform the updated data required by the SRAM. 7. The system for resolving the request conflict of the SRAM as described in item 6 of the patent application 'When the last data of the active window mentioned above is the odd sequence data, the temporary data is kept for two cycles before being transmitted. . 8. The system for resolving the request conflict of the single bee as described in item 6 of the patent application. When the last data of the above active window is even sequence data, the temporary data is kept for one cycle time. 9. A method for requesting a single-port static (four) machine access memory (SRAM) request conflict, comprising: sequentially accessing a first SRAM portion of the single SRAM portion SliAJVI portion; ~~ when a request conflict occurs Temporarily storing data in the first and second temporary storage areas corresponding to the first or second SRAM portion being accessed; and during the subsequent period, when one of the first/second SRAM portions is stored At the time of the acquisition, the temporary data is simultaneously transferred to the first/second SRAM portion = the other. 19 201032230 10 - The method for resolving the request conflict of the SRAM as described in claim 9 of the patent application scope, further comprising: when a host issues an internal request to request display of data, reading from the first/second SRAM portion The display data of the entire line is taken, and the display data is stored in at least one latch. φ 11. The method for resolving the request conflict of the SRAM as described in claim 9 of the patent application scope, further comprising: generating, during the last data, a virtual request, so that the temporary data is transmitted to the corresponding first or the first Two SRAM parts. 12. The method for resolving a request conflict of a SRAM as described in claim 9 of the patent scope, further comprising: 产生 generating a control signal to manage a data stream entering and leaving the 單埠SRAM; and using the control signal to derive a sequence signal, To control the timing of the first/second SRAM portion and the first/second temporary storage area. 13. The method for resolving a request conflict of a SRAM as described in claim 12, deriving an external request signal for writing data to the first or second SRAM portion according to an external request sent by a host . 201032230 14. A method for resolving a request conflict of a SRAM as described in claim 13 wherein the host issues an internal request to the SRAM for requesting display of data. 15. A method of resolving a request for resolution of a SRAM as described in claim 9 wherein an SRAM controller determines an active window for notifying the updated data required by the SRAM. 16. If the method for resolving the request conflict of the SRAM described in claim 15 is applied, when the last data of the active window is an odd sequence data, the temporary data is transmitted for two cycles. 17. If the method for resolving the request conflict of the SRAM is as described in claim 15 of the patent application, when the last data of the active window is the even serial resource, the temporary data is kept for one cycle time before being transmitted. . twenty one