TWI409816B - System and method for resolving request collision in a single-port sram - Google Patents

Abstract

A system and method for resolving request collision in a single-port static random access memory (SRAM) are disclosed. A first SRAM part and a second SRAM part of the single-port SRAM are accessed in turn. When request collision occurs, data is temporarily stored in a first or second shadow bank associated with the first or the second SRAM part which is under access. The temporarily stored data is then transferred, at a later time, to an associated one of the first/second SRAM parts while the other one of the first/second SRAM parts is being accessed.

Description

System and method for solving request conflict of static random access memory

The present invention relates to static random access memory (SRAM), and more particularly to a system and method for addressing a request collision of a single-port SRAM.

Static Random Access Memory (SRAM) is a type of semiconductor memory that is faster than dynamic random access memory (DRAM) because it does not require periodic refreshes. In view of this, SRAM is often used as a video memory for a flat panel display (such as a liquid crystal display) driver. SRAM can be classified into single-port SRAM and multi-port SRAM. The former has only a single read/write 埠, while the latter has two or more read/write 埠, allowing multiple requesters to access at the same time. Since multi-turn SRAMs occupy a large wafer area and consume more power, 單埠SRAM is more commonly used in portable or handheld electronic devices, such as mobile phones.

However, a high-capacity, low-power SRAM can cause a sudden drop in speed when it encounters a request collision or multiple requests in the same clock cycle. The first A diagram illustrates a timing diagram of a request collision of a conventional 單埠SRAM. In the figure, a host sends an external request EXT-REQUEST to sequentially write data (data 1, data 2, data 3, data 4) to the 單埠SRAM. However, in the same cycle 1, the internal request INT_RD also requires reading data. In other words, internal requests and external requests have a request conflict for material 1. To solve this problem, the SRAM sequencer provides the modified timing as shown in Figure B, where the signal RAM_CLK is derived from the external request EXT_REQUEST and the signal RAM_LE is derived from the internal request INT_RD. When data 1 is written to SRAM in cycle 1, the next cycle (ie, cycle 2) allows the internal request to be used exclusively. The external request for data 2 is deferred to the next cycle (ie, cycle 3), while the remaining data 3 and 4 are also delayed by one cycle.

As mentioned above, the request collision can be resolved by delaying the cycle of all requests, however this will cause the speed of the traditional 單埠SRAM to drop sharply (that is, each time a request collision occurs, it will be accompanied by a delay of one cycle) . In view of this, it is urgent to propose a novel 單埠SRAM architecture and method for improving speed performance.

In view of the above, one of the objects of the present invention is to provide a system and method that, when a request conflict occurs in a SRAM, does not need to delay its cycle, thereby improving speed performance and maintaining the advantages of high capacity and low power at the same time. .

According to an embodiment of the invention, the 單埠SRAM includes a first SRAM portion and a second SRAM portion that are sequentially accessed. The SRAM further includes a first temporary storage area and a second temporary storage area for temporarily storing at least one data and an address, wherein the first temporary storage area corresponds to the first SRAM part, and the second temporary storage area corresponds to the first temporary storage area The second SRAM part. The SRAM controller generates control signals for managing the flow of data into and out of the SRAM. The sequencer derives a sequence signal according to a control signal of the SRAM controller for controlling timing of the first/second SRAM portion and the first/second temporary storage area. The first bus bar allows the first SRAM portion, the first temporary storage area to communicate with the sequencer, and the second bus line allows the second SRAM portion and the second temporary storage area to communicate with the sequencer. According to this embodiment, when a request collision occurs, the data is temporarily stored in the first/second temporary storage area corresponding to the first/second SRAM portion being accessed. During the subsequent period, when one of the first/second SRAM sections is accessed, the temporary data is simultaneously transferred to the other of the first/second SRAM sections.

The block diagram of the second diagram shows a system 1 for addressing a request collision of a single-port static random access memory (SRAM) 100 in accordance with an embodiment of the present invention. In this embodiment, the system 1 is suitable for a flat panel display (for example, a liquid crystal display) driver of a portable or handheld electronic device (for example, a mobile phone). However, the system 1 disclosed in the embodiment is equally applicable to other systems. In an electronic device.

The SRAM 100 is generally divided into two parts: a first SRAM portion (or SRAM left portion) 10A and a second SRAM portion (or SRAM right portion) 10B. Some logic circuits (not shown) are arranged in the middle of the two parts (10A, 10B) for better timing. Each portion of 10A/10B typically contains one or more banks of memory. In the present embodiment, the first SRAM portion 10A and the second SRAM portion 10B are sequentially accessed. For example, the first material is written to the first SRAM portion 10A, and then the second material is written to the second SRAM portion 10B. Next, the third data is again written to the first SRAM portion 10A, and the fourth data is written to the second SRAM portion 10B. In this embodiment, the first (left) temporary storage area (also referred to as a shadow bank) 12A corresponds to the first SRAM part 10A, and the second (right) temporary storage area (also known as the shadow temporary stage) The shadow bank 12B corresponds to the second SRAM portion 10B. The first temporary storage area 12A can temporarily store at least one data and address, and the second temporary storage area 12B can temporarily store at least one data and address.

In the architecture of system 1, SRAM controller 14 is used to manage the flow of data into and out of SRAM 100. For example, the SRAM controller 14 can communicate with the host of the mobile phone by means of a data line, an address line, and an (external) request input. Thereby, the SRAM controller 14 generates a control signal and transmits it to the sequencer 16 of the SRAM 100. For example, when the host transmits an external request to write data to the SRAM 100, the SRAM controller 14 generates an external request EXT_RE. UEST. When the display needs to display the data, an internal request INT_RD is issued and input to the sequencer 16. The signal Dummy_Request_Enable and the signal Active_Window_Odd will be described later.

Next, the sequencer 16 generates sequence signals for controlling the timing of the first/second SRAM sections 10A/10B and the first/second temporary storage areas 12A/12B according to the control signals of the SRAM controller 14. Among these signals, the signal RAM_CLK is derived from the external request EXT_RE UEST, while the signal RAM_LE is derived from the internal request INT_RD. The signal SHADOW_CLK provides a clock to the first/second buffer area 12A/12B.

The first SRAM portion/temporary storage area 10A/12A and the second SRAM portion/temporary storage area 10B/12B are provided by the first bus bar (left address line (address_L), left data line (data_L)) and the second bus bar (The right address line (address_R) and the right data line (data_R)) communicate with the sequencer 16, respectively. The first SRAM portion 10A and the second SRAM portion 10B each have their decoder (not shown in the drawings).

The SRAM 100 also includes a first latch 11A and a second latch 11B that correspond to the first/second SRAM portions 10A/10B, respectively. When the internal request INT_RD is issued from the host, the latch 11A/11B is used to read and store the entire line of display material from the first/second SRAM portion 10A/10B.

The third A diagram shows a timing chart of the first request collision example of the SRAM 100 of the present embodiment. In the figure, the host transmits an external request EXT_REQEUST to sequentially write data (data 1, data 2, data 3, data 4) to the SRAM in the corresponding cycle (cycle 1, cycle 2, cycle 3, cycle 4). 100. However, in cycle 1, the internal request INT_RD also requires reading data. Therefore, internal requests and external requests have a request conflict for material 1. To solve this problem, the sequencer 16 provides a modified timing as shown in FIG. B, in which the signal RAM_CLK is derived from the external request EXT_REQUEST and the signal RAM_LE is derived from the internal request INT_RD. When the data 1 is written to the first SRAM portion 10A in cycle 1 (by the left data line (data_L)), the next cycle (ie, cycle 2) allows the internal request RAM_LE to be exclusively used. At the same time, under the control of the temporary sector clock SHADOW_CLK, the data 2 is written into the second temporary storage area 12B. In the next cycle 3, the data 3 (by the left data line (data_L)) is directly written to the first SRAM portion 10A, and at the same time, the data 2 is transferred from the second temporary storage area 12B to the second SRAM portion 10B. The rest of the information (ie, data 4 and subsequent information) is written in accordance with its original cycle. According to the embodiment, the timing of the third B graph does not require a delay period to solve the request conflict problem, and the timing of the first B graph requires a delay period. Thereby, the speed of the embodiment of the present invention is not affected.

The fourth A diagram shows a timing chart of the second request collision example of the SRAM 100 of the present embodiment. The timing diagram is similar to the third A diagram. The difference is that the data 2 is the last data, and there is no data 3 or data 4 thereafter. Figure 4B shows the timing of the correction proposed to solve the request conflict problem of Figure 4A. After the data 2 is written to the second temporary storage area 12B in the cycle 2, the SRAM controller 14 generates a dummy request Dummy_Request_Enable so that the material 2 can be transferred from the second temporary storage area 12B to the second SRAM portion 10B. In general, the SRAM controller 14 generates a virtual request Dummy_Request_Enable at time t when one of the following conditions is met: when leaving a host request active window, or leaving a memory access command (memory access command) )Time. In the present specification, the above-mentioned "active window" is determined by the host to notify the update area required by the SRAM 100.

The fifth A diagram shows the host request active window 50 of the third request collision example of the SRAM 100 of the present embodiment. The host request active window 50 is determined by the SRAM controller 14. In this example, the last data (data 3) of the active window 50 is an odd sequence of data. The last data (data 3) of the first line and the first data (data 4) of the second line also correspond to the same SRAM portion (i.e., the first SRAM portion 10A). If the request conflict occurs before the material 3, the data 3 is temporarily stored in the first temporary storage area 12A in the period 3. Since the material 4 also corresponds to the first SRAM portion 10A, the material 3 and the material 4 cannot be simultaneously written to the first SRAM portion 10A at the same time. In order to solve this problem, as shown in the correction timing shown in FIG. 5B, the data 3 is kept in the first temporary storage area 12A until after two cycles (that is, at the time of the cycle 5), the data 3 is transmitted. To the first SRAM portion 10A, the material 5 is simultaneously written to the second SRAM portion 10B. The access of the odd sequence data 3 described above is controlled by an asserted Active_Window_Odd (active window odd sequence) signal, which is generated by the SRAM controller 14.

The sixth A diagram shows a host request active window 60 of the fourth request conflict example of the SRAM 100 of the present embodiment. In this example, the last data (information 4) of the active window 60 is even sequence data. The last data (data 4) of the first line and the first data (data 5) of the second line correspond to different SRAM parts (i.e., the second SRAM part 10B, the first SRAM part 10A, respectively). If the request conflict occurs before the data 4, the data 4 is temporarily stored in the second temporary storage area 12B. Since the material 5 corresponds to the first SRAM portion 10A, the data 4 and the data 5 can be simultaneously transferred/written to the second SRAM portion 10B and the first SRAM portion 10A at the same time, as shown in the timing chart of FIG. . The access of the even sequence data 4 described above is controlled by a de-asserted Active_Window_Odd (active window odd sequence) signal, which is generated by the SRAM controller 14.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

1. . . System for resolving 單埠SRAM request conflicts

10A. . . First SRAM section (left of SRAM)

10B. . . Second SRAM section (SRAM right)

11A. . . First latch

11B. . . Second latch

12A. . . First (left) temporary storage area

12B. . . Second (right) temporary storage area

16. . . Sequencer

14. . . SRAM controller

100. . . SRAM

EXT_REQUEST. . . External request

INT_RD. . . Internal request

RAM_CLK. . . External request export signal

RAM_LE. . . Internal request export signal

Dummy_Request_Enable. . . Virtual request

Active_Window_Odd. . . Active window odd sequence signal

SHADOW_CLK. . . (first/second) temporary storage area clock

data_L. . . Left data line

data_R. . . Right data line

address_L. . . Left address line

address_R. . . Right address line

The first A diagram illustrates a timing diagram of a request collision of a conventional 單埠SRAM.

The first B diagram shows a modified timing diagram for resolving the first graph request conflict.

The block diagram of the second figure shows a system for solving the request conflict of the SRAM in the embodiment of the present invention.

The third A diagram shows a timing chart of the first request collision example of the SRAM of the present embodiment.

The third B diagram shows the modified timing diagram proposed to solve the request conflict problem of the third A diagram.

The fourth A diagram shows a timing chart of the second request collision example of the SRAM of the present embodiment.

Figure 4B shows a modified timing diagram for resolving the request conflict problem of Figure 4A.

The fifth A diagram shows the host request active window of the third request conflict example of the SRAM of the embodiment.

Figure 5B shows a modified timing diagram for resolving the request conflict problem of Figure 5A.

The sixth A diagram shows the host request active window of the fourth request conflict example of the SRAM of the embodiment.

Figure 6B shows a modified timing diagram for resolving the request conflict problem of Figure 6A.

1. . . System for resolving 單埠SRAM request conflicts

10A. . . First SRAM section (left of SRAM)

10B. . . Second SRAM section (SRAM right)

11A. . . First latch

11B. . . Second latch

12A. . . First (left) temporary storage area

12B. . . Second (right) temporary storage area

16. . . Sequencer

14. . . SRAM controller

100. . . SRAM

EXT_REQUEST. . . External request

INT_RD. . . Internal request

RAM_CLK. . . External request export signal

RAM_LE. . . Internal request export signal

Dummy_Request_Enable. . . Virtual request

Active_Window_Odd. . . Active window odd sequence signal

SHADOW_CLK. . . (first/second) temporary storage area clock

data_L. . . Left data line

data_R. . . Right data line

addressL. . . Left address line

addressR. . . Right address line

Claims (7)

A system for solving a request collision of a single-port static random access memory (SRAM), comprising: a first SRAM portion and a second SRAM portion, which are sequentially accessed; a first temporary storage And a second temporary storage area for temporarily storing at least one data and an address, wherein the first temporary storage area corresponds to the first SRAM part, and the second temporary storage area corresponds to the second SRAM part An SRAM controller for managing data flow into and out of the SRAM, the SRAM controller generates a control signal; a sequencer that derives a sequence signal according to a control signal of the SRAM controller to control the first a timing of the second SRAM portion and the first/second temporary storage area; and a first bus bar and a second bus bar, wherein the first bus bar allows the first SRAM portion and the first temporary storage area Communicating with the sequencer, wherein the second bus line allows the second SRAM portion and the second temporary storage area to communicate with the sequencer; wherein, when a request conflict occurs, the data is temporarily stored in the access a first/second temporary storage area corresponding to the first/second SRAM portion, and During the subsequent period, when one of the first/second SRAM portions is accessed, the temporary data is simultaneously transferred to the other of the first/second SRAM portions; wherein the SRAM controller determines an active window, The update area required to notify the SRAM; the SRAM controller generates a virtual request signal when a request conflict occurs and the temporary data exits the active window. The system for resolving the request conflict of the SRAM as described in claim 1, further comprising at least one latch corresponding to the first/second SRAM portion for using the first/second SRAM Partially read and store the display data of the entire line. The system for resolving the request conflict of the SRAM as described in claim 1 of the patent application, wherein in the last data, the SRAM controller generates a virtual request, so that the temporary data is transmitted to the corresponding first or the first Two SRAM parts. A system for resolving a request conflict of a SRAM as described in claim 1, wherein the sequencer derives an external request signal according to an external request sent by a host for writing data to the first or the first Two SRAM parts. A system for resolving a request conflict of a SRAM as described in claim 4, wherein the host issues an internal request to the sequencer for requesting display of the material. For the system for resolving the request conflict of the SRAM as described in the first paragraph of the patent application, when the last data of the active window is odd sequence data, the temporary data is kept for two cycles before being transmitted. For the system for resolving the request conflict of the SRAM as described in the first paragraph of the patent application, when the last data of the active window is the even sequence data, the temporary data is kept for one cycle time before being transmitted.