JPH11353871A - Semiconductor apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the cycle time of reading, writing of a dynamic memory cell by selecting a word line, reading out a signal of a corresponding memory cell to a plurality of corresponding bit lines, amplifying the signal on an input/ output line and precharging a plurality of the bit lines. SOLUTION: At a write operation, as only a word line of a selected memory cell is asserted, a bit line is driven in accordance with write data immediately after the word line is asserted. A destructively read data from a dynamic memory is stored in an entry of a cache memory 110. Since a Valid bit is set when the data is sent (replaced) out of the cache memory, the data is written back to the dynamic memory. The data merely reciprocates between the dynamic memory 100 and cache memory 110 via a bus controller 116 and therefore the original data is not lost.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dynamic memory and a semiconductor device using the same, and more particularly to a dynamic memory suitable for high-speed and low-power applications and a semiconductor device using the same.

[0002]

2. Description of the Related Art An operation waveform of a conventional dynamic memory (hereinafter referred to as DRAM) operates as shown in FIG. 2 as described in, for example, Kiyo Ito, "Super LSI Memory", Baifukan, p86. . That is, in the read operation, after asserting the word line and reading a signal from the memory cell to the bit line, the sense amplifier is activated for a predetermined time φA to amplify the signal on the bit line. As a result, the data is determined and output after a row address access time (tRAC) from the start of the access. In addition, tR for rewriting to the memory cell
It takes time to AS, and then a precharge time (tRP) is required as a precharge time for bit lines and the like.

On the other hand, a write operation is basically the same as a read operation, but is performed by driving data of a selected memory cell on a bit line according to write data after driving a sense amplifier.

[0004]

In the above-mentioned conventional dynamic memory, (1) at the time of a read operation, the amplitude of a bit line must be increased for rewriting to a memory cell. As a result, the cycle time (tRC) represented by tRAS + tRP becomes longer.

(2) At the time of a write operation, the non-selected memory cells need to perform the same operation as the read operation, so that the write cycle time tRC becomes longer as in the case of the read operation.

(3) If the dynamic memory is completely pipelined for (1) and (2), the pipeline pitch becomes long.

The above problem arises.

[0008]

The main means used in the present invention to solve the above problems are as follows.

(1) A plurality of dynamic memory cells provided at intersections of a plurality of word lines and a plurality of bit lines, a plurality of sense amplifiers provided corresponding to each of the plurality of bit lines, In a semiconductor device including a dynamic memory having a plurality of input / output lines provided corresponding to each of a plurality of sense amplifiers, the dynamic memory selects a word line to correspond to a signal of the corresponding dynamic memory cell. After reading to the plurality of bit lines, the plurality of sense amplifiers input / output the signals read out to the bit lines without shifting to a period for rewriting the read signals to the dynamic memory cells. After amplification on the line, the plurality of bit lines are precharged. (2) The dynamic memory further comprises a corresponding bit line The write amplifier outputs a write signal to the corresponding bit line immediately or immediately before or at the same time as selecting the corresponding word line during a write operation to the dynamic memory cell, and Write a signal to the type memory cell.

(3) The semiconductor device according to (1) or (2) further comprises at least one cache constituted by static memory cells, and in the operation of reading data from the dynamic memory, Reading the data from the dynamic memory, writing the data to at least one of the caches, and writing the data back to the dynamic memory when the data is erased from all of the caches.

(4) In the semiconductor device including the dynamic memory according to (1) to (3),
An address latch circuit for receiving a row address for selecting a word line to be accessed among the plurality of word lines, wherein the address latch circuit latches the row address at each transition point of a clock signal having a predetermined cycle .

(5) The pipelined dynamic memory of (4) further includes a write delay circuit to which a first write address and a first write data are inputted at the time of the first write access, The write operation to the dynamic memory cell corresponding to the first write access is performed at the time of the second write access following the first write access with respect to the first write address and the first write data stored in the write delay circuit. Do it.

(6) The dynamic memory according to (5) further includes a forward circuit having an address comparator. In the read access, the forward circuit compares an input read address with the first write address and the address. If there is a read access at the same address as the first write address between the first write access and the second write access, the first write data is output as read data corresponding to the read access. I do.

[0014]

FIG. 1 shows a typical embodiment of the present invention.

The memory device of the present invention is a dynamic memory.
100 and cache memory 110. 111 in the cache memory 110 indicates a valid bit, and 112 and 113 indicate the address and data of each entry of the cache memory. 114 is the bus connected to the cache, 115 is DRAM
, 116 indicate those bus controllers.

The dynamic memory 100 operates as shown in FIG. That is, during the read operation, the sense amplifier is activated at φA after asserting the word line. As a result, data is output tRAC after the assertion of the word line. At this time, unlike a conventional dynamic memory, a rewrite operation of amplifying a read signal to a bit line and writing the amplified signal to a memory cell is not performed.

Therefore, there is no need to amplify data on the bit line as in the conventional case, and the power required for charging and discharging the bit line can be reduced. Also, no time equivalent to tRAS is required. Although tRP is required as a precharge time for a bit line or the like, precharging can be performed in a short time because the bit line remains at a small amplitude.

On the other hand, in the write operation, only the word line of the selected memory cell is asserted, and the bit line is driven according to the write data as soon as the word line is asserted.

Since rewriting to the memory cell is not performed at the time of reading, destructive reading is performed. The cache memory 110 is used to protect the data. Data read from the dynamic memory 100 is sent to the cache memory. The cache memory stores the read data in an entry. At this time, the valid bit of the entry is set. Further, at the time of the replacement operation of the cache memory, for the entry in which the Valid bit is set, new data is stored in the entry, and at the same time, the stored data is written back to the dynamic memory. (Control is performed like a write-back method using the write allocate write method.) With this control, the data read by the destructive read from the dynamic memory is stored in an entry in the cache memory, and the data is read from the cache memory. At the time of eviction (replacement), since the Valid bit is set, writing back to the dynamic memory is performed. The original data is never lost simply by reciprocating between the dynamic memory 100 and the cache memory 110.

The flow of data between the dynamic memory 100 and the cache memory 110 depends on the bus controller 1
The bus controller in FIG. 1 is not particularly required if the dynamic memory 100 and the cache are configured to be directly connectable by one bus.

Further, as the sense amplifier of the dynamic memory 100 of the present invention, a sense amplifier of a direct sense system as described in, for example, Kiyoo Ito, "Super LSI Memory", Baifukan, p. 165 is suitable. In this direct sensing method, a memory cell signal can be directly taken out to a common data output line without waiting for a sense amplifier to amplify data to a bit line, and high-speed operation is possible. When this direct sensing method is used in a conventional dynamic memory, an amplifier for rewriting to a memory cell is required in parallel with the sense amplifier, but this is not required in the dynamic memory of the present invention.

FIG. 4 shows an embodiment in which this direct sense type sense amplifier is applied to the dynamic memory of the present invention. MC is a dynamic memory cell, 301 is an equalizer circuit, 302 is a direct sense type sense amplifier circuit, 3
03 is a write amplifier circuit, 304 is a word driver circuit, 305
a to 305d are word lines, BL and / BL are bit lines, EQ is an equalizer circuit start signal, SA is a sense amplifier circuit start signal, and WA is a write amplifier circuit start signal. RO and / RO indicate output lines from the sense amplifier circuit, and WI and / WI indicate input lines to the write amplifier circuit. Two dual rail signals form an I / O line (input / output line). I have. The feature is that there is no rewrite amplifier circuit. Here, an example is shown in which the output line and the input line are separated, but they may be common. That is, the input / output lines may be two pairs separated for writing and reading, or may be shared by one pair.

As described above, the dynamic memory 100 of the present invention can have a significantly shorter tRC than a conventional dynamic memory. By using this feature, when the dynamic memory 100 is pipelined as shown in FIG. 5, the pipeline pitch can be reduced. In FIG. 5, reference numeral 200 denotes a configuration example when the dynamic memory of the present invention is made into a pipeline. 201 is an address latch, 202 is an address decoder, 20
3 is an address driver, 204 is a sense amplifier and a write amplifier, 205 is an input data DI latch, 206 is a write buffer,
207 is an I / O line amplifier that amplifies the signals of the I / O lines 210 and 211, 208
And 209 are bit line pairs BL and / BL, 210 and 211 are I / O line pairs, 212 is a word line, and 213 is a memory cell. Clock CLK is 201
, 205 and 207, and have a two-stage pipeline structure.

At the time of reading, after the address latched by 201 is decoded, one of the word lines 212 is selected and asserted. The information of the memory cell output to the bit lines BL and / BL is amplified at 204. The amplified data of the memory cell is latched by the next clock 207 and output as output data DO.

At the time of writing, after the address latched by 201 is decoded, one of the word lines 212 is selected and asserted. At the same time, the write data is latched by 205, and the bit lines BL and / BL are driven by 206. With this operation, writing to the memory cell is performed.

The above two operations include bit lines BL, / BL and
Although the precharge operation of the I / O line and the like is omitted, the method is not particularly limited. It may be performed between the rising of the clock CLK and the assertion of the word line.

The conventional dynamic memory has a drawback that the pipeline pitch becomes long even when pipelined due to long tRC. Conventionally, a method such as multi-bank interleaving has been used to hide this defect in appearance, but there is a problem that the pipeline is disturbed when access to the same bank is continued, and the bank control becomes complicated. There was a disadvantage.

FIG. 6 shows an embodiment in which the write latency and the read latency of the dynamic memory of FIG. 5 are the same. Latency is the time from a read access request to the output of read data or the time from a write access request to the end of a write operation.

221 is a read address latch, 222, 223, 2
24 is a write address latch, and 225 is a selector. A broken line with an arrow indicates a clock line, and the write data control unit
Control is performed by 226 as described below.

As compared with FIG. 5, the address latch 201 has a read address latch 221 and write address latches 222 to 22.
4 and selector 225 have been replaced. The input clock of the address latch and the input clock of 205 are controlled by the write data control unit 226 as follows.

When a write address is input, the write address is delayed by the write address latch. Two clocks later, the write data is latched by 205 and is ready for writing. At the timing when there is a write access request next to this write access, the data is written to the memory cell with a write latency of 0 based on the address latched in 224 and the data latched in 205. Therefore, the write operation is performed at the time of the next write access after the write access. (Delayed write) In the method of FIG. 5, the write latency is 0 and the read latency is 3. However, by controlling the configuration as shown in FIG. 6, both the write latency and the read latency are 3
Can be.

By controlling the write and read latencies to match each other, access requests and refresh requests from a plurality of CPUs and bus masters can be input to the dynamic memory without disturbing the pipeline.
In addition, a device using the dynamic memory of the present invention can completely understand not only read latency but also write latency. Therefore, it is easy to input write data to the dynamic memory with the same latency as the read latency, thereby increasing the pipeline filling rate when read and write are mixed.

In the method shown in FIG. 6, the information is actually written to the memory after the write access at least two clocks later. Therefore, care must be taken when a read access request is issued to the same address during that time.

(1) If there is a read access to the same address one clock after the write access, the write data has not yet been input to the dynamic memory.
The write data may be input at the next clock, and the data may be forwarded at the next clock.

(2) If there is a read access to the same address two clocks after the write access, the write data latched at that clock may be forwarded as it is.

FIG. 7 shows the addition of the above forward circuit to FIG. 231 is an address comparator, 232 is a selector, 2
33 is a latch. The address comparator 231 detects that a request to read unwritten data to a memory cell has been made, and forwards the corresponding read data using the selector 232.

Although the cache memory 110 of FIG. 1 may be integrated on the same semiconductor chip as the dynamic memory 100,
Another chip may be used.

When the dynamic memory 100 is used as the main memory of the CPU, the cache memory 110 is stored in the first memory of the CPU.
Optimally implemented as a secondary cache. Alternatively, the memory system may be realized as a memory system including a primary cache and a secondary cache of the CPU. In this case, the data read from the dynamic memory 100 is written to the primary cache, and when the data is erased from the primary cache, the data is written to the secondary cache, and the data is read from the secondary cache. Is replaced,
It is optimal to control the data to be written back to the dynamic memory 100. By using the cache memory 110 as the primary cache or the secondary cache of the CPU as described above, the area efficiency can be increased.

The dynamic memory of the present invention basically needs to assert only the word line connected to the selected memory cell. Therefore, when the number of selected memory cells is small, it is necessary to divide a word line into many sub-word lines and decode them. This leads to an increase in area. In order to increase the number of selected memory cells selected at a time, there are the following methods.

(1) If the cache memory 110 is integrated on the same semiconductor chip as the dynamic memory 100, the line size of the cache memory can be increased because there is no bottleneck in the number of pins. You can increase the number. In an extreme case, the memory cells of the cache memory may be laid out in parallel with the sense amplifier.

(2) When the cache memory 110 is implemented by using a primary cache or a secondary cache of a CPU and is formed on a separate chip from the dynamic memory 100,
The data transfer size only between the cache memory 110 and the dynamic memory 100 is increased. For example, cache memory
When 110 is realized by the secondary cache of the CPU, the line size of the secondary cache may be increased.

The data stored in the dynamic memory of the present invention exists in the cache memory 110 or the dynamic memory 100. Therefore, when a plurality of bus masters are provided for these memory systems, a so-called coherency problem occurs. For example, this problem can be solved as follows.

(1) If the cache memory 110 and the dynamic memory 100 are integrated on the same semiconductor chip and the access to the chip is performed only through the cache memory 110, the direct access to the dynamic memory 100 is There is no coherency problem because it is not possible.

(2) When the cache memory 110 and the dynamic memory 100 are formed on different chips, the cache memory 110 may be realized by using the primary cache or the secondary cache of the CPU. Although the dynamic memory 100 can be directly accessed by a plurality of CPUs, a coherency compensation method using a MESI protocol or the like built in the CPU, the primary cache, or the secondary cache controller can be used as it is. When data is read from the dynamic memory 100, the Va of the data entry is
The lid bit is set, so MESI protocol
Monitors the corresponding entry access of PU.

FIG. 8 shows an example of the use of the fully pipelined dynamic memory of the present invention when the cache memory 110 cannot be used. As described above, the dynamic memory of the present invention is a destructive read. Therefore, the read data does not exist in the dynamic memory.
In FIG. 8, the dynamic memory is formed into a pipeline, and a write operation of data read at the same address is performed immediately after reading. (A) is a waveform when the embodiment of FIG. 5 is used. (B) is a waveform when the embodiment of FIG. 6 or 7 is used. As described above, the use of the method shown in FIG. 6 or FIG. 7 can completely suppress the access overhead to one clock. When there are a plurality of bus masters, the write access following the continuous read / write operation for rewriting must be performed with the highest priority in order to compensate for coherency.

The method of FIG. 8 can be used not only when the cache memory 110 cannot be used but also when the valid bit control cannot be used for the cache memory 110. further,
It can also be used when the cache memory 110 is an instruction cache.

The number of cache memories 110 is not limited. Alternatively, the cache memory 110 may have a plurality of memory hierarchies. There may be two such as an instruction cache and a data cache. In the case of a data cache, an access method using the Valid bit described in FIG. 1 is used, and in the case of an instruction cache, a write access is performed after a read access using the method described in FIG. Alternatively, the dynamic memory 100 may be provided with two modes, and may have a mode for accessing with the dynamic memory format of the present invention and a mode for accessing with the conventional dynamic memory format. If a mode with good access efficiency is selected according to the access content, the dynamic memory 100 can be used more efficiently.

In the above embodiment, an example is shown using the Valid bit, but the presence or absence of the Valid bit is not particularly limited.
Further, the line size, the number of ways, the capacity, and the like of the cache memory 110 are not particularly limited. Dynamic memory 100
The data destructively read from the cache memory 110
, And the data expelled from the cache memory 110 may be stored in the dynamic memory 100. If you have more than one cache memory,
What is necessary is just to control so that data always exists in those cache memory and dynamic memory. In short, the dynamic memory is destructively read, and if the read data is controlled to be stored in a memory other than the read dynamic memory (the cache memory in the present invention) of the entire system using the dynamic memory, the system configuration is particularly limited. do not do.

The number of dynamic memories 100 is not limited. The method of the present invention may be applied to a plurality of dynamic memory chips, or the method of the present invention may be applied to some dynamic memories of the plurality of dynamic memory chips.

Further, the structure of the memory cell of the cache memory 110 is not particularly limited. It may be a dynamic type that stores data by storing charges in a capacitance, an SRAM memory cell using a poly resistor or a TFT, or 6
A complete CMOS SRAM memory cell using one MOS transistor may be used.

The operation and effect of the above embodiment are as follows.

(1) By making the dynamic memory a destructive read, there is no need to amplify data on the bit line,
No time equivalent to tRAS is required. As for the precharge time, since the bit line remains at a small amplitude, the precharge can be performed in a short time.

(2) According to (1), the cycle time tRC can be significantly reduced as compared with the conventional dynamic memory. This feature allows dynamic memory to be pipelined SR
When pipelined like AM, the pipeline pitch can be reduced.

(3) When a direct sense type sense amplifier is used as the sense amplifier of the dynamic memory, a high-speed amplification operation is possible. When this direct sensing method is used in a conventional dynamic memory, an amplifier for rewriting to a memory cell is required in parallel with the sense amplifier. However, the dynamic memory according to the present invention does not require an amplifier, so that the chip area can be reduced.

(4) In the dynamic memory pipelined by the above configuration, the read latency and the write latency can be made equal. This makes it possible to increase the filling rate of the pipeline when the read and the write are mixed.

[0056]

Since the cycle time for reading and writing dynamic memory cells can be reduced, a DRAM capable of high-speed operation can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms of a conventional dynamic memory.

FIG. 3 is a diagram showing an example of an operation waveform of the dynamic memory of the present invention.

FIG. 4 is a diagram showing an embodiment of a dynamic memory of the present invention using a sense amplifier circuit of a direct sense system.

FIG. 5 is a diagram showing an embodiment of a pipelined dynamic memory according to the present invention and operation waveforms thereof.

FIG. 6 is a diagram showing an embodiment of a dynamic memory in which the write latency and the read latency are the same pipelined according to the present invention, and operation waveforms thereof.

FIG. 7 is a diagram showing an embodiment in which a forward circuit is further added to the embodiment of FIG. 5;

FIG. 8 is a diagram showing an example of using the dynamic memory of the present invention when a cache memory cannot be used.

[Explanation of symbols]

100 …… dynamic memory, 110 …… cache memory, 200 …… complete pipeline dynamic memory,
220 …… No-wait access complete pipeline dynamic memory, 230 …… No-wait access complete pipeline dynamic memory with forward circuit,
300 …… Dynamic memory using direct sense type sense amplifier, Ra1, Ra2 …… Read address, Wa
1, Wa2: Write address, Rd1, Rd2: Read data, Wd1, Wd2: Write data.

Claims (15)

[Claims] A plurality of dynamic memory cells provided at intersections of a plurality of word lines and a plurality of bit lines; a plurality of sense amplifiers provided corresponding to each of the plurality of bit lines; In a semiconductor device including a dynamic memory having a plurality of input / output lines provided corresponding to each of the sense amplifiers, the dynamic memory selects the word line and responds to the signal of the corresponding dynamic memory cell. After reading out to the plurality of bit lines, the plurality of sense amplifiers read the signals read out to the bit lines on the input / output lines without shifting to a period for rewriting the readout signals to the dynamic memory cells. A first read mode in which the plurality of bit lines are precharged after amplification in the semiconductor device. Place. 2. The dynamic memory according to claim 1, wherein the dynamic memory further selects the word line and reads a signal of the corresponding dynamic memory cell to a corresponding bit line, and the sense amplifier reads the signal to the bit line. A semiconductor device having a second read mode in which a signal is amplified on the bit line and the input / output line and rewritten to the dynamic memory cell read from the dynamic memory cell. 3. The dynamic memory according to claim 1, further comprising: a write amplifier in a corresponding bit line, wherein a write operation is performed on the dynamic memory cell.
Immediately before, immediately before or at the same time as selecting the corresponding word line, the write amplifier outputs a write signal to the corresponding bit line, and has a first write mode for writing a signal to the dynamic memory cell. Semiconductor device. 4. The dynamic memory according to claim 3, wherein the dynamic memory further selects the word line and reads a signal of the corresponding dynamic memory cell to a corresponding bit line, and the sense amplifier reads a signal to the bit line. After amplifying a signal to the bit line and rewriting information read from the dynamic memory cell to the dynamic memory cell, the write amplifier outputs a write signal to the corresponding bit line, and A semiconductor device having a second write mode for writing a signal to a memory cell. 5. The semiconductor device according to claim 1, further comprising at least one cache configured by a static memory cell, wherein in the operation of reading data from the dynamic memory, Reading data from the dynamic memory in a read mode, the data is written to at least one of the caches, and when the data is erased from the cache, the data is transferred to the dynamic memory by the first or second A semiconductor device which is written back in a write mode. 6. A plurality of dynamic memory cells provided at intersections of a plurality of word lines and a plurality of bit lines; a plurality of sense amplifiers provided corresponding to each of the plurality of bit lines; Address latch receiving a row address for selecting a word line to be accessed among a plurality of word lines in a semiconductor device including a dynamic memory having a plurality of input / output lines provided corresponding to each of the sense amplifiers A semiconductor device, comprising a circuit, wherein the address latch circuit latches the row address at each transition point of a clock signal having a predetermined period. 7. The dynamic memory cell according to claim 6, wherein the dynamic memory selects the word line and reads a signal of the corresponding dynamic memory cell to a corresponding bit line, and then outputs the read signal to the dynamic memory cell. A first read mode in which the plurality of bit lines are precharged after the sense amplifier amplifies a signal read out to the bit line on the input / output line without shifting to a rewrite period to A semiconductor device characterized by the above-mentioned. 8. The dynamic memory according to claim 7, further comprising a write amplifier for a corresponding bit line, and at the time of a write operation to said dynamic memory cell, immediately after or immediately before selecting a corresponding word line. At the same time, the semiconductor device has a first write mode in which the write amplifier outputs a write signal to the corresponding bit line and writes a signal to the dynamic memory cell. 9. The dynamic memory according to claim 6, further comprising a write delay circuit to which a first write address and a first write data input at the time of the first write access are input. The corresponding write operation to the dynamic memory cell is performed on the first write address and the first write data stored in the write delay circuit at the time of the second write access following the first write access. Characteristic semiconductor device. 10. The dynamic memory according to claim 9, further comprising a forward circuit having an address comparator, wherein in a read access, the forward circuit compares an input read address with the first write address and the address. If there is a read access at the same address as the first write address between the first write access and the second write access, the first write data is output as read data corresponding to the read access. A semiconductor device, comprising: 11. The semiconductor device according to claim 7, wherein the semiconductor device further comprises at least one cache constituted by static memory cells, and in the operation of reading data from the dynamic memory, Reading data from a memory, wherein the data is written to at least one of the caches; and when the data is erased from the cache, the data is written back to the dynamic memory in the first or second write mode. A semiconductor device characterized in that: 12. The semiconductor device according to claim 5, wherein at least one of said dynamic memory and said cache memory is integrated on a same semiconductor chip. 13. The semiconductor according to claim 5, wherein the semiconductor device further includes a central processing unit, and at least one of the central processing unit and the cache is integrated on a same semiconductor chip. apparatus 14. The semiconductor device according to claim 13, wherein at least one of said caches is a primary cache of said central processing unit. 15. The semiconductor device according to claim 5, wherein the semiconductor device further has a central processing unit, and at least one of the caches is a secondary cache of the central processing unit.