201026168 九、發明說明： •【發明所屬之技術領域】 本發明係有關於一種電路板及其製法，尤指一箱 -線路之電路板及其製法。 #超、，、田 ，【先前技術】 &咖子產業的蓬勃發展，電子產品亦逐漸邁入多功 ^〶性能的方向研發。為滿足半導體封裝件高積集产 Untegratl0n)以及微型化的封裝需求，提供 又 ❹被動元件及料脑之電路板，亦逐漸㈣層板演變成多 俾於有限的空間下’藉由層間連接技術擴大電路板 上可利用的電路面積以因應高電子密度 用需求。此外，發展超细螻心& +杜α 、冤路之使 士展超細線見的電路板亦可提升電路密 又，並可縮小晶片尺寸大小及降低晶片成本。 請參閱第1Α至1C圖所示，係為一種習知轉印法 =之製法示意圖；如第1Α圖所示，於_承載板ι〇上藉 參由電鍍或㈣方式以形成線路層⑴；如第^圖所示， 將上述第1Α圖所示之結構分別壓合至介電層12之上表面 與下表面；如第1C圖所示，移除該介電層12上表面及下 表面之承載板ίο以形成具有該線路層lu之介電層ΐ2· $ =於該介電層12及線路層⑴上形成增層 圖 式ΐ未表示）。 ί 然而，將該線路層111壓入該介電層12之表面中， 料路之線寬受限於光阻及電鍍或料能力而無法形成 超細之線路；又線路於上下對壓時，該線路之相對精度 111010 201026168 差’而不符合高精密度基板之需要，且办^ •製程（如钱刻等）景》響而造成線路浮離。易又後續之加工 . 請參閱第2A至2C圖，係為另—種羽 -示意圖；如第2A圖所示，於介電層i2 j ^電路板之製法 ，形成複數開槽120;如第2B圖所曰 藉由雷射方式以 介電層12上形成金屬層η ;如第2c圖讀些開槽120與 成於該開槽12〇中之金屬層n，以 所不，移除未形 '復可於該介電；s 12及U i / 、、友路層111;之後 ❹未表示）層金屬層U上形成增層結構(圖式中 惟，使用雷射開槽法以形成1〇微来（ 線路開槽時，則必須使用昂責之雷 、，田 成該開槽120,導致成本增加 °準分子雷射）形 者，者谁广+恤c十士 不易進行線寬控制；再 者田進仃電鍍反應時，若該開槽丨20之深官+ ratio)較大時，常限制雷供、发士 ^ <冰見比（Aspect ㈣摊m 有效地進行擴散，而不易於 忒開槽120中電鍍形成該金屬 、 志的鬥播产& 1 11特別疋雷射燒灼形 成的竭才曰底邛成圓弧狀，令電 罾诚武却^, 奴欣文雞以擴散至深層的開 =靠度 槽120底部常無法填滿金屬層，影響產 比不鑒於上述之問題’如何避免習知技術中之線寬 π 位精度差、線路浮離、加工成本高、加工 眚不ί控制等問題’而難以形成超細線寬之線路， 貫已成為目兩亟欲解決之課題。 【發明内容】 馨；上述|知技術之缺失，本發明之主要目的係提供 ]]!〇]〇 6 201026168 一種超細料並提升電性連接性能之電路板及 • 為達上述目的及其他目的，本發 牧 -層，係具有複數垂直線路，且各該垂直 線路 槽之側壁；以及第_介雷屛^ 、 ”叹於各該開 直線路之間的f於各該開槽中之各該垂 &上述之電路板，該第—介電層 光性之材料；該第-及第二介電層係可或非感 ^質復包括導電層’係形成於該線路層與第-介 電層電路板中，該些垂錢路係可顯露於該第—介 :緣又該線路層復可具有複數收納 表面該連接部可電性連接至該垂直:路:電層 岸之二=板中，該第二介電層復可設於該第-介電 ❹^ 層上；或該連接部係嵌埋於該第 埋於該第-介電;V二 該連接部係部分嵌 上。 電層中，而部分設於該第-介電層之表面 前述之電路板復可包括至少—貫穿該第 導電通孔，該導恭、$ y ^&層之 層、或塞孔材料Γ34孔中何狀金屬材、該第二介電 盥的月J l之電路板中’該第二介電層復設於該第—八+ 與線路層上。 乐介電層 ]ϊ1〇]〇 201026168 些開槽，而另電上該第-介電層之其中-表面具有該 •複數位於該第-；電層可中:置1線:板，該線純^ ',^ . 曰甲之電性連接墊，且該第一介雷爲 -中設有複數電性連接 按登且^ ”书層 •盲孔；又，於另_眚Α 〇 μ兒性連接墊及線路層之導電 面，以結合該第一中’該線路板可具有相對兩表 •介電ί =彳 路板之製法，係包括:於-第- 應之各該垂直線路之間的f及於料開槽中，相對 间丨永形成第二介電層。 又上述製法，該些開槽 式形成；該第雷射或曝先、顯影的方 且該第—及$帛1…。為感絲或非感光性之材料， :及5玄弟二介電層係可為相同或不同材質。 上述製法，該線路層之製法係可包括. 電層及各該開槽之槽壁上形成一介 ❹ 之=層’以及移除該第—介電層上之金屬層 4::各該開槽底部之部分金屬層及其覆蓋之 令該些開槽之侧壁上形成該些垂直線路 層；以及移除該第-介電声上成金屬 路。金屬層’令該㈣槽之側壁上形成該些垂直線 :上述製法’該些垂直線路係可顯露於該 表面，且料垂直線路係可延伸或未延伸至該開槽之底 111010 201026168 又该線路層復可具有複數收納於該第 •連接心該連接部可電性連接至該垂直線路。… 之電路板之製法’該第二介電層復 .第一介電層與線路層上。 取於Λ ’上述之製法復可包 兩表*之導電通孔二Λ :中:貫Λ該第一介電層 第二介電層、或塞孔材料以孔中係可填入金屬材、該 ©梓，二上：製法，該第一介電層之其中-表面具有該些開 曰 一表面上可設置一線路板，該線路板上且有 位於該第一介雷爲攸上具有複數 有複數電性連接中設 电「王逑接至各5亥電性連接墊及線路層之導電盲 樣中’該線路板可具有相對兩表： 由上可知’本發明之電路板因於較寬之開槽之側 2線路’故只需使用—般低成本之雷射設備或曝光顯影 〇ΟΧ ’又該垂直線路係由該開槽之側壁朝該開槽中心形 成’令δ亥垂直線路之寬度係酉己合鑛膜之膜厚《，俾該垂直 2路之寬度由電鐘或化鑛時間控制，而並非由如習技術之 雷射開槽之寬度控制；因此，本發明有效完成超細線路之 圖案且克服習知技術之缺點。 【實施方式】 丨 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 111010 9 201026168 第一實施例 ，㈣第3A至㈣，料本發明之電路板之製 第一貫施例之示意圖。 •如第？所示，於-第-介電層20之其中一表面上 ，以例如雷射f曝光、顯影方式形成複數開槽·，且該此 開=200之兔度係為該些垂直線路2化之寬度的至少三 該第-介電層2G係例如為感光性或非感光性之才: •如第3B圖所示’於該第―介電層2〇上 200之槽壁上形成導電層21。 第3C一1及3C_2圖所示’於該導電層21上電鍍形 成金屬層22,該金屬層22係例如為銅（㈤，如第^ ，斤丁 ’然、方;其他貫施例中，該金屬層22亦可藉由例 _鍍之方式直接形成於該第一介電層20上及各該開槽 200之槽壁上，如第3C-2圖所示。 • 如第3D-1至3D-5圖所示’係顯示不同態樣之線路； 猎例如触刻或雷射燒灼的方式移除該第一介電層2〇表 之金屬層22 ’並移除各該開槽200底部之部分金屬層 2 7 6亥些開槽200中之側壁形成複數垂直線路221& , 以作為線路層22卜且於各該開槽2〇〇中相對之各垂直線 :221a之間係形成斷路;又該垂直線路ah係顯露於該 弟一介電層20之表面。 羊i田地，如第如―1圖所示，該些垂直線路221a係延 D °玄開槽200之底部；如第3D_2圖所示，該些垂直 111010 201026168 線路221a係未延伸至各該_ _底部n 示，該線路層221復|有和赵π你# μ 圖斤 夕，查垃却99Κ 八夂數°又方；該弟一介電層20表面 •之連接邛221b’各該連接部221b ，221a，且各該連接部22比孫―么『連接至该垂直線路 面上，又1此牛2lb係元全設於該第—介電層20 广f 直線路221a未延伸至各該開槽200 -介電…並二== 又於5亥弟一介電層20之表面上。 此外’各該開槽200之寬度 之寬度的至少三倍寬。以下僅==垂直線路⑽ 製程之說明。 弟3D-2及3D-3圖作後續 如苐3E-1圖所示，传试續筮。^ -介電層20之表面上、構， 中之各該垂直線路别上及各該開槽· ❹ 線路221a之間的間隙形成第二介❹Μ 或其他增層結構（未圖示），且玆 八 電層23 :介電層，係為相同或不同材質;亦二二 :係延續第3D-2圖之結構，於各該開槽2⑽巾各 J Ϊ路2仏之間的間隙形成第二介電層23。 ^二Τ貫施例 請參閱第4圖，係為本發明 示意圖；本實_#__ 1/路板之弟二實施例之 電層20之相對兩貫施例之製法’於該第一介 參照第-實1:上形成該線路層221;後續製程可 π 111010 201026168 5月參閱第5圖，传為太狀 示咅图.士— 為本發明之電路板之第三實施例之 .’、心圖，本貫施例係於第二 ♦ 貫穿該第一介電層2〇逢恭、 $板中形成至少一 -中係可填入金屬^ a通孔222’且該導電通孔222 屬材、‘弟二介電 續製程可參照第一實施例。 $ 土 L材料；後 差四實施 請參閱第6圖，係為本發明之電路板之第四者仏 籲示意圖；於本竇絲仓丨由〆 板之弟四貝鈀例之 9 、、 中，係提供—線路板24，該線路招 24之相對兩表面t乂錄路扳 路板24之相t /矣 性連㈣241，且於該線 板上4之相對兩表面上分別結合第一實施 弟一介電層20，令各嗜命杈、*杻# Λ .9η . 谷該电性連接墊241位於該第一介電 層20中，並於各該第— 电 各嗲雷性、查垃“ 中形成複數電性連接至 各及電陡連接墊241及線路層221之導電盲 製程可參照第一實施例。 “盲孔223’後續 ❹,：明復揭露一種電路板，係包括：第一介電層2〇, 其至 > -表面具有複數開槽2〇〇;線路 數垂直線路2 21 a，且該垂直岭踗9 9彳〆 係具有複 . 芏直、，泉路22h係設於各該開槽2〇〇 土，1弟二介電層23，係設於各該開槽200中之 相對之各該垂直線路221a之間的間隙。 料4所述第介電層2〇係為感光性或非感光性之材 二;玄弟一介電層20與該第二介電層23係為相同或不同 材^而所述之第二介電層23亦可設於該第_介電層2〇 與線路層221上;該些開槽2〇〇之寬度係為該些垂直線路 111010 12 201026168 221a之寬度的至少三倍寬。 • 所述之垂直線路221a係顯露於該第一介電層2〇之表 •面，且該些垂直線路221a係延伸或未延伸至各該開槽2〇〇 • 之底部。 所述之線路層221復具有複數設於該第—介電層2〇 表面之連接部221b，該些連接部221b電性連接至該些垂 直線路221a;該些連接部221b係可完全設於該第一介電 層20之表面上、或可嵌埋於該第一介電層2〇中並顯露於 ❹該第-介電層20之表面、或可部分嵌埋於該第—介電層 20中且部分設於該第一介電層2〇之表面上。 所述之電路板復包括至少一貫穿該第一介電層20之 導電通孔222,該導電通孔222中係可填滿金屬層22，或 者，該導電通孔222中係可填入該第二介電層23或塞孔 材料（圖式中未表示）。 所述之電路板復包括增層結構（圖式中未表示），係 _設於該第一介電層2〇與線路層221上。亦或，該第一介 電層20之其中一表面具有該些開槽2〇〇，而另一表面上 設置—線路板24 ’該線路板24上設有複數位於該第一介 電層20中之電性連接墊241，且該第一介電層2〇中設有 j數電性連接至各該電性連接墊241及線路層221之導電 盲孔223。然!’於另—實施態樣中，該線路板24之兩表 面上均結合該第一介電層2〇。 纟τ、上所述’本發明之電路板因於較寬之開槽之側壁形 成田、灰路’故只需使用一般低成本之雷射設備或曝光顯影 13 111010 201026168 设備；又該垂直線路係由該開槽之側壁朝該開槽中心/ •成’令該垂直線路之寬度係配合鍍膜之膜厚度，俾該垂^ .線路之寬度由電鍍或化鍍時間控制，而並非由如習知技棘_ 之雷射開槽之寬度控制；因此，本發明有效完成超細線: …（如小於1〇n)之圖案且克服習知技術之缺點。 上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範嚕下，對上述^施例進行修 β改戶。因此本發明之權利保護範圍’應如後述之中請專利範 I辜I戶歹j 【圖式簡單説明】 第1Α至1C圖係為習知之電路板之製法示意圖； =2八至2C圖係為f知之電路板之另—製法示意圖; 3A至3E圖係為本發明之電路板之製法之第一實施 例之示意圖，·其中，第3C—丨圖係 ❹ 能样a _ * υ A圓你马第3C-2圖之不同實施 U取之示意圖；第3D—j 音圖•筮π , — ^叫丨小句个叫貫施態樣之 及3Ε 2 ®係為不同實施態樣之示意圖； ί圖係為本發明之電路板之第二實施例之示意圖 圖，·=圖係為本發明之電路板之第三實施例之示j 意圏m…一圖係、為不同實施態樣之示 實施例之示意圖。 第6圖係為本發明之電路板之第四 【主要元件符號說明】 承載板 11、22 金屬層 111010 14 201026168 111 ' 221 線路層 12 • 介電層 120 > 200 開槽 -20 第一介電層 • 21 導電層 221a 垂直線路 221b 連接部 222 導電通孔 ❿23 第二介電層 24 線路板 241 電性連接墊 223 導電盲孔201026168 IX. Description of the invention: • [Technical field to which the invention pertains] The present invention relates to a circuit board and a method of manufacturing the same, and more particularly to a box-line circuit board and a method of manufacturing the same. #超,,,田, [previous technology] & the development of the coffee industry, electronic products have gradually entered the direction of multi-functional performance. In order to meet the packaging requirements of semiconductor packages and the miniaturized package, the circuit boards of passive components and materials are provided, and the (four) layers are gradually evolved into more than a limited space. Expand the circuit area available on the board to meet the demand for high electron density. In addition, the development of ultra-fine care & + Du α, the road to see the ultra-fine line of the board can also improve the circuit density, and can reduce the size of the chip and reduce the cost of the wafer. Referring to Figures 1 to 1C, it is a schematic diagram of a conventional transfer method = as shown in Fig. 1 , by means of electroplating or (4) on the _ carrying board ι to form a wiring layer (1); As shown in FIG. 2, the structures shown in FIG. 1 are respectively pressed onto the upper surface and the lower surface of the dielectric layer 12; as shown in FIG. 1C, the upper surface and the lower surface of the dielectric layer 12 are removed. The carrier layer ίο is formed to form a dielectric layer 该2·$= having the wiring layer lu on the dielectric layer 12 and the wiring layer (1) to form a build-up pattern (not shown). ί However, the circuit layer 111 is pressed into the surface of the dielectric layer 12, and the line width of the material path is limited by the photoresist and plating or material ability, and the ultra-fine line cannot be formed; The relative accuracy of the line is 111010 201026168. The difference is not in line with the need of a high-precision substrate, and the process of making a process (such as money engraving) causes the line to float. Easy and subsequent processing. Please refer to Figures 2A to 2C for another feather-schematic diagram; as shown in Figure 2A, in the dielectric layer i2 j ^ circuit board manufacturing method, a plurality of slots 120 are formed; 2B shows a metal layer η formed on the dielectric layer 12 by laser; as shown in FIG. 2c, the trench 120 is formed and the metal layer n formed in the trench 12 is removed. The shape 'recombines the dielectric; s 12 and U i /, the friend layer 111; after ❹ not shown) the layer metal layer U forms a build-up structure (in the figure, only using the laser slotting method to form 1 〇 micro (when the line is slotted, you must use the thunder of the blame, Tian Cheng the slot 120, resulting in increased cost ° excimer laser) shape, who is wide + shirt c ten is not easy to line width Control; in the case of the Tianjin 仃 electroplating reaction, if the depth of the shovel 20 is large, the mine is often limited, and the ice is often limited. It is not easy to pry open the groove 120 to form the metal, and the cockroach broadcasts the production & 1 11 special 疋 烧 烧 烧 烧 烧 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 ^ ^ ^ ^ ^ ^ ^ The broiler spreads to the deep layer of the opening = the bottom of the groove 120 is often unable to fill the metal layer, affecting the production ratio without considering the above problems. How to avoid the line width π-bit precision difference, line floating, processing cost in the prior art It is difficult to form a line of ultra-fine line width, which is difficult to form a line of ultra-fine line width. [Summary of the Invention] The main purpose of the present invention is to provide a lack of the above-mentioned technology. ]]!〇]〇6 201026168 A circuit board with ultra-fine materials and improved electrical connection performance and • For the above and other purposes, the present invention has a plurality of vertical lines, and each of the vertical line slots a side wall; and a material sighing between each of the straight lines, each of the slats in the slats and the above-mentioned circuit board, the material of the first dielectric layer; The first and second dielectric layers may or may not include a conductive layer formed in the circuit layer and the first-dielectric layer circuit board, and the dips can be exposed to the first : the edge and the circuit layer can have a plurality of storage surfaces, the connection Electrically connected to the vertical: way: the second layer of the electrical layer = the plate, the second dielectric layer can be disposed on the first dielectric layer; or the connecting portion is embedded in the first buried In the first dielectric layer, the connection portion is partially embedded in the electrical layer, and the circuit board partially disposed on the surface of the first dielectric layer may include at least through the first conductive via hole. Guide layer, layer of y ^ & layer, or plug hole material Γ 34 holes in the metal material, the second dielectric 盥 month J l circuit board 'the second dielectric layer is set in the first -8+ on the circuit layer. Le dielectric layer]ϊ1〇]〇201026168 some slots, and the other part of the first-dielectric layer-surface has the complex number in the first--electric layer: Set 1 line: board, the line is pure ^ ', ^ . The electrical connection pad of the armor, and the first medium mine is - with a plurality of electrical connections according to the board and ^ "book layer • blind hole; In another 眚Α 〇 儿 儿 连接 连接 连接 及 及 及 及 及 及 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿 儿- should each of the vertical lines In the inter-f and the material trench, a second dielectric layer is formed in the opposite direction. In the above method, the slotted formation is formed; the first laser is exposed or exposed, and the first and the first are formed. For sensitive or non-photosensitive materials, and 5 Xuandi two dielectric layers can be the same or different materials. In the above method, the circuit layer manufacturing method may include: forming a dielectric layer on the electrical layer and each of the grooved trench walls; and removing the metal layer 4 on the first dielectric layer: each of the trenches a portion of the metal layer at the bottom and the cover thereof form the vertical line layers on the sidewalls of the slots; and removing the first-dielectric sound-forming metal path. The metal layer 'forms the vertical lines on the sidewalls of the (four) slots: the above method 'the vertical lines can be exposed on the surface, and the vertical lines can extend or not extend to the bottom of the slots 111010 201026168 The circuit layer may have a plurality of storage ports connected to the first connection. The connection portion may be electrically connected to the vertical line. The method of manufacturing the circuit board is as follows. The second dielectric layer is formed on the first dielectric layer and the circuit layer. According to the above method, the conductive vias of the two tables* can be packaged: the second dielectric layer of the first dielectric layer or the plug material can be filled with metal in the hole, The method of manufacturing, the first dielectric layer has a surface on which a surface is provided, and a circuit board is disposed on the circuit board, and the circuit board has a plurality of There is a plurality of electrical connections in which "Wang Hao is connected to each of the 5 electrical connection pads and the conductive layer of the circuit layer." The circuit board can have two opposite tables: It can be seen from the above that the circuit board of the present invention is The wide slotted side 2 line 'is only need to use a low-cost laser device or exposure development 〇ΟΧ' and the vertical line is formed by the sidewall of the slot toward the slotted center. The width is the film thickness of the mercaping film. The width of the vertical channel is controlled by the electric clock or the time of the mineralization, and is not controlled by the width of the laser grooving according to the prior art; therefore, the invention is effectively completed. The pattern of ultra-fine lines overcomes the shortcomings of the prior art. [Embodiment] The specific embodiments of the present invention are described by those skilled in the art, and other advantages and effects of the present invention can be easily understood by the disclosure of the present disclosure. 111010 9 201026168 First Embodiment, (4) 3A to (4), A schematic diagram of a first embodiment of the circuit board of the present invention. • As shown in the above, a plurality of slots are formed on one surface of the first dielectric layer 20 by, for example, laser f exposure and development. And the degree of the rabbit of the opening = 200 is at least three of the widths of the vertical lines. The first dielectric layer 2G is, for example, photosensitive or non-photosensitive: • as shown in FIG. 3B. A conductive layer 21 is formed on the trench wall of the first dielectric layer 2 。 200. The metal layer 22 is formed by electroplating on the conductive layer 21 as shown in FIGS. 3C-1 and 3C_2, and the metal layer 22 is, for example, copper. (5), as in the case of ^, 斤丁然, square; in other embodiments, the metal layer 22 can also be directly formed on the first dielectric layer 20 and each of the slots 200 by way of example plating On the wall of the tank, as shown in Figure 3C-2. • As shown in Figures 3D-1 to 3D-5, the line showing the different patterns Removing the metal layer 22' of the first dielectric layer 2 and removing a portion of the metal layer at the bottom of each of the trenches 200, such as a etch or laser cauterization. The sidewalls form a plurality of vertical lines 221 & as a circuit layer 22 and an open circuit is formed between the respective vertical lines: 221a in each of the slots 2; and the vertical line ah is exposed to the younger brother The surface of the electric layer 20. In the field of the sheep, as shown in Fig. 1, the vertical lines 221a are extended to the bottom of the D° stencil 200; as shown in Fig. 3D_2, the vertical 111010 201026168 lines 221a are Not extending to each of the _ _ bottom n shows that the circuit layer 221 complex | has and Zhao π you # μ Figure jin eve, Cha La but 99 Κ eight 夂 number ° square; the brother a dielectric layer 20 surface • the connection邛 221b' each of the connecting portions 221b, 221a, and each of the connecting portions 22 is connected to the vertical line surface, and the other 2 lb system is disposed on the first dielectric layer 20 wide f straight line The path 221a does not extend to each of the slots 200 - dielectric ... and two = = again on the surface of the dielectric layer 20 of the 5th. Further, the width of each of the slits 200 is at least three times wider than the width. The following is only a description of the == vertical line (10) process. The 3D-2 and 3D-3 pictures are followed up. As shown in Figure 3E-1, the test is continued. a second dielectric layer or other build-up structure (not shown) is formed on the surface of the dielectric layer 20, the gap between each of the vertical lines and the respective trenches 221 221a, and八八层23: dielectric layer, the same or different materials; also two: the continuation of the structure of Figure 3D-2, in the gap between each of the slot 2 (10) towel J Ϊ 2 Two dielectric layers 23. ^ 二Τ例 Example, please refer to Figure 4, which is a schematic diagram of the present invention; the actual method of the second embodiment of the electric layer 20 of the second embodiment of the _#__ 1/Road Referring to the first-solid 1: forming the circuit layer 221; the subsequent process can be π 111010 201026168 May to refer to the fifth figure, which is transmitted as a too-shaped diagram. The present invention is the third embodiment of the circuit board of the present invention. The first embodiment is formed in the second dielectric layer 2 through the first dielectric layer 2, and the at least one-middle-system can be filled with a metal via 222' and the conductive via 222 For the genus material, the second dynamometer process can be referred to the first embodiment. $ soil L material; after the implementation of the four differences, please refer to Figure 6, which is the fourth of the circuit board of the present invention; in this sinus silk shovel by the scorpion brother Sibei palladium case 9 , , Provided by the circuit board 24, the line is opposite to the two surfaces t乂 the circuit board 24 phase t / 矣 连 (4) 241, and the first two sides of the opposite side of the board 4 are combined with the first implementation a dielectric layer 20, such that each of the fatality, *杻# Λ.9η. Valley, the electrical connection pad 241 is located in the first dielectric layer 20, and in each of the first Referring to the first embodiment, the conductive blind process for forming a plurality of electrical connections to each of the electrical and steep connection pads 241 and the circuit layer 221 can be referred to the first embodiment. The "blind hole 223" is followed by a smear: a circuit board is disclosed, including: The first dielectric layer 2〇, to the surface of the surface having a plurality of slots 2〇〇; the number of lines is 2 21 a, and the vertical ridges 9 9 具有 has a complex line. It is disposed in each of the slots 2, and the first dielectric layer 23 is disposed in a gap between each of the vertical lines 221a in each of the slots 200. The dielectric layer 2 is made of photosensitive or non-photosensitive material 2; the dielectric layer 20 and the second dielectric layer 23 are the same or different materials and the second The dielectric layer 23 may also be disposed on the first dielectric layer 2 and the circuit layer 221; the width of the trenches 2 is at least three times wider than the width of the vertical lines 111010 12 201026168 221a. • The vertical line 221a is exposed on the surface of the first dielectric layer 2, and the vertical lines 221a extend or do not extend to the bottom of each of the slots. The circuit layer 221 has a plurality of connecting portions 221b disposed on the surface of the first dielectric layer 2, and the connecting portions 221b are electrically connected to the vertical lines 221a. The connecting portions 221b can be completely disposed on the connecting portion 221b. The surface of the first dielectric layer 20 may be embedded in the first dielectric layer 2 and exposed on the surface of the first dielectric layer 20, or may be partially embedded in the first dielectric layer The layer 20 is partially disposed on the surface of the first dielectric layer 2A. The circuit board includes at least one conductive via 222 extending through the first dielectric layer 20, and the conductive via 222 is filled with the metal layer 22, or the conductive via 222 can be filled in the conductive via 222. The second dielectric layer 23 or plug material (not shown in the drawings). The circuit board includes a build-up structure (not shown), and is disposed on the first dielectric layer 2 and the circuit layer 221. Or, one of the surfaces of the first dielectric layer 20 has the slots 2〇〇, and the other surface is provided with a circuit board 24 ′. The circuit board 24 is provided with a plurality of the first dielectric layer 20 The electrical connection pads 241 are disposed, and the first dielectric layer 2 is provided with a plurality of conductive vias 223 electrically connected to the electrical connection pads 241 and the circuit layer 221 . However, in another embodiment, the first dielectric layer 2 is bonded to both surfaces of the circuit board 24.纟τ, the above-mentioned 'the circuit board of the present invention forms a field and a gray road due to the side wall of the wider slot, so it is only necessary to use a general low-cost laser device or an exposure developing 13 111010 201026168 device; The line is made from the side wall of the groove toward the center of the groove. The width of the vertical line is matched with the film thickness of the coating, and the width of the line is controlled by plating or plating time, and not by The width control of the laser slotting is conventional; therefore, the present invention effectively completes the pattern of ultra-fine lines: (e.g., less than 1〇n) and overcomes the shortcomings of the prior art. The above-described embodiments are intended to illustrate the principles of the invention and its advantages, and are not intended to limit the invention. Anyone who is familiar with the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as described in the following. Patent Specification I辜I 歹j [Simple Description of the Drawings] The first to the 1C drawings are schematic diagrams of the conventional circuit board; =2-8 to 2C FIG. 3A to 3E are diagrams showing the first embodiment of the method for manufacturing a circuit board of the present invention, wherein the 3C-丨 diagram system can be a _ * υ A circle The schematic diagram of the different implementations of the 3C-2 diagram of your horse; the 3D-j sound map • 筮π, — ^ 丨 丨 个 个 个 Ε Ε Ε Ε Ε Ε Ε ® ® ® ® ® ® ® ® ® ® The figure is a schematic view of a second embodiment of the circuit board of the present invention, and the figure is a third embodiment of the circuit board of the present invention, which is a diagram of a system, which is a different embodiment. A schematic of the illustrated embodiment. Figure 6 is the fourth circuit board of the present invention. [Main component symbol description] Carrier board 11, 22 Metal layer 111010 14 201026168 111 '221 Circuit layer 12 • Dielectric layer 120 > 200 Slot -20 First Electrical layer • 21 conductive layer 221a vertical line 221b connecting portion 222 conductive through hole 第二 23 second dielectric layer 24 circuit board 241 electrical connection pad 223 conductive blind hole