Ϊ376988 九、發明說明： 【發明所屬之技術領域】 本^明係有關於一種電路板及其製法，尤指_種超細 、-泉路之電路板及其製法。 【先前技術】 〜隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 …性能的方向研發。為滿足半導體封裝件高積隼戶 (Integrate)以及微魏的封裝需求，提供多數= 丨；動元件及線路載接之電路板，亦逐漸由單層板演變成多 純’俾於有_空間下’藉由相連接技術擴大電2 =用的電路面積以因應高電子密度之積體電路之使 ^。^外’發展超細線寬的電路板亦可提升電路密 X ’並可縮小晶月尺寸大小及降低晶片成本。 - 請參閱第1八至1C圖所示，係為一種習知轉印法之帝 路板之製法示意圖；如第1A圖所示，於—承載板1〇上二 由電鍍❹刻方式以形成線路層⑴；如第ΐδ圖所示，曰 將上述第1Α圖所示之結構分別麗合至介電層^之上表面 與下表面；如第lc圖所示，移除該介電層12上表面及、下 表面之承載板10以形成具有該線路層⑴之介電 之後可於該介電層12及線路層⑴上形成 ς圖 式中未表示）。 . #(圖Ϊ 376988 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a circuit board and a method of manufacturing the same, and more particularly to a circuit board of ultra-fine, -spring road and a method of manufacturing the same. [Prior Art] ~ With the booming development of the electronics industry, electronic products have gradually entered the direction of multi-functional ... performance. In order to meet the packaging requirements of semiconductor packages, Integrate and Weiwei, most of the circuit boards are provided, which are gradually evolved from single-layer boards to multi-pure. Under the 'connection technology to expand the electricity 2 = the circuit area used to respond to the high electron density of the integrated circuit ^. ^External development of ultra-thin linewidth boards can also increase the circuit density and reduce the size of the crystal and reduce the cost of the wafer. - Please refer to Figures 18 to 1C, which is a schematic diagram of a method for fabricating a conventional transfer method; as shown in Fig. 1A, on the carrier plate 1 is formed by electroplating to form a circuit layer (1); as shown in the ΐδ diagram, the structure shown in the above first drawing is respectively coupled to the upper surface and the lower surface of the dielectric layer; as shown in FIG. lc, the dielectric layer 12 is removed. The carrier plate 10 on the upper surface and the lower surface may be formed on the dielectric layer 12 and the circuit layer (1) after forming a dielectric layer having the circuit layer (1). . #(图
x I 然而，將該線路層】】】壓入該介電層】2之孑面 該線路之線寬受限於光阻及電鍍或蝕刻能力而無成 超細之線路’·叉線路於上下對壓時，該線路之相對精度 ]]]〇]〇 5 1376988 ί程而合高精密度基板之需要，且容易受後續之加工 衣稜（如蝕刻等）影響而造成線路浮離。 請參閱第2Α至2C圖，係為另一種羽 不意圖；如第2Α圖所示，於介電層：心板之製法 ，數開請;如第㈣所示，==式以 介電層U上形成金屬層11;如第沈圖^/礼⑽與 成於該開槽120中之金屬層U，以 不’移除未形 復可於該介電層12及金屬層12上形之後 >未表示）。 成0層、吉構（圖式中 .線二: = :Γ以形成10微W下之細 成該開槽，導致成本雷射)形 者，•進行電錢反應時，若該開 見控，，再 灿。)較大時，常限制電鑛液 二之：見比(Aspect 該開槽120中電鍍形成 進订擴放，而不易於 ，成的開槽底部成圓弧狀，令電屬上=特別㈣ 槽底部，導致該開槽12〇 ^更難以擴散至深層的開 品可靠度。 —吊…'法填滿金屬層，影響產 因此’鑒於上述之問 比不良、線#何避免習知技術中之線寬 匕个民線路對位精度差、線路一 難度高且/不易控制等問 σ工成本尚、加工 實已成為目前 Q 、而難以形妓超細線寬之绨路， 男匕成馮目刖亟欲解决之課題。x I However, the circuit layer]]] is pressed into the dielectric layer] 2, the line width of the line is limited by the photoresist and plating or etching ability without the ultra-fine line '· fork line up and down When the pressure is applied, the relative accuracy of the line]]] 〇 〇 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Please refer to pictures 2 to 2C, which is another type of feather; as shown in the second figure, in the dielectric layer: the method of making the core, the number is open; as shown in the fourth (4), the == is the dielectric layer A metal layer 11 is formed on U; as in the case of the first sinking layer (10) and the metal layer U formed in the trench 120, after the unshaped amorphous layer 12 and the metal layer 12 are not removed >not shown). In the 0 layer, the structure (in the figure, the line 2: = : Γ to form a fine 10 μW into the slot, resulting in a cost laser), • when the electricity money reaction, if the control ,, and then can. When it is large, it often limits the electric ore liquid: see the ratio (Aspect in the slot 120, the plating is formed into a predetermined expansion and expansion, which is not easy, and the bottom of the groove is formed into an arc shape, so that the electricity is on the special = (four) At the bottom of the trough, the reliability of the opening of the trough 12〇 is more difficult to diffuse into the deep layer. The method of “hanging” is filled with the metal layer, which affects the production. Therefore, in view of the above-mentioned problems, the line #he avoids the conventional technology. The line width is narrow, the accuracy of the alignment of the pedestrian line is high, the difficulty of the line is high, and it is difficult to control. The cost of the work is still the current Q, and it is difficult to shape the road of ultra-fine line width. I want to solve the problem.
f發明内容J 參於上述習知技術之缺失，本發明之主要目的係提供 ])!〇]〇 -種超：線路並提升電性連接性能之電路板及其製法。 為達上述目的及其他目的，本發明揭露—種 係包括··第一介電声，苴 电路板： 層’係具有複數垂直線路，且各該垂直 ；::路 直線路:間=:介電層’一該開槽中之各該垂 光'二之一介電層係可為感光性或非感 I ,, ^ ，VA弟及弟二；丨電層係可為相同或不如P! 間:復包括導電層，係形成於該線路層與第—介電層^ 電片之^ ^ ^板中’ 3些垂直線路係可顯露於該第-介 電層之表面，且該些垂直蜱 之底部；X該線路層復;或未延伸至該開槽 =接部，料接部可電性連接至該垂直線路。θ :述之電路板中’該第二介電層復可 f線路層上；或該連接部係嵌埋一 層中，並顯露於該第一介電 "電 上弟一介電層中’而部分設於該第-介電層之表面 =之電路板復可包括至少一貫穿該第一 導包通孔’ S玄導電通孔中作 〈 層、或塞孔材料。 η填k金屬材、該第二介電 前述之電路板中，該第-八 與線路層上。 1笔層復設於該第-介電層 1Π010 7 丄：> 珂述之電路板中，該第一介带 些開槽，而另—矛而 电运’、—表面具有該 複數位於該第-二^可中^—線路板，該線路板上具有 中設有複數電性連Γ;二性連接塾’且該第-介電層 盲孔；又，於另一連實接電性連接塾及線路層之導電 面，以結合該第中’該線路板可具有相對兩表 介電rm:種電路板之製法，係包括··於-第-SUMMARY OF THE INVENTION In view of the above-mentioned deficiencies of the prior art, the main object of the present invention is to provide a circuit board and a method for manufacturing the same. To achieve the above and other objects, the present invention discloses a system comprising: a first dielectric sound, a circuit board: a layer having a plurality of vertical lines, and each of which is vertical;:: a straight line: between =: The electrical layer 'one of the dielectric layers in the trenches' may be photosensitive or non-inductive I, ^, VA and brother 2; the electrical layer may be the same or not as good as P! Between: a conductive layer is formed in the circuit layer and the first dielectric layer of the dielectric layer, and three vertical lines are exposed on the surface of the first dielectric layer, and the vertical The bottom of the crucible; X the circuit layer is complex; or does not extend to the slot = junction, the material connection can be electrically connected to the vertical line. θ: in the circuit board, the second dielectric layer is on the circuit layer; or the connection portion is embedded in a layer and is exposed in the first dielectric "electrically on a dielectric layer And the circuit board partially disposed on the surface of the first dielectric layer may include at least one through the first conductive via hole 'S' conductive via hole as a layer or a plug material. η fills the k metal material, the second dielectric in the aforementioned circuit board, the VIIIth and the circuit layer. 1 pen layer is disposed on the first dielectric layer 1Π010 7 丄:> in the circuit board described above, the first interposer has some slots, and the other spears are electrically transported, the surface has the complex number located at The first-two-^ can be in the circuit board, the circuit board has a plurality of electrical connection ports therein; the two-dimensional connection 塾' and the first-dielectric layer blind hole; and, in another connection, the electrical connection导电 and the conductive surface of the circuit layer, in combination with the middle of the circuit board can have a relative two-dielectric rm: a circuit board manufacturing method, including ···--
表面形成複數開槽；於該此門M :::直線路’以作為線路層;以及於各該開;曹;之= 應之各該垂直線路之間的間隙形成第二介電層。 依上述製法，該些開槽係可以雷射或曝光、 式形成丨該第一介電声将…〜’方 m η ^ 為感光性或非感光性之材料， 弟 亥弟二介電層係可為相同或不同材質。 依上述製法，該線路層之製法係可 電層及各該開槽之槽壁上形成導電層.於 j第" •形成金屬層;以及移除該第-介電層上之:屬 電層’並移除各該開槽底部之部分金屬層及1覆：： 導-电層，令該些開槽之側壁上形成該些垂直線路。 居亦或，於該第一介電層上及各該開槽中化錄形成金屬 二’以及移除介電層上之金屬層，並移除各該開槽 ^部之部分金屬層，令該些開槽之側壁上形成該些垂直線 依上述製法，該些垂直線路係可顯露於該第—介電層 之表面，且該些垂直線路係可延伸或未延伸至該開槽之底 111010 8 部；又該線路層復可具有複數收心—人 ，㈣接蝴直f表面之 第-介製法’該第二介電層復可形成於該 . 上述之製法復可包括-形成至少一孙*吁外人+ & Λ主二^ 貝穿該第一介電層 兩表面之‘電通孔，且該導 笛-八电通孔中係可填入金屬材、該 弟一 電層、或塞孔材料。 =製法’該第一介電層之其中一表面具有該些開 表面上可①置—線路板’該線路板上具有複數 古玄苐一介電層中之電性連接墊，且該第-介電層中設 複數電性連接至各該電性連接墊及線路層之導電盲 ' 於另貝施悲樣中，該線路板可具有相對兩表面， 以結合該第一介電層。 由上可知’本發明之電路板因於較寬之開槽之側壁形 j、、、田線路’故只需使用一般低成本之雷射設備或曝光顯影 i °又備，又戎垂直線路係由該開槽之側壁朝該開槽中心形 成，令該垂直線路之寬度係配合鍍膜之膜厚度，俾該垂直 線路之見度由電鍍或化鍍時間控制，而並非由如習技術之 田射開槽之寬度控制；因此’本發明有效完成超細線路之 圖案且克服習知技術之缺點。 【實施方式】 j 以下藉由特定的具體實施例說明本發明之實施方 式A悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 9 111010 1376988The surface is formed with a plurality of slots; the gate M::straight line is used as the circuit layer; and each of the openings is formed; Cao; = the gap between each of the vertical lines forms a second dielectric layer. According to the above method, the slotting system can be formed by laser or exposure, and the first dielectric sound will be...~' square m η ^ is a photosensitive or non-photosensitive material, and the two dielectric layers are Can be the same or different materials. According to the above method, the circuit layer is formed by forming an electrically conductive layer on the electrically conductive layer and each of the grooved groove walls. The formation of the metal layer is performed; and the removal of the first dielectric layer: The layer 'and removes a portion of the metal layer at the bottom of each of the trenches and a layer of: a conductive layer to form the vertical lines on the sidewalls of the trenches. Or, on the first dielectric layer and in each of the slots, the metal layer is formed and the metal layer on the dielectric layer is removed, and a portion of the metal layer of each of the trench portions is removed. Forming the vertical lines on the sidewalls of the slots according to the above method, the vertical lines may be exposed on the surface of the first dielectric layer, and the vertical lines may extend or not extend to the bottom of the slot 111010 8; and the circuit layer can have a plurality of hearts - people, (4) the first - dielectric method of the surface of the straight f - the second dielectric layer can be formed in the above. The above method can include - forming at least One child* yue outsider + & Λ 二 二 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Or plug material. The method of the first dielectric layer has one of the surface of the first dielectric layer, and the circuit board has a plurality of electrical connection pads in the dielectric layer, and the first The dielectric layer is electrically connected to each of the electrical connection pads and the circuit layer. The circuit board may have opposite surfaces to bond the first dielectric layer. It can be seen from the above that the circuit board of the present invention is only required to use a general low-cost laser device or an exposure developing device, and a vertical line system, due to the wide-grooved sidewall shape j, and the field circuit. Forming the sidewall of the slot toward the center of the slot, such that the width of the vertical line matches the film thickness of the coating, and the visibility of the vertical line is controlled by plating or plating time, and is not caused by the field of the prior art. The width control of the slot; therefore, the present invention effectively completes the pattern of ultra-fine lines and overcomes the shortcomings of the prior art. [Embodiment] The following describes the embodiments of the present invention by way of specific embodiments. Those skilled in the art can readily understand the other advantages and effects of the present invention from the disclosure of the present disclosure. 9 111010 1376988
請參間第3A至3e圖，伤A 第-實制之示意圖。為切明之電純之裂法之 如第3'圖所示’於—第—介電層2〇之其中— 開样二二…形成複數·開槽-2 〇 0…，且該也 二:2°〇::f:為該些垂直線路仙之寬度的至少： 1 %層2〇係例如為感光性或非感光性之材 灸如第3B圖所示，於今箪—入 _之槽壁上形成導電層、^ %層2〇上及.各該開槽 第3C_1及3C'2圖所示’於該導電層21上電㈣ 成金屬層22’該金屬層22係例如 ^ 然，於其他一該金㈣亦 200 :二:式直接形成於該第—介電層2〇上及各該開槽 200之槽壁上，如第3C-2圖所示。 夢由ST 3ΙΜ至圖所示’係顯示不同態樣之線路； ^ =钱刻或雷射燒灼的方式移除該第一介電層別表 ，22,並移除各該開槽2〇〇底部之部分金屬層 :该些開槽200中之側壁形成複數垂直線路22ia， =線路層221’且於各該開槽2〇〇中相對之各垂直線 =之間係形成斷雄；又該垂直線路221&係顯露於該 弟一介電層20之表面。 詳細地，如第3D-1圖所示，該些垂直線路。“係延 各該開槽2〇〇之底部；如第3D-2圖所示，該些垂直 111010 10 ^/6988 線路22ϋ未延伸至各該開槽2〇〇底部 不’該線路層221復具有複數設 f 3D 3圖所 ”’各該連接部221b電性連 ： 且各該連接部221b係完全設於該第直= 之表面上，又該些垂直線路22ia未 日20 底部；如第3D-4 FI邮- f至。違開槽20〇 二第-介電層2。之表面;如第 Q斤丁各该連接部22113係部分嵌埋 丨層2〇中，且部分設於該第一介電層2〇之表面上… =’各該開槽2。。之寬度係為各該 三倍寬。以下僅以第—』 -介係延續第3D-3圖之結構，於該第 中連接部伽上及各該開槽_ 或h 之間的間隙形成第二介電層23 •IS電：層::丄未圖示），且該第一介電層20與曰該第 —/曰23係為相同或不同材質；亦可如第3e、2 :知延續第3D-2圖之結構’於各該開槽2〇〇中，各該 =一、!路221a之間的間隙形成第二介電層㈡。 示^青參Π4圖:係為本發明之電路板之第二實施例之 θ，户' 轭例係藉由第—實施例之製法，於該第一八 相對兩表面上形成該線路層221; ; 荃恥乐一實施例。 1 ]]]〇]〇 11 ^376988 一施例 :參閱第5圖，係為本發明之電路板之第三實施例之 貫本實施例係於第二實施例之電路板中形成至少-介電層20之導電通孔微，且該導電通孔222 二C.第二介電層23、或塞孔她後 貝衣％可參照第一實施例。 U施例 *意係為本發明之電路板之第四實施例之 24之;目對兩/二例中，係提供—線路· 24 ’該線路板 .路板24之相成有複數電性連接塾241，且於該線 第一 分別結合第一實施例之電路板之 月20中曰電性連接塾241位於該第一介電 二卜’亚於各該第一介電層20中形成複數電性連接至 連^241及線路層221之導電盲孔 I备可參照第一實施例。 傻只 本發明復揭露-種電路板，係包括：第— 數;有複數開槽I線路層221，係具有複 之側壁：ΓΓ且八該垂直線路221&係設於各該開槽2°〇 土，以及弟二介電層23，係設於各該開枰 相對之各該垂直線路221a之間的間隙。曰 料，該戶層2G係為感紐或非感光性之材 材質；而所述之曰笫Γ該第二介電層23係為相同或不同 與線路声221上Γ電層23亦可設於該第—介電層2〇 9上’遠些開槽2〇〇之寬度係為該些垂直線路 111010 12 1376988 22la之寬度的至少三倍寬。 所述之垂直線路221Μ“頁露於該第一介電 面’且該些垂直線路221a#延柚弋去兑从” θ 之表 之底部。 係延伸或未延伸至各該開槽2〇〇 -所述之線I層221復具有複數設於該第_介 表面之連接部221b，該些連接部2m電性連接至該曰此〇 直線路221a;該些連接部221b係可完全設於节第二垂 二Γ之上面上、或可後埋於該第-介電層2”並顯2 ：H20广表面、或可部分嵌埋於該第-介電展 且部分设於該第一介電層20之表面上。 运 所述之電路板復包括至少一貫穿該第一介電 ‘電通孔222,該導泰捅了丨000丄 ( 者，$ 孔222中係可填滿金屬層22,曳 者以電通孔222中係可填入該第戍 材料（圖式中未表示）。 h層23或塞孔 ^ 述之電路板復包括增層結構（圖式中未表示 C思 介電層20與線路層221上。亦或，今第八、 電層20之A中一本品曰本 A "亥弟一介 設置…： 面具有該些開槽，而另-表面上 電声2(Γ中反24，該線路板24上設有複數位於該第一介 电層20中之電性連 複數電性連接5夂 第一介電層20中設有 盲孔州 連㈣24】及線路層⑵之導電 目孔223。然丨，於另一盘 午电 面上均結合該苐一介電；2V:…5线路板24之兩表 成細：二返亡電路板因於較寬之開槽之側壁形 而吏用般低成本之雷射設備或曝光顯影 J3 ⑴ 0H) I376988 備’又έ亥垂直線路係由該開槽之側壁朝該開槽中心形 ‘成，令該垂直線路之寬度係配合鍍膜之膜厚度，俾該垂直 •線路之寬度由電鍍或化鍍時間控制，而並非由如習知技術 之田射開槽之寬度控制；因此，本發明有效完成超細線路 (如小於1-0./i.m)之圖案且克服習知技術之缺點。 . 上述實施例係用以例示性說明本發明之原理及其功 -效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不延背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範 •圍所列。 【圖式簡單説明】 第1A至1C圖係為習知之電路板之製法示意圖； :2A至2C圖係為習知之電路板之另一製法示意圖; 弟至3E圖係為本發明之電路板之製法之第一實施 例之示意圖丨其中，第3(M圖 弟Please refer to Figures 3A to 3e for a diagram of the injury-first-implementation. In order to clarify the electricity pure cracking method, as shown in Figure 3', the first layer of the dielectric layer 2 is opened - the second and second layers are formed... the complex number is formed, the groove is -2 〇0..., and the second is: 2°〇::f: at least the width of the vertical lines: 1% of the layers 2, for example, photosensitive or non-photosensitive moxibustion as shown in Fig. 3B, in the wall of the current Forming a conductive layer, forming a conductive layer, and forming a metal layer 22 on the conductive layer 21, wherein the metal layer 22 is, for example, as shown in FIG. 3C_1 and 3C'2. The other one of the gold (4) is also 200:2: directly formed on the first dielectric layer 2〇 and the groove walls of each of the slots 200, as shown in FIG. 3C-2. Dreams from ST 3 ΙΜ to the figure shown in the figure 'shows different patterns of lines; ^ = money engraved or laser cauterized way to remove the first dielectric layer table, 22, and remove each of the slots 2 bottom a portion of the metal layer: the sidewalls of the slots 200 form a plurality of vertical lines 22ia, = circuit layer 221' and between each of the vertical lines in each of the slots 2, a broken male is formed; Line 221 & is exposed on the surface of the dielectric layer 20 of the younger brother. In detail, as shown in Fig. 3D-1, the vertical lines. "The bottom of each slot is 2"; as shown in Figure 3D-2, the vertical 111010 10^/6988 lines 22ϋ do not extend to the bottom of each slot 2, and the circuit layer 221 Each of the connecting portions 221b is electrically connected to each other: and each of the connecting portions 221b is completely disposed on the surface of the first direct=, and the vertical lines 22ia are not at the bottom of the day 20; 3D-4 FI Mail - f to. Violation of the slot 20 〇 two-dielectric layer 2. The surface of each of the connecting portions 22113 is partially embedded in the layer 2, and partially disposed on the surface of the first dielectric layer 2: = ' each of the slots 2. . The width is three times as wide as each. In the following, only the structure of the 3D-3 is continued, and the second dielectric layer 23 is formed on the gap between the middle connection portion and each of the slots _ or h. :: 丄 not shown), and the first dielectric layer 20 and the first / / 曰 23 are the same or different materials; can also be as 3e, 2: know the structure of the 3D-2 diagram In each of the slots 2, a gap between each of the ones and the paths 221a forms a second dielectric layer (2). Figure 4 is a diagram showing a second embodiment of the circuit board of the present invention. The household yoke is formed on the first eight opposite surfaces by the method of the first embodiment. ; ; 荃 shame an embodiment. 1]]]〇]〇11 ^ 376988 an embodiment: refer to FIG. 5, which is a third embodiment of the circuit board of the present invention. The present embodiment is formed in the circuit board of the second embodiment. The conductive vias of the electrical layer 20 are micro, and the conductive vias 222, C., the second dielectric layer 23, or the plugs are referred to the first embodiment. U example * is intended to be the fourth embodiment of the circuit board of the present invention; in the case of two / two, the line - 24 'the circuit board. The circuit board 24 has a plurality of electrical phases. Connecting the 塾241, and the first electrical connection 241 is formed in the first dielectric layer 20 in the first month of the first circuit board 20 in combination with the circuit board of the first embodiment. For the conductive blind vias I electrically connected to the connection 241 and the circuit layer 221, reference may be made to the first embodiment. Stupid only the present invention is a circuit board comprising: a first number; a plurality of slotted I circuit layers 221 having a plurality of side walls: ΓΓ and eight vertical lines 221 & amps are provided at each of the slots 2° The bauxite, and the second dielectric layer 23 are disposed in a gap between each of the vertical lines 221a of the openings. In addition, the 2G layer of the household layer is a material of a sense or non-photosensitive material; and the second dielectric layer 23 is the same or different, and the layer 23 of the line sound 221 may also be provided. The width of the 'distal slot 2' on the first dielectric layer 2〇9 is at least three times wider than the width of the vertical lines 111010 12 1376988 22la. The vertical line 221 Μ "page is exposed to the first dielectric surface" and the vertical lines 221a # 弋 弋 兑 go to the bottom of the table of θ. The wire I layer 221 has a plurality of connecting portions 221b disposed on the surface of the first dielectric layer, and the connecting portions 2m are electrically connected to the connecting line The connecting portion 221b may be completely disposed on the upper surface of the second hanging ridge, or may be buried in the first dielectric layer 2" and may be 2: H20 wide surface, or may be partially embedded in The first dielectric layer is partially disposed on the surface of the first dielectric layer 20. The circuit board includes at least one through the first dielectric 'electric via 222, and the conductive device is 丨000丄(The hole 222 can be filled with the metal layer 22, and the tracer can be filled with the second material in the electric through hole 222 (not shown in the figure). The h layer 23 or the plug hole ^ the circuit board Including the layered structure (the figure does not show the C-thinking layer 20 and the circuit layer 221. Or, the eighth, the second layer of the electric layer 20, a product of the A " Haidi one set...: The plurality of slots are formed on the other surface, and the second surface of the circuit board 24 is provided with a plurality of electrical connections in the first dielectric layer 20. Electrical layer 2 0 is provided with a blind hole state (four) 24] and a conductive layer 223 of the circuit layer (2). Then, the other dielectric layer is combined with the first dielectric; 2V: ... 5 circuit board 24 is formed into two Fine: The second returning circuit board uses a low-cost laser device or exposure development J3 (1) 0H) due to the wider sidewall shape of the slotted slot. The I376988 is also equipped with a side wall of the slot. The slotted center is shaped such that the width of the vertical line matches the film thickness of the coating, and the width of the vertical line is controlled by plating or plating time, and is not caused by the width of the field as in the prior art. Control; therefore, the present invention effectively completes the pattern of ultra-fine lines (e.g., less than 1-0./im) and overcomes the disadvantages of the prior art. The above embodiments are used to illustrate the principles of the present invention and its power-effects. The present invention may be modified without departing from the spirit and scope of the invention, and the scope of the present invention should be applied as described below. Patent paradigm listed. [Simple description of the diagram] 1A 1C is a schematic diagram of a conventional circuit board; 2A to 2C is a schematic diagram of another method of the conventional circuit board; and the 3E diagram is a schematic diagram of the first embodiment of the method for manufacturing the circuit board of the present invention.丨 Among them, the third (M Tudi
態樣之示意圖；第㈣至秦化/^2圖之不同實施 音同·笼奸，οη 5圖係為不同實施態樣之示 一望 及_2圖係為不同實施態樣之示竜圖； 為本發明之電路板之第二實施例之;音圖; 第5圖係為本發明之電路板之总 圖；以及 罘一貝轭例之示思 四實施例之示意圖。 第6圖係為本發明之電路板之第 【主要元件符號說明】 承載板 11、22 金屬層 Π1010 14 1376988 .111 、 221 12 120 、 200 -20 -21 221a 221b 222 #23 -24 -241 223 線路層 介電層 開槽 第一介電層 -導電層 垂直線路 連接部 導電通孔 第二介電層 線路板 電性連接墊 導電盲孔Schematic diagram of the pattern; the different implementations of the (4) to Qinhua/^2 diagrams are the same as the cages, and the οη 5 diagrams are shown in different implementations and the _2 diagrams are diagrams of different implementations; The second embodiment of the circuit board of the present invention; the sound map; the fifth drawing is a general view of the circuit board of the present invention; and the schematic view of the fourth embodiment of the first embodiment of the yoke. Figure 6 is the first part of the circuit board of the present invention. [Main component symbol description] Carrier plate 11, 22 Metal layer Π 1010 14 1376988 .111 , 221 12 120 , 200 -20 -21 221a 221b 222 #23 -24 -241 223 Circuit layer dielectric layer slotted first dielectric layer - conductive layer vertical line connection portion conductive via hole second dielectric layer circuit board electrical connection pad conductive blind hole