TW201019376A - Semiconductor wafer, electronic device and manufacturing method of semiconductor wafer - Google Patents

Semiconductor wafer, electronic device and manufacturing method of semiconductor wafer Download PDF

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TW201019376A
TW201019376A TW098133513A TW98133513A TW201019376A TW 201019376 A TW201019376 A TW 201019376A TW 098133513 A TW098133513 A TW 098133513A TW 98133513 A TW98133513 A TW 98133513A TW 201019376 A TW201019376 A TW 201019376A
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crystal
layer
compound semiconductor
wafer
seed
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TW098133513A
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Masahiko Hata
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Sumitomo Chemical Co
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Priority claimed from JP2008334830A external-priority patent/JP5543711B2/en
Priority claimed from JP2009046587A external-priority patent/JP2009239270A/en
Application filed by Sumitomo Chemical Co filed Critical Sumitomo Chemical Co
Publication of TW201019376A publication Critical patent/TW201019376A/en

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Abstract

A semiconductor wafer having a base wafer, an insulating layer, and a Si crystal layer in this order, and including a seed crystal provided on the Si crystal layer and annealed, and a chemical compound semiconductor lattice-matching or pseudomorphic deformed with the seed crystal is provided. Moreover, an electronic device including a substrate, an insulating layer provided on the substrate, a Si crystal layer provided on the insulating layer, a seed crystal provided on the Si crystal layer and annealed, a compound semiconductor lattice-matching or pseudomorphic deformed with the seed crystal, and a semiconductor device formed by using the chemical compound semiconductor is provided.

Description

201019376 六、發明說明： 【發明所屬之技術領域】 本發明係關於半導體晶圓（Semiconductor Wafer)、電 子裝置、及半導體晶圓之製造方法。本發明尤其關於使用 低價的S0I(Silicon On Insulator;絕緣體上矽薄膜）晶 圓，在絕緣膜上形成結晶性良好的化合物半導體結晶薄膜 之半導體晶圓、電子裝置、及半導體晶圓之製造方法。 【先前技術】 使用GaAs(砷化鎵）系等化合物半導體結晶之電子裝 置，有利用異質接面（heterojunction)之各種高功能電子 裝置開發出來。由於化合物半導體結晶的結晶性會左右電 子裝置的性能，因此要求要有良質的結晶薄膜。製造使用 GaAs系等化合物半導體結晶之電子裝置時，因為在異質界 面之晶格匹配（lattice matching)等的要求，所以使薄膜 在GaAs或晶格常數與GaAs極相近的Ge等之基底晶圓之上 結晶成長。 專利文獻1中記載有：在成長於晶格不匹配的晶圓或 差排（dislocation)缺陷密度大的晶圓之上的磊晶 (epitaxial)區域具有限定區域之半導體裝置。非專利文獻 1中s己載有·措由棱向轰晶過成長法（laterai epitaxial overgrowth)在以Ge(鍺）加以被覆的Si(矽）晶圓上成長成 的低差排密度GaAs磊晶層。非專利文獻£中記載有：在 Si晶圓上形成向品質的Ge磊晶成長層（以下，有時稱之為 Ge磊晶層）之技術。該技術係在si晶圓上限定區域而形成 4 321546 201019376 ' Ge磊晶層之後，對Ge磊晶層施行周期性熱退火處理，藉 、 此使Ge磊晶層的平均差排密度成為2. 3xl06cm:2。 [先前技術文獻] 〔專利文獻〕 專利文獻1 :日本特開平4-233720號公報 〔非專利文獻〕 非專利文獻 1:B. Y. Tsauret. al/Low-dislocation-density GaAs epilayers grown on Ge-coated Si © substrates by means of lateral epitaxial overgrowth」， Appl. Phys. Lett. 41(4)347-349, 15 August 1982. 非專利文獻 2 : Hsin-Chiao Luan et. al.「High-quality Ge epi layers on Si with low threading-dislocation densities」，APPLIED PHYSICS LETTERS, VOLUME 75, NUMBER 19, 8 NOVEMBER 1999. 【發明内容】 φ (發明所欲解決之課題）201019376 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor wafer (Semiconductor Wafer), an electronic device, and a method of manufacturing a semiconductor wafer. More particularly, the present invention relates to a semiconductor wafer, an electronic device, and a semiconductor wafer manufacturing method using a low-cost SOI (Silicon On Insulator) wafer to form a compound semiconductor crystal film having good crystallinity on an insulating film. . [Prior Art] Electronic devices using compound semiconductor crystals such as GaAs (gallium arsenide) have been developed using various high-performance electronic devices using heterojunctions. Since the crystallinity of the compound semiconductor crystal affects the performance of the electronic device, a favorable crystalline film is required. When manufacturing an electronic device using a compound semiconductor crystal such as GaAs or the like, it is required to have a lattice matching at a hetero interface, etc., so that the thin film is made of a GaAs or a base wafer such as Ge having a lattice constant close to that of the GaAs. Crystal growth. Patent Document 1 describes a semiconductor device having a limited region in an epitaxial region which is grown on a wafer having a lattice mismatch or a wafer having a large dislocation defect density. Non-Patent Document 1 has a low-difference-density GaAs epitaxial growth grown on a Si (矽) wafer coated with Ge (锗) by a gradient epitaxial overgrowth. Floor. A technique for forming a quality Ge epitaxial growth layer (hereinafter sometimes referred to as a Ge epitaxial layer) on a Si wafer is described in the non-patent literature. The technique is to perform periodic thermal annealing on the Ge epitaxial layer after forming a region on the Si wafer to form a 4321546 201019376 'Ge epitaxial layer, whereby the average difference density of the Ge epitaxial layer is 2. 3xl06cm: 2. [Prior Art Document] [Patent Document] Patent Document 1: Japanese Laid-Open Patent Publication No. Hei-4-233720 (Non-Patent Document) Non-Patent Document 1: BY Tsauret. al/Low-dislocation-density GaAs epilayers grown on Ge-coated Si © Included by means of lateral epitaxial overgrowth, Appl. Phys. Lett. 41(4)347-349, 15 August 1982. Non-Patent Document 2: Hsin-Chiao Luan et. al. "High-quality Ge epi layers on Si with Low threading-dislocation densities", APPLIED PHYSICS LETTERS, VOLUME 75, NUMBER 19, 8 NOVEMBER 1999. [Summary of the Invention] φ (The subject to be solved by the invention)

GaAs系的電子裝置，以在GaAs晶圓、或Ge晶圓等之 可使之與GaAs晶格匹配的晶圓上形成為佳。然而，GaAs 晶圓或Ge晶圓等之可與GaAs晶格匹配的晶圓很貴。而且， 此等晶圓的散熱特性不充分，為了進行有餘裕的熱設計就 必須抑制裝置（device)的形成密度。因此，希望得到一種 使用低價的Si晶圓而形成之具有GaAs系等化合物半導體 的結晶薄膜之良質的半導體晶圓。此外，還希望得到一種 可實現藉由GaAs系的電子裝置而進行的高速開關 321546 201019376 (switching)之半導體晶圓。 (解決課題之手段） > 為了解決上述課題，在本發明的第一形態中，提供以 基底晶圓、絕緣層、Si結晶層這樣的順序具有該基底晶圓、 絕緣層及Si結晶層，且具備有設於Si結晶層上並經過退 火處理之種子結晶、以及與種子結晶晶格匹配（lattice match)或準晶格匹配（quasi-lattice match或擬格子匹配 pseudo lattice matching)的化合物半導體之半導體晶 圓。種子結晶為不會因為在退火處理中產生的熱應力而發 ❹ 生缺陷之大小。種子結晶之與化合物半導體的界面，接受 以氣體之P(磷）化合物進行之表面處理。化合物半導體係 為III-V族化合物半導體或II-VI族化合物半導體。化合 物半導體為III-V族化合物半導體時，作為III族元素者 可包含A1 (鋁）、Ga(鎵）、In(銦）中之至少一者，作為V族 元素者可包含N(氮）、P(磷）、As(砷）、Sb(銻）中之至少一 者。 ❹ 半導體晶圓可再具備阻礙化合物半導體的結晶成長之 阻礙層，阻礙層具有貫通至Si結晶層之開口，且將種子結 晶設在開口的内部。在上述半導體晶圓中，可將阻礙層形 成在Si結晶層上。此外，化合物半導體之包含於開口内的 部份可具有不到/2之深寬比（aspect ratio)。阻礙層亦 可藉由使Si結晶層之設有前述種子結晶之區域以外的區 域熱氧化而形成。 另外，化合物半導體可具有·在種子結晶上，結晶成 6 321546 201019376 長到比阻礙層的表面凸出之種子化合物半導體結晶、以及 4 以種子化合物半導體結晶為核而沿著阻礙層橫向成長之橫 向成長化合物半導體結晶。橫向成長化合物半導體結晶可 具有：以種子化合物半導體結晶為核而沿著阻礙層橫向成 長之第一化合物半導體結晶、以及以第一化合物半導體結 晶為核而沿著阻礙層朝向與第一化合物半導體結晶不同的 方向橫向成長之第二化合物半導體結晶。 另外，可將Si結晶層、種子結晶、及化合物半導體大 ® 致平行地形成於基底晶圓。該半導體晶圓可再具備：覆蓋 住Si結晶層的上表面，阻礙化合物半導體的結晶成長之阻 礙層。另外，亦可在Si結晶層上等間隔設置複數個種子結 晶。 半導體晶圓可再具備：捕捉種子結晶的内部產生的缺 陷之缺陷捕捉部，且種子結晶所包含的區域中的任意的點 到缺陷捕捉部的最大距離，比在退火處理中缺陷可移動的 _ 距離小。缺陷捕捉部可為種子結晶的界面或表面，化合物 半導體不與之晶格匹配或準晶格匹配之區域。 另外，種子結晶可包含結晶成長成的SixGenCOSxCl) 結晶或在500C以下之溫度結晶成長成的GaAs。化合物半 導體可包含由含有P(磷）之III-V族化合物半導體所構成 之緩衝層，且緩衝層與種子結晶晶格匹配或準晶格匹配。 半導體晶圓可再具備：設於Si結晶層之未為種子結晶 所覆蓋的部份之Si半導體裝置。可使基底晶圓為單結晶之 Si，然後將Si半導體裝置設在基底晶圓之未為種子結晶所 7 321546 201019376 覆蓋的部份。 另外，種子結晶的表面的差排密度（disl〇cati⑽ density)可在lxl〇Vcm2以下。Si結晶層之形成種子結晶的 面，可具有相對於從（1〇0)面、（11〇)面、（m)面、與（1〇〇) 面在結晶學上等效的面、與（11〇)面在結晶學上等效的面、 及與（111)面在結晶學上等效的面之中選出的任一個結晶 面傾斜-個角度之傾斜角（off angle)。傾斜角可為^以 上6°以下之角度。 另外，種子結晶的底面積可在丨咖2以 士 底面積亦可在_^以下。此外，種子結晶的底:= 在900 //m2以下。 — 另外，種子結晶的底面的最大寬度可在8〇#m以下。 種子結晶的底面的最大寬度亦可纟40_以下。. 另外’基底晶圓可具有：擁有相對於（1〇〇)面或與（1〇〇) 面在結晶學上等效的面傾斜—個角度的傾斜角（咐a n g i e ) 之主面’ 種子結晶的底面可為長方形，且長方形的一邊 與基底晶圓的<010>方向、<0-10>方向、<〇〇1>方向、及 <〇〇-1>方向之任—者實質地平行。此情況也___樣，傾斜角 可為2。以上6。以下之角度。 基底晶圓亦可具有：擁有相對於⑴丨）面或與(⑴）面 結晶學上等效的面傾斜—個角度的傾斜角之主面，且種 ^結晶的底面可為六角形，且六角形的—邊與基底晶圓的 <1~1〇>方向、C-HO〉方向、<(M1>方向、训七方向、<ι〇ι> 向、及<-101>方向之任一者實質地平行。此情況也一樣， 321546 8 201019376 傾斜角可為2 °以上6 °以下之角度。 4 另外，阻礙層的外形的最大寬度可在4250 //m以下。 阻礙層的外形的最大寬度亦可在400 /zm以下。 在本發明的第二形態中，提供具備有：基體 (substrate)、設於基體上的絕緣層、設於絕緣層上的Si 結晶層、設於Si結晶層上並經過退火處理的種子結晶、與 種子結晶晶格匹配或準晶格匹配的化合物半導體、以及使 用化合物半導體而形成的半導體裝置之電子裝置。 ❿ 電子裝置可再具備阻礙化合物半導體的結晶成長之阻 礙層，阻礙層具有貫通至Si結晶層之開口，且種子結晶設 在開口的内部，化合物半導體可具有：在種子結晶上結晶 成長到比阻礙層的表面凸出之種子化合物半導體結晶、以 及以種子化合物半導體結晶為核·而沿著阻礙層橫向成長之 橫向成長化合物半導體結晶。 在本發明的第三形態中，提供包含有：準備以基底晶 _ 圓、絕緣層、Si結晶層這樣的順序具有該基底晶圓、絕緣 層及Si結晶層之SOI晶圓的階段；使種子結晶在Si結晶 層上成長的階段；對種子結晶進行退火處理的階段；以及 使與種子結晶晶格匹配或準晶格匹配的化合物半導體結晶 成長的階段之半導體晶圓之製造方法。使種子結晶成長的 階段包含：在Si結晶層上設置阻礙化合物半導體的結晶成 長之阻礙層的階段、在阻礙層形成貫通至Si結晶層之開口 的階段、以及使種子結晶在開口的内部成長的階段。使種 子結晶成長的階段，係使複數個種子結晶等間隔成長。使 9 321546 201019376 種子結晶成長的階段，錢種子結晶絲到不會因為退火 處理所產生的熱應力而使得種子結晶發生缺陷之大小。進 行退火處理的階段，係以可使種子結晶中所含的缺陷移動 到種子結晶的外緣之溫度及時間進行。該製造方法亦可包 含有使進行退火處理的階段重複進行複數次的階段。可藉 由退火處理’使種子結晶的表面的差排密度在 以下。 半導體晶圓之製造方法，可再包含有：在使化合物半 導體結晶成長的階段之前進行，藉由使以結晶層之設有種 子結晶之區域以外的區域熱氧化，而設置阻礙化合物半導 體的結晶成長之阻礙層的階段。 【實施方式】 以下雖然透過發明的實施形態來說明本發明，但以 下的實施形態並非用來限定中請專職圍所載的發明者。 此外，並非實施形態中說明的特徵的組合的全部都是發明 的解決手段所必須者。 第1圖概略地顯不一實施形態之半導體晶圓10的斷面 之一例。如第i圖所示’半導體晶圓1〇具備有基底晶圓 12、絕緣層13、Si結晶層14、種子結晶16、及化合物 導體18。 在半導體晶圓10的至少一部份，基底晶圓12'絕緣 層13 Si、.、。曰曰層14及種子結晶16依序在與基底晶圓 的主面11大致垂直的方向配置。如此，絕緣層13使基底 晶圓12與Si結晶層14絕緣，就可抑制漏電流（μ 321546 201019376 wt则基底日日日圓12。本說明書中，所謂的「大致垂 直的方向」’並不皁指很嚴密的垂直的方向，也考慮 及各部件的製造誤差而包含偏離垂直而略微傾斜===圓 基底晶圓12的一個例子為矽晶圓。絕緣層13的二 例子為藉由使基底晶圓12的主面1丨氧化而形成之氧化p 層。Si結晶層14的一個例子為形成於絕緣層13上之^ = 晶矽層。基底晶圓12、絕緣層13及Si結晶層14 =結 市售的SOI晶圓。 ’、可為 Φ ❹ 種子結晶16及化合物半導體18，係藉由赠 機金屬化學氣相成纽）域由制 ^有 的職分子束成紐㈣ 以下之溫度形成的GaAs結晶。. 種子結晶16要接受退火處理。士 s -結晶層Η上之狀態接受退火處理。、;^ 不到電，較佳為8机以下接受退火處理。藉此，= 維持種子結晶16的表面的平坦性。另外，亦可使種子結晶 16在680。(：以上，較佳為7〇〇°c 〇曰日 就可減低種子結晶16的結晶缺陷的密度。 退火處理可進行複數次。例如，以800至90(TC之溫 度進行2至10分鐘’實施並未達到^的融點的溫度之高 溫退火處理後，以680至78(TC之溫度實施2至1〇分鐘之 低溫退火處理。藉由料退火處理総低鮮結晶16的内 部的缺陷密度。 321546 11 201019376 ^匕外亦可使種子結晶16在大氣環境下、氮氣環境 下：環境τ、錢氣魏下接受退火處理。尤其，在 匕3氫氣之％&氣氛中對種子結晶16進行退火處理，可使 晶16的表面狀態_平滑驗態，㈣減低種子結 曰曰16的結晶缺陷的密度。 本說明書中，所謂的「準晶格匹配」，係指··可在雖缺 2完全的晶格匹配，但是相接的兩種半導體的晶格常數 =恨小’因晶格不匹配而發生缺陷的情形不顯著的範 圍，使相接的兩種半導體層積之狀態。此時，各半導體的 晶格會在可彈性變形的範圍内變形，而吸收上述晶格常數 的差。例如，Ge與GaAs、或Ge與InGaP(磷化銦嫁）在晶 格緩和界限厚度内之層積狀態，即稱為準晶格匹配。 化合物半導冑18，係與經過退火處理的種子結晶16 晶袼匹配或準晶格匹配。化合物半導體18係以種子結晶 ^為核而結晶成長。使祕過退火處理的種子結晶16,可 得到結晶性良好的化合物半導體18。化合物半導體18係 為例如ιιι-ν族化合物半導體或π_νι族化合物半導體。 化。物半導豸18 4 Ili-v族化合物半導體時，化合物半導 體18包含的111族元素可為A卜Ga、In中之至少一者， 包含的V族元素可為N、p、As、Sb中之至少一者。 作為-個例子’絕緣層13的面積比基底晶圓12的面 積小。另夕卜’作為一個例子，Si '结晶層14的面積比絕緣 層13的面積小。又，作為一個例子，種子結晶16及化合 物半導體18的面積比Si結晶層14的面積小。在本實施形 321546 12 201019376 態中，雖針對種子社曰 圓12的主面11α'7ΘΘ 16及化合物半導體18在與基底晶 明，惟種子结曰曰16敎垂直的方向並排而配置之情況進行說 12的主面致1及化合物半導體18亦可在與基底晶圓 士奋吵”行的方向並排而配置。 本貝％形態中，雜^ 雖針對基底晶圓12與絕緣層13相接 之情況進行說明’惟基底晶圓12與絕緣層13的位置關係， 並不限定於兩者相接之關係。亦可在基底晶圓丨2與絕緣層 13之間形成其他的層。另外，在本實施形態中，雖針對s i _結晶層14與種子結晶16相接之情況進行說明，惟si結晶 層14與種子結晶16的位置關係，並不限定於兩者相接之 關係。亦可在Si結晶層14與種子結晶16之間形成其他的 層。此外，種子結晶16及化合物半導體18亦可各由複數 層結晶層所形成。 第2圖概略地顯示半導體晶圓20的斷面之一例。如第 2圖所不’半導體晶圓20在其至少一部份，具備有在與基 底晶圓12的主面11大致垂直的方向依序為基底晶圓a、 絕緣層13、Si結晶層14、及阻礙層25之部件。另外，半 導體晶圓20還具備有種子結晶26及化合物半導體28。 阻礙層25形成於Si結晶層14上。阻礙層25至少阻 礙化合物半導體28的結晶成長。阻礙層25亦可也阻礙種 子結晶26的結晶成長。阻礙層25形成有在與基底晶圓12 之一侧的主面11大致垂直的方向從阻礙層25的表面到si 結晶層14而貫通阻礙層25之開口 27。 如此’結晶便不會在阻礙層25的表面成長，結晶會選 321546 13 201019376 擇性地在開Π 27的㈣絲。作為—_子，阻礙 的面積比Si結晶層Η的面積小。阻礙層25可為^ 氧化矽W吏用例如⑽(化學氣相成長)法而形成。開二 可藉由光刻（photol ithography)法來形成。 種子結晶26及化合物半導體28等同於第丨圖中之 子結晶16及化合物半導體18。因此，在以下的說明中， 會有將關於同等部件的重複說明予以省略之情形；種子結 晶26係設於開口 27的内部。例如，種子結晶％設於= 27的底面。 如上所述，種子結晶26要接受退火處理。藉此，減低 種子結晶16的内部的缺陷密度。化合物半導體28，係與 種子結晶2 6晶格匹配或準晶格匹配。使用經過退火處理的 種子結晶26，可得到結晶性良好的化合物半導體28。 第3圖概略地顯示半導體晶圓3〇的斷面之一例。如第 3圖所示，半導體晶圓3〇具備有基底晶圓12、絕緣層a、The GaAs-based electronic device is preferably formed on a wafer which can be lattice-matched to GaAs on a GaAs wafer or a Ge wafer. However, wafers that can be lattice matched to GaAs, such as GaAs wafers or Ge wafers, are expensive. Moreover, the heat dissipation characteristics of such wafers are insufficient, and it is necessary to suppress the formation density of devices in order to carry out a sufficient heat design. Therefore, it is desired to obtain a semiconductor wafer of a crystalline film having a compound semiconductor such as GaAs or the like which is formed using a low-cost Si wafer. Further, it is desired to obtain a semiconductor wafer capable of realizing a high-speed switch 321546 201019376 (switching) by a GaAs-based electronic device. (Means for Solving the Problem) In the first aspect of the present invention, the base wafer, the insulating layer, and the Si crystal layer are provided in the order of the base wafer, the insulating layer, and the Si crystal layer. And having a seed crystal which is disposed on the Si crystal layer and annealed, and a compound semiconductor which is lattice matching or quasi-lattice match or pseudo lattice matching. Semiconductor wafers. The seed crystallizes to a size that does not cause a defect due to thermal stress generated in the annealing treatment. The interface between the seed crystal and the compound semiconductor is subjected to surface treatment with a gas P (phosphorus) compound. The compound semiconductor is a III-V compound semiconductor or a II-VI compound semiconductor. When the compound semiconductor is a III-V compound semiconductor, at least one of A1 (aluminum), Ga (gallium), and In (indium) may be contained as a group III element, and N (nitrogen) may be contained as a group V element. At least one of P (phosphorus), As (arsenic), and Sb (锑).半导体 The semiconductor wafer may further include a barrier layer that hinders crystal growth of the compound semiconductor, the barrier layer having an opening penetrating into the Si crystal layer, and the seed crystal being crystallized inside the opening. In the above semiconductor wafer, a barrier layer may be formed on the Si crystal layer. Further, the portion of the compound semiconductor contained in the opening may have an aspect ratio of less than /2. The barrier layer can also be formed by thermally oxidizing a region other than the region in which the seed crystal is crystallized in the Si crystal layer. Further, the compound semiconductor may have a seed compound semiconductor crystal which is crystallized to 6321546 201019376 on the surface of the seed crystal, and a lateral growth of the seed compound semiconductor crystal as a core and a lateral growth along the barrier layer. Growth of compound semiconductor crystals. The laterally growing compound semiconductor crystal may have a first compound semiconductor crystal which grows laterally along the barrier layer with the seed compound semiconductor crystal as a core, and a crystal of the first compound semiconductor crystal as a core and crystallizes along the barrier layer toward the first compound semiconductor Crystallization of a second compound semiconductor that grows laterally in different directions. Further, the Si crystal layer, the seed crystal, and the compound semiconductor can be formed in parallel on the base wafer. The semiconductor wafer may further include a barrier layer covering the upper surface of the Si crystal layer and hindering the crystal growth of the compound semiconductor. Further, a plurality of seed crystals may be provided at equal intervals on the Si crystal layer. The semiconductor wafer may further include: a defect capturing portion that captures defects generated inside the seed crystal, and the maximum distance from any point in the region included in the seed crystal to the defect capturing portion is movable more than the defect in the annealing process The distance is small. The defect trapping portion may be an interface or surface where the seed crystallizes, a region where the compound semiconductor does not lattice match or pseudo-lattice matching. Further, the seed crystal may include a crystal grown into a crystal of SixGenCOSxCl) or a crystal grown by crystal growth at a temperature of 500 C or lower. The compound semiconductor may comprise a buffer layer composed of a III-V compound semiconductor containing P (phosphorus), and the buffer layer is lattice-matched or quasi-lattice-matched to the seed crystal. The semiconductor wafer may further include a Si semiconductor device provided in a portion of the Si crystal layer that is not covered by the seed crystal. The base wafer can be made into a single crystal Si, and then the Si semiconductor device is placed on the portion of the base wafer that is not covered by the seed crystal 7 321546 201019376. Further, the difference in discharge density (disl〇cati (10) density) of the surface of the seed crystal may be below lxl 〇 Vcm2. The surface of the Si crystal layer forming the seed crystal may have a crystallographically equivalent surface with respect to the (1〇0) plane, the (11〇) plane, the (m) plane, and the (1〇〇) plane, and The (11 Å) plane is inclined at an angle of an angle between the crystallographically equivalent surface and any crystal plane selected from the crystallographically equivalent plane of the (111) plane. The tilt angle can be an angle of 6 or less above. In addition, the bottom area of the seed crystal may be less than _^ in the base area of the coffee. In addition, the bottom of the seed crystal: = below 900 // m2. — In addition, the maximum width of the bottom surface of the seed crystal may be below 8〇#m. The maximum width of the bottom surface of the seed crystal may also be 纟40_ or less. In addition, the 'substrate wafer may have: a main surface' having a tilt angle (咐angie) that is crystallographically equivalent to the (1〇〇) plane or the (1〇〇) plane. The bottom surface of the crystal may be a rectangle, and one side of the rectangle and the <010> direction, <0-10> direction, <〇〇1> direction, and <〇〇-1> direction of the base wafer are The people are substantially parallel. This case is also ___, and the tilt angle can be 2. Above 6. The following angles. The base wafer may also have a main surface having an inclination angle of an angle which is crystallographically equivalent to the (1) 丨 plane or the ((1)) plane, and the bottom surface of the crystal may be hexagonal, and Hexagon-side and base wafer <1~1〇> direction, C-HO> direction, <(M1> direction, training direction, <ι〇ι> direction, and <-101&gt The direction is substantially parallel. The same is true for this case. 321546 8 201019376 The inclination angle can be an angle of 2 ° or more and 6 ° or less. 4 In addition, the maximum width of the shape of the barrier layer can be 4250 //m or less. The maximum width of the outer shape of the layer may be 400 / zm or less. In the second aspect of the present invention, the substrate is provided with a substrate, an insulating layer provided on the substrate, and a Si crystal layer provided on the insulating layer. a seed crystal which is provided on the Si crystal layer and which is annealed, a compound semiconductor which is lattice-matched or quasi-lattice-matched with the seed crystal, and an electronic device which is formed using a compound semiconductor. ❿ The electronic device can further have a hindrance compound The growth of semiconductor crystal growth a layer, the barrier layer has an opening penetrating into the Si crystal layer, and the seed crystal is disposed inside the opening, and the compound semiconductor may have a seed compound semiconductor crystal which grows on the seed crystal to grow on the surface of the barrier layer, and a seed In the third aspect of the present invention, the compound semiconductor crystal is a core and grows laterally along the barrier layer. In the third aspect of the present invention, it is provided that the substrate crystal has a base crystal ring, an insulating layer, and an Si crystal layer. a stage of the base wafer, the insulating layer, and the SOI wafer of the Si crystal layer; a stage in which the seed crystal is grown on the Si crystal layer; a stage of annealing the seed crystal; and a crystal lattice matching or quasicrystal to the seed crystal A method of producing a semiconductor wafer in a stage in which a compound semiconductor crystal is grown. The step of growing the seed crystal includes a step of providing a barrier layer for inhibiting crystal growth of the compound semiconductor on the Si crystal layer, and forming a barrier layer to penetrate into the Si layer. a stage of opening of the crystal layer, and a step of growing the seed crystal inside the opening In the stage of crystal growth of seeds, a plurality of seeds are crystallized at equal intervals to grow. In the stage of crystal growth of 9 321 546 201019376 seeds, the crystals of the seeds are crystallized to prevent defects in seed crystals due to thermal stress generated by annealing treatment. The size of the annealing treatment is performed by moving the defects contained in the seed crystals to the temperature and time of the outer edge of the seed crystal. The manufacturing method may also include repeating the annealing step. The step of annealing the surface of the seed crystal by the annealing treatment may be as follows. The method for fabricating a semiconductor wafer may further include: performing a crystal layer before the stage of crystal growth of the compound semiconductor The region other than the region in which the seed crystal is crystallized is thermally oxidized, and a step of hindering the retardation layer of crystal growth of the compound semiconductor is provided. [Embodiment] Hereinafter, the present invention will be described by way of embodiments of the invention, but the following embodiments are not intended to limit the inventors of the present invention. Further, not all combinations of the features described in the embodiments are essential to the means for solving the invention. Fig. 1 schematically shows an example of a cross section of a semiconductor wafer 10 of an embodiment. As shown in Fig. i, the semiconductor wafer 1 includes a base wafer 12, an insulating layer 13, an Si crystal layer 14, a seed crystal 16, and a compound conductor 18. At least a portion of the semiconductor wafer 10, the base wafer 12' insulating layer 13 Si, . The germanium layer 14 and the seed crystal 16 are sequentially arranged in a direction substantially perpendicular to the principal surface 11 of the base wafer. As described above, the insulating layer 13 insulates the base wafer 12 from the Si crystal layer 14 to suppress leakage current (μ 321546 201019376 wt, the base day and the sun circle 12). In the present specification, the so-called "substantially perpendicular direction" does not soap. Refers to a very strict vertical direction, taking into account the manufacturing tolerances of the components and including a slight tilt from the vertical direction. === One example of the circular base wafer 12 is a tantalum wafer. Two examples of the insulating layer 13 are by making the substrate An oxide p-layer formed by oxidizing the main surface 1 of the wafer 12. An example of the Si crystal layer 14 is a germanium layer formed on the insulating layer 13. The base wafer 12, the insulating layer 13, and the Si crystal layer 14 = SOI wafers sold at the end of the market. ', can be Φ ❹ seed crystal 16 and compound semiconductor 18, by the metal chemical vaporization of the metal, the domain is formed by the molecular beam into the new (four) temperature below Formed GaAs crystals. The seed crystal 16 is subjected to annealing treatment. The state of the s-crystal layer is annealed. , ; ^ Less than electricity, preferably 8 or less to be annealed. Thereby, the flatness of the surface of the seed crystal 16 is maintained. Alternatively, the seeds may be crystallized at 680. (: Above, preferably 7〇〇°c. The density of crystal defects of the seed crystal 16 can be reduced. The annealing treatment can be performed plural times. For example, at 800 to 90 (temperature of TC for 2 to 10 minutes) After performing a high-temperature annealing treatment at a temperature that does not reach the melting point of the ^, a low-temperature annealing treatment is performed at 680 to 78 (the temperature of TC for 2 to 1 minute). The defect density inside the low fresh crystal 16 is treated by the material annealing. 321546 11 201019376 ^The seed crystal 16 can also be subjected to annealing under atmospheric conditions and nitrogen atmosphere: environment τ, money gas, especially in the 匕3 hydrogen % & atmosphere Annealing treatment can make the surface state of the crystal 16 smooth, and (4) reduce the density of the crystal defects of the seed crucible 16. In the present specification, the so-called "quasi-lattice matching" means that Complete lattice matching, but the lattice constants of the two semiconductors that are connected to each other = hate small. The range in which defects occur due to lattice mismatch is not significant, and the state of the two semiconductor layers that are connected is combined. The lattice of each semiconductor will Deformation within the range of elastic deformation, and absorption of the difference in the above lattice constant. For example, Ge and GaAs, or Ge and InGaP (indium phosphide) are stacked in a lattice relaxation limit thickness, which is called a quasi-lattice lattice. The compound semi-conducting yttrium 18 is matched or quasi-lattice-matched with the annealed seed crystal. The compound semiconductor 18 crystallizes with the seed crystal as the nucleus, crystallizing the seed after the annealing treatment, A compound semiconductor 18 having good crystallinity can be obtained. The compound semiconductor 18 is, for example, an ιιι-ν group compound semiconductor or a π_νι group compound semiconductor. When the compound semiconductor 18 semiconductor group semiconductor, the compound semiconductor 18 contains 111 The family element may be at least one of A, Ga, and In, and the included group V element may be at least one of N, p, As, and Sb. As an example, the area of the insulating layer 13 is larger than the base wafer 12 The area is small. As an example, the area of the Si 'crystal layer 14 is smaller than the area of the insulating layer 13. Further, as an example, the area of the seed crystal 16 and the compound semiconductor 18 is larger than that of the Si crystal layer 14. In the present embodiment, in the state of 321546 12 201019376, the main faces 11α'7ΘΘ 16 and the compound semiconductor 18 for the seed circle 12 are arranged side by side in the direction perpendicular to the base crystal, but the seed knots are 16 inches. In this case, the main surface 1 and the compound semiconductor 18 of FIG. 12 may be arranged side by side in the direction of the base wafer. In the present embodiment, the impurity is applied to the base wafer 12 and the insulating layer 13 In the case of the contact, the positional relationship between the base wafer 12 and the insulating layer 13 is not limited to the relationship between the two, and another layer may be formed between the base wafer cassette 2 and the insulating layer 13. Further, in the present embodiment, the case where the s i - crystal layer 14 is in contact with the seed crystal 16 will be described. However, the positional relationship between the si crystal layer 14 and the seed crystal 16 is not limited to the relationship between the two. Other layers may also be formed between the Si crystal layer 14 and the seed crystals 16. Further, the seed crystal 16 and the compound semiconductor 18 may each be formed of a plurality of crystal layers. FIG. 2 schematically shows an example of a cross section of the semiconductor wafer 20. As shown in FIG. 2, the semiconductor wafer 20 is provided with a base wafer a, an insulating layer 13, and a Si crystal layer 14 in a direction substantially perpendicular to the main surface 11 of the base wafer 12 in at least a portion thereof. And the components of the barrier layer 25. Further, the semiconductor wafer 20 is further provided with a seed crystal 26 and a compound semiconductor 28. The barrier layer 25 is formed on the Si crystal layer 14. The barrier layer 25 at least hinders the crystal growth of the compound semiconductor 28. The barrier layer 25 may also hinder the crystal growth of the seed crystals 26. The barrier layer 25 is formed with an opening 27 penetrating the barrier layer 25 from the surface of the barrier layer 25 to the si crystal layer 14 in a direction substantially perpendicular to the principal surface 11 on one side of the base wafer 12. Thus, the crystallization will not grow on the surface of the barrier layer 25, and the crystallization will be selected 321546 13 201019376 selectively in the opening of the (four) wire. As the -_ sub, the area of the hindrance is smaller than the area of the Si crystal layer. The barrier layer 25 may be formed of, for example, a (10) (chemical vapor phase growth) method. The second can be formed by photolithography. The seed crystal 26 and the compound semiconductor 28 are equivalent to the sub-crystal 16 and the compound semiconductor 18 in the figure. Therefore, in the following description, a repetitive description of the equivalent members will be omitted; the seed crystal 26 is provided inside the opening 27. For example, the seed crystal % is set at the bottom surface of = 27. As described above, the seed crystals 26 are subjected to an annealing treatment. Thereby, the defect density inside the seed crystal 16 is reduced. The compound semiconductor 28 is lattice matched or quasi-lattice matched to the seed crystal. Using the annealed seed crystal 26, a compound semiconductor 28 having good crystallinity can be obtained. Fig. 3 schematically shows an example of a cross section of a semiconductor wafer 3A. As shown in FIG. 3, the semiconductor wafer 3 is provided with a base wafer 12, an insulating layer a,

Si結晶層34、種子結晶36及化合物半導體38。Si結晶層 34、種子結晶36及化合物半導體38等同於第丨圖中之Si 結晶層14、種子結晶16及化合物半導體18。因此，在以 下的說明中，會有將關於同等部件的重複說明予以省略之 情形。 半導體晶圓30 ’在Si結晶層34、種子結晶36及化合 物半導體38係於與基底晶圓丨2的主面11大致平行的方向 並排而配置之點，與半導體晶圓1〇不同。Si結晶層34、 種子結晶36及化合物半導體38係沿著絕緣層13的表面 14 321546 201019376 19而依序配置。換言之，種子結晶36係設在Si結晶層34 ' 與化合物半導體38之間。Si crystal layer 34, seed crystal 36, and compound semiconductor 38. The Si crystal layer 34, the seed crystal 36, and the compound semiconductor 38 are equivalent to the Si crystal layer 14, the seed crystal 16 and the compound semiconductor 18 in the figure. Therefore, in the following description, a repetitive description of equivalent components will be omitted. The semiconductor wafer 30' differs from the semiconductor wafer 1 in that the Si crystal layer 34, the seed crystal 36, and the compound semiconductor 38 are arranged side by side in a direction substantially parallel to the main surface 11 of the base wafer cassette 2. The Si crystal layer 34, the seed crystal 36, and the compound semiconductor 38 are sequentially disposed along the surface 14 321546 201019376 19 of the insulating layer 13. In other words, the seed crystal 36 is provided between the Si crystal layer 34' and the compound semiconductor 38.

Si結晶層34的面積、種子結晶36的面積、及化合物 半導體38的面積，都比絕緣層13的面積小。本實施形態 中，雖針對種子結晶36及化合物半導體38在與基底晶圓 12的主面11大致平行的方向並排而配置之情況進行說 明，惟在其他例子中，種子結晶36及化合物半導體38亦 可在與基底晶圓12的主面11大致垂直的方向並排而配 ⑩ 置。本說明書中，所謂的「大致平行的方向」，並不單指很 嚴密的平行的方向，也考慮到晶圓及各部件的製造誤差而 包含偏離平行而略微傾斜之方向。 第4圖概略地顯示半導體晶圓40的斷面之一例。如第 4圖所示，半導體晶圓40具備有基底晶圓12、絕緣層13、 Si結晶層44、阻礙層45、種子結晶46及化合物半導體48。 Si結晶層44、種子結晶46及化合物半導體48等同於第3 ©圖中之Si結晶層34、種子結晶36及化合物半導體38。阻 礙層45等同於第2圖中之阻礙層25。因此，在以下的說 明中，會有將關於同等部件的重複說明予以省略之情形。 半導體晶圓40，在還具備有覆蓋住Si結晶層44的上 表面43之阻礙層45的點，與半導體晶圓30不同。Si結 晶層44的上表面43，係Si結晶層44之與基底晶圓12的 主面11大致平行的面中，離基底晶圓12較遠的那一面。 阻礙層45會阻礙化合物半導體48及種子結晶46的結晶成 長。 15 321546 201019376 如此，種子結晶46就會選擇性地以Si結晶層44之與 基底晶圓12的主面11大致垂直的側面41為核而成長。結 果，種子結晶46的結晶性就會提高。另外，絕緣層13 ^ 包含阻礙結晶成長的材料。絕緣層13的—個例子為。 半導體晶圓40可按以下所述的程序而製作。首先，準 備具備有基底晶圓12、絕緣層13及Si結晶層之go〗晶圓。 然後，藉由蝕刻等使S 〇 I晶圓的S i結晶層圖案化，而Μ形成 矩形的si結晶層。然後，以覆蓋矩形的Si結晶層的面中 與基底晶圓12的主φ 11大致平行的面之方式，形成阻礙 層45。阻礙層45可具有與矩形的Si結晶層一樣的形狀。 以例如CVD法生成Si〇2，藉此來形成阻礙層。然後，藉 由蝕刻矩形的Si結晶層來形成Si結晶層44。因為蝕刻形 成的Si結晶層44比阻礙層45小，所以阻礙層45與絕緣 層13之間會出現空間。 其次，選擇性地使種子結晶46在Si結晶層44之與基 底晶圓12的主面π大致垂直的面41成長。種子結晶46 係藉由例如Μ0ΠΦ法而形成。接著，對種子結晶46進行退 火處理。藉由讓種子結晶46接受退火處理，而提高種子結 晶46的結晶性。然後，形成與種子結晶46晶格匹配或準 曰曰格匹配之化合物半導體48。化合物半導體48係藉由例 如CVD法而形成。 第5圖顯示電子裝置的平面例。第6圖顯示第5 圖中之A A線斷面。第7圖顯示顯示第5圖中之b_b線斷 面。電子裝置100具備有S0I晶圓102、阻礙層104、Ge 321546 16 201019376 .結晶層106、種子化合物半導體結晶108、第一化合物半導 體結晶110、第二化合物半導體結晶112、開極絕緣膜⑴、 閘極電極116、以及源極/沒極電極118。The area of the Si crystal layer 34, the area of the seed crystal 36, and the area of the compound semiconductor 38 are both smaller than the area of the insulating layer 13. In the present embodiment, the seed crystal 36 and the compound semiconductor 38 are arranged side by side in a direction substantially parallel to the main surface 11 of the base wafer 12. However, in other examples, the seed crystal 36 and the compound semiconductor 38 are also arranged. 10 can be arranged side by side in a direction substantially perpendicular to the main surface 11 of the base wafer 12. In the present specification, the term "substantially parallel direction" does not mean a very strict parallel direction, but also includes a direction in which the wafer and each component are manufactured with a slight deviation from the parallel direction. Fig. 4 schematically shows an example of a cross section of the semiconductor wafer 40. As shown in Fig. 4, the semiconductor wafer 40 includes a base wafer 12, an insulating layer 13, a Si crystal layer 44, a barrier layer 45, a seed crystal 46, and a compound semiconductor 48. The Si crystal layer 44, the seed crystal 46, and the compound semiconductor 48 are equivalent to the Si crystal layer 34, the seed crystal 36, and the compound semiconductor 38 in the third drawing. The barrier layer 45 is equivalent to the barrier layer 25 in Fig. 2. Therefore, in the following description, a repetitive description of equivalent components will be omitted. The semiconductor wafer 40 is different from the semiconductor wafer 30 in that it further includes a barrier layer 45 covering the upper surface 43 of the Si crystal layer 44. The upper surface 43 of the Si junction layer 44 is the side of the Si crystal layer 44 that is substantially parallel to the main surface 11 of the base wafer 12, which is farther from the base wafer 12. The barrier layer 45 hinders the crystallization of the compound semiconductor 48 and the seed crystal 46. 15 321546 201019376 Thus, the seed crystal 46 is selectively grown with the side surface 41 of the Si crystal layer 44 substantially perpendicular to the major surface 11 of the base wafer 12 as a core. As a result, the crystallinity of the seed crystal 46 is improved. In addition, the insulating layer 13^ contains a material that hinders crystal growth. An example of the insulating layer 13 is. The semiconductor wafer 40 can be fabricated in accordance with the procedures described below. First, a wafer having a base wafer 12, an insulating layer 13, and a Si crystal layer is prepared. Then, the Si crystal layer of the S 〇 I wafer is patterned by etching or the like to form a rectangular si crystal layer. Then, the barrier layer 45 is formed so as to cover a surface of the Si crystal layer of the rectangular shape which is substantially parallel to the main φ 11 of the base wafer 12. The barrier layer 45 may have the same shape as the rectangular Si crystal layer. Si 2 is formed by, for example, a CVD method, whereby a barrier layer is formed. Then, the Si crystal layer 44 is formed by etching a rectangular Si crystal layer. Since the Si crystal layer 44 formed by etching is smaller than the barrier layer 45, a space may occur between the barrier layer 45 and the insulating layer 13. Next, the seed crystal 46 is selectively grown on the surface 41 of the Si crystal layer 44 which is substantially perpendicular to the principal surface π of the base wafer 12. The seed crystal 46 is formed by, for example, the Π0ΠΦ method. Next, the seed crystals 46 are subjected to annealing treatment. The crystallinity of the seed crystals 46 is improved by subjecting the seed crystals 46 to annealing treatment. Then, a compound semiconductor 48 which is lattice-matched or quasi-pegically matched to the seed crystal 46 is formed. The compound semiconductor 48 is formed by, for example, a CVD method. Fig. 5 shows a plane example of an electronic device. Figure 6 shows the A A line section in Figure 5. Figure 7 shows the b_b line cross-section in Figure 5. The electronic device 100 includes an SOI wafer 102, a barrier layer 104, Ge 321546 16 201019376, a crystal layer 106, a seed compound semiconductor crystal 108, a first compound semiconductor crystal 110, a second compound semiconductor crystal 112, an open insulating film (1), and a gate. The pole electrode 116 and the source/nopole electrode 118.

Ge結晶層1〇6等同於種子結晶16、種子結晶邡、種 子結晶36或種子結晶46。種子化合物半導體結晶1〇8、第 一化合物半導體結晶110、及第二化合物半導體結晶112 各自等同於化合物半導體18、化合物半導體28、化合物半 導體38、及化合物半導體48。因此，在以下的說明中，會 ❹有將關於同等部件的重複說明予以省略之情形。 本例中’使種子化合物半導體結晶1〇8以設於開口 1〇5 之Ge結晶層1〇6為核而成長到從開口 1〇5突出。然後，使 第一化合物半導體結晶11〇以種子化合物半導體結晶1〇8 為核而在阻礙層1〇4的表面上之第一方向成長。然後，使 第二化合物半導體結晶112以第一化合物半導體結晶110 為核而在阻礙層1〇4的表面上之第二方向成長。第一方向 ❹及弟一方向係為例如互相正交的方向。 電子裝置100可包含複數個MISFET(Meta卜Insulator -Semiconductoi* Field-Effect Transistor;金屬絕緣體 半導體場效電晶體）或 HEMT(Hi gh-El ectron-Mobi 1 i ty Transistor;高電子移動率電晶體）。 SOI晶圓1〇2在其至少一部份，以si晶圓162、絕緣 層164、Si結晶層166這樣的順序具有該Si晶圓162、絕 緣層164及Si結晶層166。SOI晶圓102在Si晶圓162的 主面172之一側，具有絕緣層164及Si結晶層166。Si晶 17 321546 201019376 圓162可為單結晶Si晶圓。Si晶圓162具有作為電子裝 置100的基體（substrate)之功能。 絕緣層164使Si晶圓162及Si結晶層166電性絕緣。 絕緣層164係與Si晶圓162的主面172相接而形成。'以 結晶層166可包含Si的單結晶。Si結晶層166係與絕緣 層164相接而形成。Si晶圓162及絕緣層164等同於基底 晶圓12及絕緣層13。Si結晶層166等同於Si結晶層14、 Si結晶層34、或Si結晶層44。因此，在以下的說明中， 會有將關於同等部件的重複說明予以省略之情形。 在SOI晶圓102之上，形成作為主動元件之MISFET或 HEMT等。在S〇i晶圓102形成電子裝置1〇〇，藉此電子裝 置1〇〇的寄生電容（straycapacitance)會減低，因而電子 裝置100的動作速度會提高。此外，絕緣層164具有高絕 緣電阻，可抑制漏電流從電子裝置100流到Si晶圓162。 阻礙層104係在SOI晶圓102之主面172側，與Si結 晶層166相接而形成。阻礙層1〇4等同於阻礙層25或阻礙 層45。另外，阻礙層1〇4形成有在與Si晶圓162的主面 172大致垂直的方向貫通阻礙層1〇4之開口 1〇5。阻礙層 104阻礙種子化合物半導體結晶、第一化合物半導體結 晶110、及第二化合物半導體結晶112之結晶的磊晶成長。 開口 105在種子化合物半導體結晶1〇8尚未形成的狀 態下，使Si結晶層166露出。換言之，阻礙層1〇4形成有 從阻械層1 〇4的表面到以結晶層166之開口 1 。因此， 蠢晶膜會選擇性地在讓Si結晶層166露出的開d 1〇5成 321546 18 201019376 v長。Ge結晶層106會選擇性地在例如開口 105的内部結晶 成長。種子化合物半導體結晶108也會以Ge結晶層106為 核而選擇性地在開口 1〇5的内部結晶成長。另一方面，因 為在阻礙層1〇4的表面之結晶成長會受到阻礙，所以蟲晶 膜不會在阻礙層104的表面成長。阻礙層1〇4可包含氧化 梦或氮化梦。 本說明書中，所謂的「開口的深寬比（aspect ratio)」’係指將「開σ的深度」除以「開口的寬度」所得 到的值。例如，日本電子情報通信學會編「 信〜ho(手冊）第-分冊」請頁⑽8年月報；: —厶社（Ohmsha，Ltd.)發行）中，就有深寬比為（蝕刻深度/ 圖$寬度）之記載。本說明書中，亦基於同樣的意義而使用 深寬比之用語。而且，「開口的深度」係指，在晶圓上層積薄 膜之情況之在層積方向之開口的深度。「開口的寬 在與層積方向垂直的方向之開口的寬度。在開口的寬度並 ❹不-定之情況，「開口的寬度」係指開口的最小寬度。例如， 從層積方向所見之開口的形狀為長方形之情況，「開口的寬 度」係指長方形的短邊的長度。 在Ge結晶層106於開口 1〇5的内部結晶成長之情況， 「開口 105的深度」等於Ge結晶層1〇6的表面與阻礙層 104的表面之距離。另外，在種子化合物半導體結晶1〇8 以Ge結晶層106為核而選擇性地在開口 1〇5的内部結晶成 長之情況，「開口 105的深度」等於種子化合物半導體結晶 108包含在開口 105内的部份。此處’所謂的「種子ς = 321546 19 201019376 物半導體結晶m包含在開n 1Q5_部份」，係指從以 結晶層106的表面的高度到阻礙層104的表面的高度之種 子化合物半導體結晶108的垂直方向的寬度。因此，本說 明書中之「開〇 1〇5的深寬比」，係為「種子化合物半導體 結晶108包含在開口 1〇5内的部份的高度」除以「開口的 寬度」所得到的值。 在並不將形成於開口 1〇5内的Ge結晶層⑽加熱至 600至900 C左右之情況，舉例來說，開口 1〇5以具有 (/"3)/3以上的深寬比為佳。更具體言之，在開口】的的 底面之S!結晶層166的面方位為（1〇〇)之情況，開口服 可具有1以上的深寬比。在開口 1〇5的底面之si結晶層 I66的面方位為（111)之情況，開口 105可具有/*2(=約 1.414)以上的深寬比•開口 1〇5的底面之Si結晶層的 面方位為（11〇)之情況，開口 1〇5可具有（/_3)/3 約〇 以上的深寬比。 當將Ge結晶層1〇6形成於深寬比（,3)/3以上的開口 10 5的内σ卩時，Gp結晶層1 〇 6所含有的缺陷就會在開口 1 〇 5 的壁面被消滅掉。結果，並未為開口 105的壁面所覆蓋而 路出之Ge結晶層1〇6的表面之缺陷就會減低。亦即，在開 口 1〇5具有（yr3)/3以上的深寬比之情況，即使在並未對 形成於開口 1〇5内的Ge結晶層1〇6實施退火處理之狀態， 也可使在開口 1〇5内露出的Ge結晶層1〇6的表面的缺陷密 度小到預定的容許範圍。將開口 1〇5内露出的Ge結晶層 106的表面用作為種子化合物半導體結晶1〇8的結晶核， 321546 20 201019376 ，可提高種子化合物半導體結晶108的結晶性。 另外，在可將形成於開σ 1G5内的Ge結晶層⑽加熱 至600至90(TC左右而實施退火處理之情況，則開口 1〇5 的深寬比不到’2亦無妨。因為即使是開〇 1〇5的深寬比 不到/"2之情況’也可藉由實施退火處理而減低以結晶層 106的缺陷。更具體言之，在開口 1〇5的底面之si結晶層 =6的面方位為⑽）之情況，開σ 1〇5可具有不到丄之深 寬比。在開π 105的底面之^結晶層166的面方位為⑴^ 之& ;兄開口 105可具有不到/2( =約1.414)之深寬比。 開口 105的底面之Si結晶層166的面方位為（11〇)之情 況，開口 105可具有不到（，3)/3 (=約〇. 577)之深寬比。The Ge crystal layer 1〇6 is equivalent to the seed crystal 16, the seed crystal ruthenium, the seed crystal 36 or the seed crystal 46. The seed compound semiconductor crystal 1〇8, the first compound semiconductor crystal 110, and the second compound semiconductor crystal 112 are each equivalent to the compound semiconductor 18, the compound semiconductor 28, the compound semiconductor 38, and the compound semiconductor 48. Therefore, in the following description, a repetitive description of equivalent components will be omitted. In this example, the seed compound semiconductor crystal 1〇8 was grown to protrude from the opening 1〇5 by using the Ge crystal layer 1〇6 provided in the opening 1〇5 as a core. Then, the first compound semiconductor crystal 11〇 is grown in the first direction on the surface of the barrier layer 1〇4 with the seed compound semiconductor crystal 1〇8 as a core. Then, the second compound semiconductor crystal 112 is grown in the second direction on the surface of the barrier layer 1〇4 with the first compound semiconductor crystal 110 as a core. The first direction and the other direction are, for example, mutually orthogonal directions. The electronic device 100 may include a plurality of MISFETs (Metabu Insulator - Semiconductoi* Field-Effect Transistor) or HEMTs (Hi gh-Electron-Mobi Transitor; high electron mobility transistor) . The SOI wafer 1 2 has the Si wafer 162, the insulating layer 164, and the Si crystal layer 166 in the order of at least a portion of the Si wafer 162, the insulating layer 164, and the Si crystal layer 166. The SOI wafer 102 has an insulating layer 164 and an Si crystal layer 166 on one side of the main surface 172 of the Si wafer 162. Si crystal 17 321546 201019376 Round 162 can be a single crystal Si wafer. The Si wafer 162 has a function as a substrate of the electronic device 100. The insulating layer 164 electrically insulates the Si wafer 162 and the Si crystal layer 166. The insulating layer 164 is formed in contact with the main surface 172 of the Si wafer 162. The crystalline layer 166 may comprise a single crystal of Si. The Si crystal layer 166 is formed in contact with the insulating layer 164. The Si wafer 162 and the insulating layer 164 are equivalent to the base wafer 12 and the insulating layer 13. The Si crystal layer 166 is equivalent to the Si crystal layer 14, the Si crystal layer 34, or the Si crystal layer 44. Therefore, in the following description, a repetitive description of equivalent components will be omitted. On top of the SOI wafer 102, a MISFET or HEMT or the like as an active element is formed. When the electronic device 1 is formed on the S?i wafer 102, the parasitic capacitance of the electronic device 1 is reduced, and the operating speed of the electronic device 100 is improved. Further, the insulating layer 164 has a high insulating resistance, and it is possible to suppress leakage current from flowing from the electronic device 100 to the Si wafer 162. The barrier layer 104 is formed on the main surface 172 side of the SOI wafer 102 and is in contact with the Si crystal layer 166. The barrier layer 1〇4 is equivalent to the barrier layer 25 or the barrier layer 45. Further, the barrier layer 1〇4 is formed with an opening 1〇5 penetrating the barrier layer 1〇4 in a direction substantially perpendicular to the principal surface 172 of the Si wafer 162. The barrier layer 104 hinders the epitaxial growth of the seed compound semiconductor crystal, the first compound semiconductor crystal 110, and the second compound semiconductor crystal 112. The opening 105 exposes the Si crystal layer 166 in a state where the seed compound semiconductor crystal 1〇8 has not been formed. In other words, the barrier layer 1〇4 is formed from the surface of the barrier layer 1 〇4 to the opening 1 of the crystal layer 166. Therefore, the stupid film is selectively opened to make the Si crystal layer 166 open, d 1 〇 5 to 321546 18 201019376 v long. The Ge crystal layer 106 selectively crystallizes, for example, inside the opening 105. The seed compound semiconductor crystal 108 also selectively crystallizes and grows inside the opening 1〇5 with the Ge crystal layer 106 as a core. On the other hand, since the crystal growth on the surface of the barrier layer 1〇4 is hindered, the insect crystal film does not grow on the surface of the barrier layer 104. The barrier layer 1〇4 may contain an oxidative dream or a dream of nitriding. In the present specification, the "aspect ratio" of the opening means a value obtained by dividing the "depth of the σ" by the "width of the opening". For example, the Japanese Electronic Information and Communication Society compiled the "letter ~ ho (manual) section - volume" page (10) 8 years monthly report;: - issued by Ohmsha, Ltd.), the aspect ratio is (etching depth / map) The record of $width). In this specification, the term "aspect ratio" is also used based on the same meaning. Further, the "depth of the opening" means the depth of the opening in the stacking direction in the case where the film is laminated on the wafer. "The width of the opening is the width of the opening in the direction perpendicular to the stacking direction. The width of the opening refers to the minimum width of the opening when the width of the opening is not fixed. For example, when the shape of the opening seen from the lamination direction is a rectangle, the "width of the opening" means the length of the short side of the rectangle. In the case where the Ge crystal layer 106 grows crystallized inside the opening 1〇5, the "depth of the opening 105" is equal to the distance between the surface of the Ge crystal layer 1〇6 and the surface of the barrier layer 104. Further, in the case where the seed compound semiconductor crystal 1〇8 selectively crystallizes and grows inside the opening 1〇5 with the Ge crystal layer 106 as a core, the “depth of the opening 105” is equal to the seed compound semiconductor crystal 108 contained in the opening 105. Part of it. Here, the so-called "seed ς = 321546 19 201019376 The semiconductor crystal m is contained in the open n 1Q5_ portion" means the seed compound semiconductor crystal from the height of the surface of the crystal layer 106 to the height of the surface of the barrier layer 104. The width of the vertical direction of 108. Therefore, the "aspect ratio of opening 〇5" in the present specification is the value obtained by dividing the height of the portion of the seed compound semiconductor crystal 108 included in the opening 1〇5 by the width of the opening. . In the case where the Ge crystal layer (10) formed in the opening 1〇5 is not heated to about 600 to 900 C, for example, the opening 1〇5 has an aspect ratio of (/"3)/3 or more. good. More specifically, the surface orientation of the S! crystal layer 166 on the bottom surface of the opening is (1 Å), and the opening service may have an aspect ratio of 1 or more. In the case where the plane orientation of the Si crystal layer I66 on the bottom surface of the opening 1〇5 is (111), the opening 105 may have an aspect ratio of /*2 (=about 1.414) or more. • The Si crystal layer of the bottom surface of the opening 1〇5 In the case where the plane orientation is (11 〇), the opening 1 〇 5 may have an aspect ratio of (/_3) / 3 or more. When the Ge crystal layer 1〇6 is formed in the inner σ卩 of the opening 105 of the aspect ratio (3)/3 or more, the defects contained in the Gp crystal layer 1 〇6 are on the wall surface of the opening 1 〇5. Eliminate it. As a result, the defects of the surface of the Ge crystal layer 1〇6 which are not covered by the wall surface of the opening 105 are reduced. In other words, in the case where the opening 1〇5 has an aspect ratio of (yr3)/3 or more, even in a state in which the Ge crystal layer 1〇6 formed in the opening 1〇5 is not annealed, The defect density of the surface of the Ge crystal layer 1〇6 exposed in the opening 1〇5 is as small as a predetermined allowable range. The surface of the Ge crystal layer 106 exposed in the opening 1〇5 is used as the crystal nucleus of the seed compound semiconductor crystal 1〇8, 321546 20 201019376, and the crystallinity of the seed compound semiconductor crystal 108 can be improved. Further, when the Ge crystal layer (10) formed in the open σ 1G5 can be heated to about 600 to 90 (TC) and the annealing treatment is performed, the aspect ratio of the opening 1〇5 is not less than 2, because even if it is The aspect ratio of the opening 1〇5 is less than /"2', and the defect of the crystal layer 106 can be reduced by performing the annealing treatment. More specifically, the si crystal layer on the bottom surface of the opening 1〇5 In the case where the plane orientation of =6 is (10)), the opening σ 1〇5 may have an aspect ratio of less than 丄. The plane orientation of the crystal layer 166 on the bottom surface of the opening π 105 is (1)^ &; the brother opening 105 may have an aspect ratio of less than /2 (= about 1.414). In the case where the plane orientation of the Si crystal layer 166 of the bottom surface of the opening 105 is (11 Å), the opening 105 may have an aspect ratio of less than (3) / 3 (= about 577 577).

Ge、、O M層106可在使化合物半導體在Ge結晶層1〇6上結 晶成長之前接受退火處理。 2開口 105的底面積可在lmm2以下，較佳為不到〇. 25 随2 2。此情況’種子化合物半導體結晶1〇8的底面積也會為 ❹lmm以下或〇· 25则12。藉由使種子化合物半導體結晶1〇8的 尺寸在預定值以下，就可利用預定條件的退火處理，使種 子^ η物半導體結晶1 的任意點的缺陷移動到種子化合 物半導體結晶1〇8的端部。因此，可容易地減低種子化合 物半導體結晶1〇8的缺陷密度。 此外，開口 1〇5的底面積亦可在〇 〇lmm2以下，較佳為 1600 #m2以下，更佳為9〇〇#m2以下。此等情況，形成於開 口 105的内部之種子化合物半導體結晶108的底面積也會 為0.01mm2以下、16〇〇#m2以下、或9〇〇#m2以下。 21 321546 201019376 在種子化合物半導體結晶108及化合物半導體層等的 功能層、與SOI晶圓102的熱膨脹係數之差很大的情況， 熱退火處理容胃使功能層局部發生㈣。相對於此，上述 面積在O.Olimn2以下之情況，與上述面積比〇〇lmm2大之情 況相比較，可縮短形成於開口 1〇5的内部之以結晶層1〇6 的退火處理所需的時間。因此’使開π 1G5的底面積在 0.01mm2以下，可抑制功能層由於該翹曲而產生結晶缺陷之 情形。 開口⑽的底面積比16GMm2A之情況’無法充分抑 制，晶缺陷，所以很難獲得具有在裝置的製造上所必須的 預定特性之半導體晶圓。相對於此，開口 1〇5的底面積在 160=m以下之情況，結晶缺陷的數目會減低到預定值以 果就可利用形成於開口的内部之功能層來製造高 上述面積在__2以下之情況，則結晶缺陷 製造上述裝置。下的機革很间，所以能以很好的良率 :方面，開口 105的底面積以在25_2以上為佳。 “irt:5广時，在使_^ 的成長速度就會變得不财，而容易使 =的形狀產生纽。此外，當上述面積比m =:成的化合物半導體進行加工而難以形繼， 尤θ有良率降低之情形。 在〇 2 105的底面積相對於被覆區域的面積之比率，以 .。以上為佳。被覆區域係指Sl結晶層166之為阻礙 321546 22 201019376 ^層104所覆蓋之區域。當上述比率比0.01%小時，在開口 105的内部之結晶的成長速度就會變得不穩定。此外，在 -個被覆區域形成有複數個開口 1G5之情況，開〇 1〇5的 底面積係表示該被魏朗包含賴數㈣口 1[)5的底面 積的總和。 開口 105的底面形狀，可為最大寬度在私爪以下 者，較佳為80,以下者。開σ 1〇5的底面形狀的最大寬 度，係指將開口 105的底面形狀所包含的任意兩點連成的 各直線的長度之中，最大的長度。開口 1〇5為正方形或長 方形之情況’該底面形狀的—邊的長度可為⑽㈣以下， 較佳為80# m以下。上述底面形狀的最大寬度在丨⑽以瓜以 下之情況，與上述底面形狀的最大寬度比1〇〇#ra大之情況 相比較，可在短時間内完成對形成於開口 1〇5的内部之以 結晶層106的退火處理。 另外，Ge結晶層106可形成為：即使在受到因以結 ❿阳層106與Si結晶層166之在退火處理的溫度條件中之熱 膨脹係數的不同而產生的應力時，Ge結晶層1〇6中也不會 發生缺陷之大小。例如，與主面172大致平行的方向之以 結晶層106的最大寬度可為40am以下，較佳為2〇"m以 下。由於Ge結晶層106的最大寬度係依開口 1〇5的底面形 狀的最大寬度而定，所以開口 105的底面形狀較佳為具有 預定值以下的最大寬度。例如’開口 1〇5的底面形狀的最 大寬度可為40βιη以下，更佳為3〇#m以下。 可在一個阻礙層104形成一個開口 1〇5。藉此，可在 321546 23 201019376 開口 105的内部使結晶以穩定的成長速度磊晶成長。亦可 在一個阻礙層104形成複數個開口 105。此情況，以將 個開口 105等間隔配置者為佳。藉此，可在開口 的 部使結晶以穩定的成長速度磊晶成長。 、 開口 1〇5的底面形狀為多角形之情況，該多角形的 少一邊的方向’較佳為與_晶圓102的主面的結晶學： 面方位之一實質地平行之方向。開口 105的底面形狀： SOI晶圓102的主面的結晶學的面方位之關係較^ 使付在開口 105的内部成長結晶的側面成為安定的面^ 係。此處，所謂的「音暂_ 奇 / 丁」，係包含上述多角形的- 邊的方向'、晶圓的結晶學的面方位之—從相互平行 態略為偏斜之㈣。上述偏斜的^的―_ 下。藉此’就可抑制钍曰士、 句u 成具^ / 日日成長的^，使上述結晶穩定地 曰。 日日心易成長，可得到形狀整齊的種子結The Ge, O M layer 106 can be annealed before the compound semiconductor is crystallized on the Ge crystal layer 1〇6. The bottom area of the opening 105 may be less than 1 mm 2 , preferably less than 〇 25 随 2 2 . In this case, the bottom area of the seed compound semiconductor crystal 1〇8 is also ❹lmm or less or 〇·25. By making the size of the seed compound semiconductor crystal 1〇8 below a predetermined value, the defect at any point of the seed semiconductor crystal 1 can be moved to the end of the seed compound semiconductor crystal 1〇8 by annealing treatment under predetermined conditions. unit. Therefore, the defect density of the seed compound semiconductor crystal 1〇8 can be easily reduced. Further, the bottom area of the opening 1〇5 may be 〇1 mm 2 or less, preferably 1600 #m2 or less, more preferably 9 〇〇#m2 or less. In these cases, the seed compound semiconductor crystal 108 formed inside the opening 105 has a bottom area of 0.01 mm 2 or less, 16 Å #m2 or less, or 9 Å #m2 or less. 21 321546 201019376 In the case where the difference between the functional layer of the seed compound semiconductor crystal 108 and the compound semiconductor layer and the thermal expansion coefficient of the SOI wafer 102 is large, the thermal annealing treatment allows the stomach to locally occur in the functional layer (4). On the other hand, when the area is equal to or less than O.Olimn2, the annealing treatment for the crystal layer 1〇6 formed inside the opening 1〇5 can be shortened as compared with the case where the area ratio is larger than 〇〇lmm2. time. Therefore, the bottom area of the opening π 1G5 is 0.01 mm 2 or less, and the occurrence of crystal defects due to the warpage of the functional layer can be suppressed. The case where the bottom area of the opening (10) is larger than the case of 16 GMm2A is not sufficiently suppressed, and crystal defects are caused, so that it is difficult to obtain a semiconductor wafer having predetermined characteristics necessary for the manufacture of the device. On the other hand, when the bottom area of the opening 1〇5 is 160=m or less, the number of crystal defects is reduced to a predetermined value, so that the functional layer formed inside the opening can be used to manufacture the above-mentioned area below __2. In the case of the crystal defects, the above device is manufactured. The machine underneath is very good, so it can be used with good yield: in terms of aspect, the bottom area of the opening 105 is preferably 25_2 or more. "irt: 5 wide, the growth rate of _^ will become unprofitable, and it is easy to make the shape of =. In addition, when the compound semiconductor having the above area ratio m =: is processed, it is difficult to process, In the case where the yield of θ is reduced, the ratio of the bottom area of 〇 2 105 to the area of the coated area is preferably above. The covered area means that the crystalline layer 166 of S1 is an obstacle 321546 22 201019376 ^layer 104 When the ratio is less than 0.01%, the growth rate of the crystal inside the opening 105 becomes unstable. Further, in the case where a plurality of openings 1G5 are formed in one of the coated regions, the opening 1〇5 is opened. The bottom area indicates the sum of the bottom areas of the Weilang inclusions (four) mouth 1 [) 5. The shape of the bottom surface of the opening 105 may be the maximum width below the private claw, preferably 80 or less. The maximum width of the bottom surface shape of 1〇5 refers to the maximum length among the lengths of the straight lines connecting any two points included in the shape of the bottom surface of the opening 105. The case where the opening 1〇5 is square or rectangular is The shape of the bottom surface - the length of the side can be (10) (4) or less, preferably 80# m or less. The maximum width of the bottom surface shape may be lower than the case where the maximum width of the bottom surface shape is larger than 1〇〇#ra, and may be shorter than the case where the maximum width of the bottom surface shape is smaller than 1〇〇#ra. The annealing treatment of the crystal layer 106 formed on the inside of the opening 1〇5 is completed. Further, the Ge crystal layer 106 may be formed such that even at the temperature at which the anode layer 106 and the Si crystal layer 166 are annealed When the stress generated by the difference in the thermal expansion coefficient in the condition is different, the size of the defect does not occur in the Ge crystal layer 1 〇 6. For example, the maximum width of the crystal layer 106 in the direction substantially parallel to the main surface 172 may be 40 mm or less. Preferably, the thickness of the Ge crystal layer 106 is determined by the maximum width of the bottom surface shape of the opening 1〇5, so that the bottom surface of the opening 105 preferably has a maximum width of a predetermined value or less. For example, the maximum width of the bottom surface shape of the opening 1〇5 may be 40βιη or less, more preferably 3〇#m or less. An opening 1〇5 may be formed in one barrier layer 104. Thereby, it may be opened at 321546 23 201019376 The inside of the 105 crystallizes and grows at a stable growth rate. A plurality of openings 105 may be formed in one of the barrier layers 104. In this case, it is preferable to arrange the openings 105 at equal intervals. The crystal is epitaxially grown at a stable growth rate. The shape of the bottom surface of the opening 1〇5 is polygonal, and the direction of the one side of the polygon is preferably the crystallography of the main surface of the wafer 102: One of the orientations is substantially parallel. The shape of the bottom surface of the opening 105 is such that the relationship between the crystallographic plane orientation of the main surface of the SOI wafer 102 is such that the side surface of the opening 105 that grows crystallizes becomes a stable surface. Here, the term "sound _ odd/odd" includes the direction of the side of the polygon, and the crystallographic plane orientation of the wafer, which is slightly skewed from the mutually parallel state (four). The above-mentioned skewed ^_ under. By this, it is possible to suppress the gentleman, the sentence u, and the growth of the day, so that the above crystals are stably stabilized. The heart grows easily, and the shape of the seed knot can be obtained.

SS 面的主面可為陶面、⑽）面或⑴υ 面，或恢些面在結晶學上等效之 圓 :主面：佳為相對於上叫 -個角度。亦即，則晶圓⑽較佳為具有傾斜角。上= 2的大h可為1G以下。此外，上述傾斜的大 •。〇5以上/以下，可為〇.3。以上6。以下，亦可為2。以上 以下。在開口的内部使方形結晶成長的情況，晶圓的主 面，可為⑽）面或⑽）面或與這些面在結晶學上等效之 面。如此，就容易使上述結晶出現4重對稱（㈣Μ 321546 24 201019376 symmetry)的側面。 ^ 以下，針對一個例子，亦即阻礙層104形成於SOI晶 圓102的表面的（100)面，開口 105具有正方形或長方形的 底面形狀，Ge結晶層10 6為Ge結晶，種子化合物半導體 結晶108為GaAs結晶之例子來進行說明。此情況，開口 105的底面形狀的至少一邊的方向，可為與SOI晶圓102 的&lt;010〉方向、&lt;0-10&gt;方向、&lt;001〉方向及&lt;00-1&gt;方向中的 任何一個方向實質地平行之方向。如此，GaAs結晶的側面 ® 就會成為安定的面。 接著，針對另一個例子，亦即阻礙層104形成於SOI 晶圓102的表面的（111)面，開口 105具有六角形的底面形 狀，Ge結晶層106為Ge結晶，種子化合物半導體結晶108 為GaAs結晶之例子來進行說明。此情況，開口 105的底面 形狀的至少一邊的方向，可為與SOI晶圓102的&lt;1-10&gt;方 向、方向、〈0_11&gt;方向、方向、〈10_1&gt;方向 g 及&lt;-101 &gt;方向中的任何一個方向實質地平行之方向。如 此，GaAs結晶的側面就會成為安定的面。此外，開口 105 的底面形狀可為正六角形。 亦可在SOI晶圓102形成複數個阻礙層104。藉此， 在SOI晶圓102形成複數個被覆區域。例如，可在SOI晶 圓102將第5圖所示的阻礙層104形成於第21圖中所示的 各個區域803。 開口 105的内部的種子化合物半導體結晶108，係以 化學氣相成長法（CVD法）或氣相蠢晶成長法（VPE法）來形 25 321546 201019376 成。此等成長法，係將包含想要形成的薄膜結晶的構成元 素之原料氣體供給至晶圓上，藉由原料氣體的氣相或在晶 圓表面的化學反應來形成薄膜。供給至反應裝置内的原料 氣體，會藉由氣相反應而生成反應中間體（以下，有時稱之 為前驅體）。生成的反應中間體，會擴散到氣相中而後吸附 於晶圓表面。吸附於晶圓表面的反應中間體，會在晶圓表 面進行表面擴散，然後成為固體膜而析出。 其中，可在SOI晶圓102，在鄰接的兩個阻礙層104 之間設置犧牲成長部。該犧牲成長部會以比該兩個阻礙層 104的任一個的上表面為高的吸取速度吸取Ge結晶層106 或種子化合物半導體結晶108的原料，而形成薄膜。在犧 牲成長部形成的薄膜並不一定要是具有與Ge結晶層106或 種子化合物半導體結晶108同等的結晶品質之結晶薄膜， 亦可為多結晶體或非晶質體。另外，在犧牲成長部形成的 薄膜可不用於裝置的製造用。 犧牲成長部可將各個阻礙層104的一個個圍起來。藉 此，就可在開口 105的内部使結晶以穩定的速度磊晶成長。 此外，各個阻礙層104可具有複數個開口 105。電子裝置 100可在鄰接的兩個開口 105之間包含有犧牲成長部。各 個犧牲成長部可等間隔配置。 SOI晶圓102之表面附近的區域，可發揮作為犧牲成 長部之功能。而且，犧牲成長部可為形成於阻礙層104之 到達SOI晶圓102的溝槽。上述溝槽的寬度，可為20#111 以上500 # m以下。犧牲成長部内，有結晶成長亦無妨。 26 321546 201019376 如上所述，犧牲成長部係配置於鄰接的兩個阻礙層l〇4 V 之間。而且，犧牲成長部係以將各個阻礙層104圍起來的 方式設置。藉此，犧牲成長部就可捕捉、吸取或黏取在被 覆區域的表面擴散之上述前驅體。因此，可使結晶在開口 105的内部以穩定的成長速度成長。上述前驅體為種子化 合物半導體結晶108的原料之一例。 在一個例子中，將預定大小的被覆區域配置於S〇i晶 圓102的表面之情況，在被覆區域以外的區域之s〇l晶圓 Ο 102的表面會露出來。藉由M0CVD法使結晶在開口 1〇5的 内部成長時，到達SOI晶圓102的表面之前驅體的一部份 就會在SOI晶圓102的表面結晶成長。如此，使上述前驅 體的一部份在SOI晶圓102的表面消耗掉’形成於開口 的内部之結晶的成長速度就會變得穩定。 · 犧牲成長部的另一個例子，可列舉是由S i、GaAs等形 成的半導體區域。例如’在阻礙層104的表面，以離子鍍 覆法（ion plating method)、濺鍍法（sputtering method) ®等之方法，堆積非晶質半導體（amorphous semiconductor)、或半導體多晶體（semiconductor polycrystal)，來形成犧牲成長部。犧牲成長部可配置於 鄰接的兩個阻礙層104之間’亦可包含於阻礙層中。 另外，可在鄰接的兩個被覆區域之間，配置阻礙前軀體的 擴散之區域。而且，被覆區域可由阻礙前驅體的擴散之區 域加以包圍。 只要使鄰接的兩個卩导礙層104略為分開，在開口 1〇5 321546 27 201019376 的内部之結晶的成長速度就會變得穩定。鄰接的兩個阻礙 層104可分離20_以上而設置。鄰接的兩個阻礙層⑽ 亦可令間隔著犧牲成長部而相隔2()_以上而設置。藉 此’就可使結晶在開口！05的内部以更穩定成長速度』 長。此處，鄰接的兩個阻礙層1〇4之間的距離，係表示鄰 接的兩個阻礙層104的外周上的點之間的最短距離。各個 阻礙層104可等間隔配置。尤其，鄰接的兩個阻礙層104 之間的距離不到1〇Am之情況’使複數個阻礙層1〇4等間 隔配置’可使結晶在開σ 1G5的内部以穩定成長速度成長。 SOI晶圓102,可為不含有雜質之高電阻晶圓，亦可為 含有P型或η型雜質之低電阻晶圓。Ge結晶層1〇6，可由 不含有雜質之Ge形成，亦可由含有p型或n型雜質之以 形成。 /開口 1G5之從層積方向所見之形狀，係為正方形、長 方，、圓形、橢圓形、及長圓形等之任意的形狀。開口 105 之，層積方向所見之形狀為圓形或橢圓形之情況，開口 1〇5 的I度係分別為圓的直徑及橢圓的短徑。開口 1〇5之在與 層積方向平行的面之斷面形狀，係為矩形、梯形、撤物線 形狀、及雙曲線形狀等之任意的形狀。開口⑽之在與層 積方向平行的面之斷面形狀為梯形之情況’開口 1〇5的寬 度係開口 105的底面或入口兩者中之最短的寬度。 ,開口 1〇5之從層積方向所見之形狀為長方形或正方 形，在與層積方向平行的面之開口 1〇5的斷面形狀為矩形 障况開口 105内部的立體形狀即為長方體。不過，開 321546 28 201019376 v 口 i〇5内部的立體形狀通常為任意的形狀。此時，可使用 與開口 105内部的立體形狀近似之長方體的深寬比， 為任意的立體形狀的深寬比。The main surface of the SS surface may be a ceramic surface, a (10) surface or a (1) surface, or a crystallographically equivalent circle: the main surface: preferably an angle relative to the upper surface. That is, the wafer (10) preferably has an oblique angle. The large h of upper = 2 can be less than 1G. In addition, the above inclination is large. 〇5 or more / below, can be 〇.3. Above 6. The following may also be 2. Above. In the case where the square crystal grows inside the opening, the main surface of the wafer may be a (10) plane or a (10) plane or a crystallographically equivalent surface to the plane. Thus, it is easy to cause the above crystal to appear on the side of the 4-fold symmetry ((4) 321 321546 24 201019376 symmetry). ^ Hereinafter, for one example, that is, the barrier layer 104 is formed on the (100) plane of the surface of the SOI wafer 102, the opening 105 has a square or rectangular bottom surface shape, and the Ge crystal layer 106 is a Ge crystal, and the seed compound semiconductor crystal 108 It is explained as an example of GaAs crystallization. In this case, the direction of at least one side of the bottom surface shape of the opening 105 may be in the &lt;010> direction, &lt;0-10&gt; direction, &lt;001> direction, and &lt;00-1&gt; direction of the SOI wafer 102. Any direction is substantially parallel to the direction. Thus, the side ® of the GaAs crystal becomes a stable surface. Next, for another example, that is, the barrier layer 104 is formed on the (111) plane of the surface of the SOI wafer 102, the opening 105 has a hexagonal bottom surface shape, the Ge crystal layer 106 is Ge crystal, and the seed compound semiconductor crystal 108 is GaAs. An example of crystallization will be described. In this case, the direction of at least one side of the bottom surface shape of the opening 105 may be &lt;1-10&gt; direction, direction, <0_11&gt; direction, direction, <10_1&gt; direction g, and &lt;-101 &gt; Any direction in the direction that is substantially parallel. Thus, the side surface of the GaAs crystal becomes a stable surface. Further, the shape of the bottom surface of the opening 105 may be a regular hexagon. A plurality of barrier layers 104 may also be formed on the SOI wafer 102. Thereby, a plurality of covered regions are formed on the SOI wafer 102. For example, the barrier layer 104 shown in Fig. 5 can be formed in each region 803 shown in Fig. 21 in the SOI wafer 102. The seed compound semiconductor crystal 108 inside the opening 105 is formed by chemical vapor deposition (CVD) or vapor phase growth (VPE) to form 25321546 201019376. In the above growth method, a material gas containing constituent elements of a thin film crystal to be formed is supplied onto a wafer, and a thin film is formed by a gas phase of a material gas or a chemical reaction on a crystal surface. The raw material gas supplied to the reaction apparatus is reacted by a gas phase to form a reaction intermediate (hereinafter sometimes referred to as a precursor). The resulting reaction intermediate diffuses into the gas phase and is then adsorbed onto the wafer surface. The reaction intermediate adsorbed on the surface of the wafer diffuses on the surface of the wafer and then forms a solid film to precipitate. Among them, a sacrificial growth portion may be provided between the adjacent two barrier layers 104 on the SOI wafer 102. The sacrificial growth portion absorbs the material of the Ge crystal layer 106 or the seed compound semiconductor crystal 108 at a suction speed higher than the upper surface of either of the two barrier layers 104 to form a thin film. The film formed in the sacrificial growth portion does not necessarily have to have a crystal quality equivalent to that of the Ge crystal layer 106 or the seed compound semiconductor crystal 108, and may be a polycrystalline body or an amorphous body. Further, the film formed at the sacrificial growth portion may not be used for the manufacture of the device. The sacrificial growth portion encloses each of the barrier layers 104. Thereby, the crystal can be epitaxially grown at a stable speed inside the opening 105. Additionally, each of the barrier layers 104 can have a plurality of openings 105. The electronic device 100 can include a sacrificial growth portion between the adjacent two openings 105. Each of the sacrificial growth units can be arranged at equal intervals. The region near the surface of the SOI wafer 102 functions as a sacrificial growth portion. Moreover, the sacrificial growth portion may be a trench formed in the barrier layer 104 to reach the SOI wafer 102. The width of the above groove may be 20#111 or more and 500#m or less. Sacrificing growth within the growth department is no problem. 26 321546 201019376 As described above, the sacrificial growth portion is disposed between the adjacent two barrier layers 10V. Further, the sacrificial growth portion is provided in such a manner as to surround each of the barrier layers 104. Thereby, the precursor which is diffused on the surface of the coated region can be captured, sucked or adhered by sacrificing the growth portion. Therefore, the crystal can be grown at a stable growth rate inside the opening 105. The above precursor is an example of a raw material of the seed compound semiconductor crystal 108. In one example, when a predetermined size of the coated region is disposed on the surface of the S?i crystal 102, the surface of the wafer 102 is exposed in a region other than the covered region. When the crystal grows inside the opening 1〇5 by the M0CVD method, a part of the precursor which reaches the surface of the SOI wafer 102 crystallizes and grows on the surface of the SOI wafer 102. Thus, a part of the precursor is consumed on the surface of the SOI wafer 102, and the growth rate of the crystal formed inside the opening becomes stable. Another example of the sacrificial growth portion is a semiconductor region formed of S i , GaAs or the like. For example, 'on the surface of the barrier layer 104, an amorphous semiconductor or a semiconductor polycrystal is deposited by an ion plating method, a sputtering method, or the like. To form a sacrifice growth department. The sacrificial growth portion may be disposed between the adjacent two barrier layers 104 and may also be included in the barrier layer. Further, a region that blocks the diffusion of the front body may be disposed between the adjacent two covered regions. Moreover, the covered area may be surrounded by a region that hinders the diffusion of the precursor. As long as the adjacent two barrier layers 104 are slightly separated, the growth rate of the crystal inside the opening 1 〇 5 321546 27 201019376 becomes stable. The adjacent two obstruction layers 104 can be disposed apart by 20_ or more. The two adjacent barrier layers (10) may be arranged at intervals of 2 ()_ or more apart from the growth portion. By this, you can crystallize at the opening! The interior of 05 is growing at a more stable growth rate. Here, the distance between the adjacent two barrier layers 1〇4 represents the shortest distance between the points on the outer circumference of the adjacent two barrier layers 104. Each of the barrier layers 104 can be arranged at equal intervals. In particular, when the distance between the adjacent two barrier layers 104 is less than 1 〇 Am, the arrangement of the plurality of barrier layers 1 〇 4 and the like is such that the crystal grows at a steady growth rate inside the opening σ 1G5. The SOI wafer 102 can be a high-resistance wafer containing no impurities or a low-resistance wafer containing P-type or n-type impurities. The Ge crystal layer 1〇6 may be formed of Ge which does not contain impurities, or may be formed of p-type or n-type impurities. / Opening The shape of the 1G5 seen from the stacking direction is any shape such as a square, a rectangle, a circle, an ellipse, and an oblong. In the case of the opening 105, the shape seen in the stacking direction is circular or elliptical, and the degree I of the opening 1〇5 is the diameter of the circle and the short diameter of the ellipse, respectively. The cross-sectional shape of the opening 1〇5 in a plane parallel to the stacking direction is any shape such as a rectangle, a trapezoidal shape, a relief line shape, and a hyperbolic shape. In the case where the cross-sectional shape of the opening (10) in the plane parallel to the stacking direction is trapezoidal, the width of the opening 1〇5 is the shortest width of the bottom surface or the entrance of the opening 105. The shape of the opening 1〇5 from the lamination direction is a rectangle or a square shape, and the cross-sectional shape of the opening 1〇5 of the surface parallel to the lamination direction is a rectangular shape. The three-dimensional shape inside the opening 105 is a rectangular parallelepiped. However, the opening 321546 28 201019376 v The internal shape of the i〇5 is usually an arbitrary shape. In this case, the aspect ratio of the rectangular parallelepiped which approximates the three-dimensional shape inside the opening 105 can be used as an aspect ratio of an arbitrary three-dimensional shape.

Ge結晶層106可具有捕捉在Ge結晶層1〇6的内部移 動的缺陷之缺陷捕捉部。該缺陷可包含當Ge結晶層工的形 成時就存在之缺陷。缺陷捕捉部可為Ge結晶層1〇6中之結 晶界面（boundary)或結晶表面，亦可為形成於^結晶層° 106之物理性的傷痕。例如，缺陷捕捉部為結晶界面= ⑩晶表面，且為並不與Si曰曰曰gj 162大致平行的方向之面 -個例子中’係藉由將Ge結晶層i㈣刻成線狀或孤立的 島狀，在Ge結晶層1G6形成結晶界面，來形成缺陷捕捉部。 另外，藉由以機械性的刮搔、摩擦、或離子注入等方式在 Ge結晶層1G6形成物理性的傷痕，亦可形成缺陷捕捉部。 缺陷捕捉部係形成於Ge結晶層⑽之並未因開口 1〇5而露 出之區域。此外’缺陷捕捉部亦可為Ge結晶層與阻礙層 ©104之界面。 缺陷捕捉部可配置成：與Ge結晶層1〇6所包含的任意 的點之距離，會小於等於在退火處理的溫度及時間條件下 缺fe可移動的距離。上述缺陷可移動的距離在退火 處理溫度為m至95(rc之情況，可為至2〇_。缺 陷她部可配置在相對於Ge結晶層106所包含的所有缺陷 而β都在上述距離内之位置。、结果，Ge、结晶層⑽内部的 貝穿缺陷密度（或者，也稱為貫穿差排密度（浙⑽恤 dislocation density))就會因為上述退火處理而減低。例 29 321546 201019376 如，作為種子結晶層的一個例子之Ge結晶層106的表面的 ’ 貫穿差排密度，會減低到lxl06/cm2以下。 v 另外，亦可讓Ge結晶層106在Ge結晶層106形成時 就已存在之缺陷可移動到Ge結晶層106的上述缺陷捕捉部 之溫度及時間的條件下接受退火處理。例如，Ge結晶層106 的外緣發揮作為缺陷捕捉部的功能之情況，可讓Ge結晶層 106在Ge結晶層106所包含的任意位置的缺陷可移動到Ge 結晶層106的外緣之溫度及時間的條件下接受退火處理。The Ge crystal layer 106 may have a defect trapping portion that traps a defect that moves inside the Ge crystal layer 1〇6. This defect may include defects that are present when the Ge crystal layer is formed. The defect trapping portion may be a boundary or a crystal surface in the Ge crystal layer 1〇6, or may be a physical flaw formed in the crystal layer 106. For example, the defect capturing portion is a crystal interface = 10 crystal surface, and is a surface that is not substantially parallel to Si曰曰曰gj 162 - in an example, by engraving the Ge crystal layer i (four) in a line shape or in isolation In the island shape, a crystal interface is formed in the Ge crystal layer 1G6 to form a defect trapping portion. Further, a physical scratch can be formed in the Ge crystal layer 1G6 by mechanical scraping, rubbing, ion implantation or the like, and a defect trapping portion can be formed. The defect trapping portion is formed in a region of the Ge crystal layer (10) which is not exposed by the opening 1〇5. Further, the defect trapping portion may be an interface between the Ge crystal layer and the barrier layer ©104. The defect trapping portion may be configured such that the distance from any point included in the Ge crystal layer 1 〇 6 is less than or equal to the distance at which the defect is movable under the temperature and time conditions of the annealing treatment. The above-mentioned defect movable distance is in the case of an annealing treatment temperature of m to 95 (in the case of rc, it may be up to 2 〇 _. The defect portion may be disposed in all the defects contained in the Ge crystal layer 106 and β is within the above distance As a result, the defect density of the inside of Ge, the crystal layer (10) (or, also referred to as the dislocation density) is reduced by the above annealing treatment. Example 29 321546 201019376 For example, The penetration density of the surface of the Ge crystal layer 106, which is an example of the seed crystal layer, is reduced to below lxl06/cm2. v Alternatively, the Ge crystal layer 106 may be formed when the Ge crystal layer 106 is formed. The defect can be annealed under the condition of the temperature and time of the defect trapping portion of the Ge crystal layer 106. For example, if the outer edge of the Ge crystal layer 106 functions as a defect trapping portion, the Ge crystal layer 106 can be made The defect at any position included in the Ge crystal layer 106 can be annealed under the condition of the temperature and time of the outer edge of the Ge crystal layer 106.

Ge結晶層106可形成為如下之大小，亦即形成為：在Ge ❹ 結晶層106形成時就已存在之缺陷可藉由退火處理而移 動，使得Ge結晶層106的内部的缺陷密度減低之大小。亦 可讓Ge結晶層106以如下之最大寬度形成，亦即以：不超 過缺陷在預定條件的退火處理下移動的距離的兩倍之最大 寬度形成。 藉由採用以上的構成，使Ge結晶層106之缺陷捕捉部 以外的區域中的缺陷密度減低。例如，Ge結晶層106蟲晶 ❹ 成長的情況，會有晶格缺陷等發生之情形。上述缺陷可在 Ge結晶層106的内部移動，且Ge結晶層106的溫度越高 移動速度也越快。而且，上述缺陷會在Ge結晶層106的表 面及界面等被捕捉。 上述缺陷，在以上述溫度及時間對Ge結晶層106施加 退火處理的作用下，會在Ge結晶層106的内部移動，然後 在例如Ge結晶層106與阻礙層104的界面被捕捉。如此， 存在於Ge結晶層106的内部之缺陷，在退火處理的作用下 30 321546 201019376 v 2集中到上述界面，因而減低G e結晶们G 6的内部的缺陷 密度。結果，與退火處理前相比較，在開π 1G5中露出的 Ge結晶層1〇6的表面的結晶性就會提高。 藉由上述的方式，減低蟲晶薄膜中之缺陷，電子裝置 的性能就會提高。例如，以在開口 105巾露出的Ge結晶層 106的表面為結晶核，使種子化合物半導體結晶⑽成長 It;兄種子彳b合物半導體結晶的結晶性就會提高。 此外’以結晶性良好的Ge結晶層1〇6作為晶圓材料，就可 απ質良好地形成由於晶格不匹配而無法在以結晶層166直 接結晶成長之種類的薄膜。The Ge crystal layer 106 may be formed in a size such that defects existing in the formation of the Ge 结晶 crystal layer 106 can be moved by annealing treatment, so that the defect density inside the Ge crystal layer 106 is reduced. . It is also possible to form the Ge crystal layer 106 with a maximum width which is formed not to exceed the maximum width of twice the distance that the defect moves under the annealing treatment under predetermined conditions. By adopting the above configuration, the defect density in the region other than the defect capturing portion of the Ge crystal layer 106 is reduced. For example, in the case where the Ge crystal layer 106 is grown, there are cases where lattice defects or the like occur. The above defects can be moved inside the Ge crystal layer 106, and the higher the temperature of the Ge crystal layer 106, the faster the moving speed. Further, the above defects are caught on the surface and interface of the Ge crystal layer 106. The above defects are moved inside the Ge crystal layer 106 by applying an annealing treatment to the Ge crystal layer 106 at the above temperature and time, and then captured at the interface between the Ge crystal layer 106 and the barrier layer 104, for example. Thus, defects existing in the inside of the Ge crystal layer 106 are concentrated to the above interface by the annealing treatment, thereby reducing the defect density inside the G e crystals G 6 . As a result, the crystallinity of the surface of the Ge crystal layer 1〇6 exposed in the open π 1G5 is improved as compared with that before the annealing treatment. By reducing the defects in the insect crystal film by the above, the performance of the electronic device is improved. For example, the surface of the Ge crystal layer 106 exposed in the opening 105 is a crystal nucleus, and the seed compound semiconductor crystal (10) grows It; the crystallinity of the crystal of the sibling seed crystal semiconductor is improved. Further, when the Ge crystal layer 1〇6 having good crystallinity is used as the wafer material, a film of a type which cannot be crystallized directly by the crystal layer 166 due to lattice mismatch can be satisfactorily formed.

Ge結晶層1〇6亦可局部地形成於第二化合物半導體結 晶112與Si結晶層166之間的一部份，並與第二化合物半 導體結晶112.晶格匹配或準晶格匹配。藉此，而得到缺陷 密度小的Ge結晶層1〇6。 本况明書中，缺陷密度小，係指預定大小的結晶層的 ⑩内部含有的貫穿差排的個數的平均值在〇1個以下之情 況。貝穿差排，係指貫穿Ge結晶層1〇6而形成的缺陷。貫 穿差排的平均值在01個以下，係相當於檢查1〇個活性層 部份的面積為10#mxl0_左右的裝置，結果發現1個具 有貫穿差排的裝置之情形。貫穿差排的平均值在〇1個以 下’係指換异為差排密度的話，以蝕孔（etch pit)法或穿 透式電子顯微鏡（以下，有時稱之為TEM)進行之平面斷面 觀察所量測出來的平均差排密度大約在〗· 〇S/cm_2以下 之情況。 321546 31 201019376The Ge crystal layer 1〇6 may also be locally formed in a portion between the second compound semiconductor crystal 112 and the Si crystal layer 166, and lattice-matched or pseudo-lattice-matched with the second compound semiconductor crystal 112. Thereby, a Ge crystal layer 1〇6 having a small defect density was obtained. In the case of the present specification, the defect density is small, and the average value of the number of penetration rows contained in the inside of the crystal layer 10 of a predetermined size is 〇1 or less. The defect of the shell is a defect formed by penetrating the Ge crystal layer 1〇6. The average value of the penetration ratio is 01 or less, which corresponds to a device in which an area of one active layer portion is examined to be about 10 #mxl0_, and as a result, one device having a through-displacement device is found. When the average value of the through-displacement is less than 1 or less, the difference is the difference in the discharge density, and the plane is broken by an etch pit method or a transmission electron microscope (hereinafter, sometimes referred to as TEM). The average difference density measured by the surface observation is about 〇·· S/cm 2 or less. 321546 31 201019376

Ge結晶層106之與種子化合物半導體結晶108相向的 · 面，可接受以包含P之氣體進行之表面處理。藉此，可提 v 高形成於Ge結晶層106之膜的結晶性。包含P之氣體，可 為包含PH3(phosphine ;填化氫）之氣體。The surface of the Ge crystal layer 106 which faces the seed compound semiconductor crystal 108 can be subjected to surface treatment with a gas containing P. Thereby, the crystallinity of the film formed on the Ge crystal layer 106 can be raised. The gas containing P may be a gas containing PH3 (phosphine).

Ge結晶層106可藉由例如CVD法或MEB法（分子線磊 晶法）而形成。原料氣體可為GeH4(鍺曱烷）。Ge結晶層106 亦可在0. 1 Pa以上100 Pa以下的壓力下藉由CVD法而形 成。如此，Ge結晶層106的成長速度就不易受到開口 105 的面積之影響。結果，例如，Ge結晶層106的膜厚的均一 ❹ 性就會提高。而且，在此情況下，可抑制Ge結晶在阻礙層 104的表面之堆積。The Ge crystal layer 106 can be formed by, for example, a CVD method or an MEB method (molecular line epitaxy method). The material gas may be GeH4 (decane). The Ge crystal layer 106 may be formed by a CVD method at a pressure of 0.1 Pa or more and 100 Pa or less. Thus, the growth rate of the Ge crystal layer 106 is less susceptible to the area of the opening 105. As a result, for example, the uniformity of the film thickness of the Ge crystal layer 106 is improved. Further, in this case, deposition of Ge crystal on the surface of the barrier layer 104 can be suppressed.

Ge結晶層106亦可在將含有鹵素元素的氣體作為原料 氣體的至少一部份而包含於其中之環境氣體中藉由CVD法 而形成。含有鹵素元素的氣體，可為氣化氫氣體或氣氣。 藉此，即使是在100 Pa以上的壓力下藉由CVD法來形成 Ge結晶層106之情況，也可抑制Ge結晶往阻礙層104的The Ge crystal layer 106 may also be formed by a CVD method in an ambient gas in which a gas containing a halogen element is contained as at least a part of a material gas. A gas containing a halogen element may be a hydrogenated gas or a gas. Thereby, even when the Ge crystal layer 106 is formed by the CVD method under a pressure of 100 Pa or more, the Ge crystal can be suppressed from proceeding to the barrier layer 104.

Q 表面之堆積。 在本實施形態中，雖然針對Ge結晶層106與SOI晶圓 102的表面相接而形成之情況進行說明，但Ge結晶層106 及SOI晶圓102之配置並不限於此。例如，亦可在Ge結晶 層106與SOI晶圓102之間配置其他的層。上述其他的層， 可為單一的層，亦可包含複數的層。 作為一個例子，Ge結晶層106係以以下的程序形成。 首先，在低溫下形成種子結晶。種子結晶可為SixGen(式 32 321546 201019376 ' 中，0$χ&lt;1)。種子結晶的成長溫度，可為330°c以上450°C 、 以下。然後，可在使形成了種子結晶之SOI晶圓102的溫 度昇高到預定的溫度後，形成Ge結晶層106。 種子化合物半導體結晶108可以Ge結晶層106為核而 結晶成長到其上部從阻礙層104的表面突出。例如，種子 化合物半導體結晶108可在開口 105的内部結晶成長到比 阻礙層104的表面突出。 種子化合物半導體結晶108的一個例子係為與Ge結晶 ❹ 層106晶格匹配或準晶格匹配之IV族、III-V族或II-VI 族之化合物半導體。更具體言之，種子化合物半導體結晶 108 可為 GaAs、InGaAs(神化銦鎵）、SixGei-x(0Sx&lt;l)。另 外，可在種子化合物半導體結晶108與Ge結晶層106之間 形成缓衝層。緩衝層與Ge結晶層106晶格匹配或準晶格匹 配。緩衝層的一個例子係具有包含P之111 -V族化合物半 導體層。 ©種子化合物半導體結晶108為功能層的一個例子。種 子化合物半導體結晶108係與Ge結晶層106相接而形成。 亦即，種子化合物半導體結晶108係在Ge結晶層106上結 晶成長。作為一個例子，種子化合物半導體結晶108係以 蟲晶成長方式結晶成長。 種子化合物半導體結晶108其算術平均粗度（以下，有 時稱之Ra值）的一個例子為0.02# m以下，較佳為0.01//m 以下。如此，就可使用種子化合物半導體結晶108來形成 高性能的裝置。此處，Ra值係表示表面粗度的指標，可依 33 321546 201019376 據JIS B06G1-2G01而算出。Ra值可將—^長度的粗度曲 線從中心線往回折，然後將藉由該粗度曲線及該中心線而 得到的面積除以量測出的長度而算出。 種子化合物半導體結晶1〇8的成長速度，可為細⑽/ mln以下’較佳為200nm/min以下，更佳為6〇⑽以下。 如此，就可使種子化合物半導體結晶1〇8的以值在〇. 〇2_ 以下。另一方面，種子化合物半導體結晶1〇8的成長速度， &quot;T為lnm/min以上，較佳為5nm/mjn以上。如此，可在不 犧牲生產性的情況下，得到良質的種子化合物半導體結晶 108。例如，可使種子化合物半導體結晶1〇8以“‘“η以 上，30〇nm/min以下的成長速度結晶成長。 在本實施形態中’雖然針對在Ge結晶層1 〇6的表面形 成種子化合物半導體結晶⑽之情職行說明，但並不限 於此。例如，亦可在以結晶層1〇6與種子化合物半導體結 晶108之間配置中間層。中間層，可為單一的層，亦可包 含複數的層。中間層可在_°C以下，較佳為在55crc以下 形成。如此，種子化合物半導體結晶1〇8的結晶性會提高。 另方面，中間層可在400t：以上形成。中間層可在4〇〇t&gt;c 以上，600t以下形成。如此，種子化合物半導體結晶ι〇8 的結晶性會提高。中間層的一個例子為以600。(：以下，較 佳為550°C以下之溫度形成的GaAs層。 、種子化合物半導體結晶108可按以下的程序來形成。 =先’在Ge結晶層1〇6的表面形成中間層。中間層的成長 溫度的一個例子，係為6〇〇ν以下。然後，可在使形成了 321546 34 201019376 中間層之SOI晶圓102的溫度昇高到預定的溫度後，形成 ' 種子化合物半導體結晶108。 第一化合物半導體結晶110，可以從阻礙層1〇4的表 面突出之種子化合物半導體結晶108的預定的面作為結晶 核的種子面，沿著阻礙層104橫向成長而形成。s〇I晶圓 102的面方位為（1〇〇)，且在〈〇〇1〉方向形成開口 1〇5之情 況’種子化合物半導體結晶108的種子面，係為（11〇)面及 與（110)面等效的面。在〈011&gt;方向形成開口 1〇5之情況， ®種子化合物半導體結晶108的種子面，係為（πι)Α面及與 (lll)A面等效的面。因為藉由退火處理等使種子化合物半 導體結晶108的結晶性提高，所以可形成結晶性良好的第 一化合物半導體結晶11〇。 第一化合物半導體結晶11〇可為與種子化合物半導體 結晶108晶格匹配或準晶格匹配之Iv族、hi_v族或 族之化合物半導體。例如，第一化合物半導體結晶11〇係 參為 GaAs、InGaAs、SixGe^O^xO。 第二化合物半導體結晶112,可以第一化合物半導體 結晶11〇的預定的面作為種子面，沿著阻礙層1〇4橫向成 長而形成。如上所述，第二化合物半導體結晶112可在與 第一化合物半導體結晶110不同的方向橫向成長。 第二化合物半導體結晶112可與以結晶層⑽晶格匹 配或準晶格匹配。第二化合物半導體結晶112以結晶性良 好的第-化合物半導體結晶110的特定面作為種子面而結 晶成長，所以可形成結晶性良好的第二化合物半導體結晶 321546 35 201019376 112。因此’第二化合物半導體結晶112具有不含有缺陷之 無缺陷區域。 第二化合物半導體結晶112可包含與Ge結晶層；[〇6晶 格匹配或準晶格匹配之ιι-νι族化合物半導體或111-¥族 化合物半導體。第一化合物半導體結晶112係包含例如 GaAs 或 InGaAs 層。 在SOI晶圓102與Ge結晶層1〇6相接的部份，可在 SOI晶圓102内包含有與SOI晶圓1〇2及Ge結晶層1〇6 的界面相接之Sh-xGex層（0&lt;χ&lt;1)。亦即，Ge結晶層ι〇6内 的Ge原子可擴散到SOI晶圓102，而形成SiGe層。在此 情況下’可提高在Ge結晶層106之上形成的磊晶層的結晶 性。另外’可使Sh-xGex層中之Ge的平均組成X，在距s〇I 晶圓102與Ge結晶層106的界面之距離為5 nm以上1〇 nm 以下的區域中為60%以上。在這樣的情況下，尤其可提高 在Ge結晶層1 〇6上形成的磊晶層的結晶性。 另外，在本實施形態中，雖然第二化合物半導體結晶 112為以第一化合物半導體結晶11〇的特定面為種子面， 而沿著阻礙層1〇4橫向成長成的化合物半導體，但種子化 合物半導體結晶108及第一化合物半導體結晶11〇亦可為 -體形成的化合物半導體結晶。第二化合物半導體結晶 亦可以上述一體形成的化合物半導體結晶的特定面作為種 子面而在阻礙層1〇4之上橫向成長成的化合物半導體。 上述-體形成的化合物半導體結晶，可為以^結晶芦⑽ 為核而成長成的化合物半導體結晶，且形成得比阻礙層ι〇4 321546 36 201019376 的表面凸出之化合物半導體結晶。藉此’使阻礙層丨〇4的 至少一部份形成於第二化合物半導體結晶112與s〇I晶圓 102的絕緣層164之間。 可在第二化合物半導體結晶112的無缺陷區域上，形 成具有活性區域之主動元件。主動元件係為例如具備有間 極絕緣膜114、閘極電極116、源極/汲極電極118之 MISFEPMISFET 可為 MOSFET(Metal-〇xide_Semic〇nduct〇rQ The accumulation of surfaces. In the present embodiment, the case where the Ge crystal layer 106 is formed in contact with the surface of the SOI wafer 102 will be described. However, the arrangement of the Ge crystal layer 106 and the SOI wafer 102 is not limited thereto. For example, another layer may be disposed between the Ge crystal layer 106 and the SOI wafer 102. The other layers described above may be a single layer or a plurality of layers. As an example, the Ge crystal layer 106 is formed by the following procedure. First, seed crystals are formed at a low temperature. The seed crystal may be SixGen (in the formula 32 321546 201019376 ', 0$χ&lt;1). The growth temperature of the seed crystals may be 330 ° C or more and 450 ° C or less. Then, the Ge crystal layer 106 can be formed after raising the temperature of the SOI wafer 102 on which the seed crystals are formed to a predetermined temperature. The seed compound semiconductor crystal 108 may have a Ge crystal layer 106 as a core and crystal growth to an upper portion thereof protruding from the surface of the barrier layer 104. For example, the seed compound semiconductor crystal 108 may crystallize in the interior of the opening 105 to protrude beyond the surface of the barrier layer 104. An example of the seed compound semiconductor crystal 108 is a compound semiconductor of Group IV, Group III-V or Group II-VI which is lattice matched or quasi-lattice matched to the Ge crystalline germanium layer 106. More specifically, the seed compound semiconductor crystal 108 may be GaAs, InGaAs (Indium Gallium), SixGei-x (0Sx &lt; l). Further, a buffer layer may be formed between the seed compound semiconductor crystal 108 and the Ge crystal layer 106. The buffer layer is lattice matched or quasi-lattice matched to the Ge crystal layer 106. An example of a buffer layer is a layer of a 111-V compound semiconductor comprising P. The seed compound semiconductor crystal 108 is an example of a functional layer. The seed compound semiconductor crystal 108 is formed by being in contact with the Ge crystal layer 106. That is, the seed compound semiconductor crystal 108 is crystal grown on the Ge crystal layer 106. As an example, the seed compound semiconductor crystal 108 crystallizes in a crystal growth manner. An example of the arithmetic mean roughness (hereinafter, referred to as Ra value) of the seed compound semiconductor crystal 108 is 0.02 # m or less, preferably 0.01 / m or less. Thus, the seed compound semiconductor crystal 108 can be used to form a high performance device. Here, the Ra value is an index indicating the surface roughness, and can be calculated according to JIS B06G1-2G01 according to 33 321546 201019376. The Ra value can be obtained by folding the thickness curve of the length from the center line back, and then dividing the area obtained by the thickness curve and the center line by the measured length. The growth rate of the seed compound semiconductor crystal 1〇8 may be preferably fine (10)/mln or less, preferably 200 nm/min or less, more preferably 6 Å (10) or less. Thus, the value of the seed compound semiconductor crystal 1〇8 can be made 〇. 〇2_ or less. On the other hand, the growth rate of the seed compound semiconductor crystal 1〇8 is &lt;T is 1 nm/min or more, preferably 5 nm/mjn or more. Thus, a good seed compound semiconductor crystal 108 can be obtained without sacrificing productivity. For example, the seed compound semiconductor crystal 1 8 can be crystal grown at a growth rate of "" η or more and 30 〇 nm / min or less. In the present embodiment, the description will be made regarding the formation of the seed compound semiconductor crystal (10) on the surface of the Ge crystal layer 1 〇6, but the present invention is not limited thereto. For example, an intermediate layer may be disposed between the crystal layer 1〇6 and the seed compound semiconductor crystal 108. The intermediate layer may be a single layer or a plurality of layers. The intermediate layer may be formed below _°C, preferably below 55crc. Thus, the crystallinity of the seed compound semiconductor crystal 1〇8 is improved. On the other hand, the intermediate layer can be formed at 400t: or more. The intermediate layer can be formed at 4 〇〇 t &gt; c or more and 600 t or less. Thus, the crystallinity of the seed compound semiconductor crystal ι〇8 is improved. An example of the middle layer is at 600. (The following is preferably a GaAs layer formed at a temperature of 550 ° C or lower. The seed compound semiconductor crystal 108 can be formed by the following procedure. = First, an intermediate layer is formed on the surface of the Ge crystal layer 1 〇 6. An example of the growth temperature is 6 ν or less. Then, the seed compound semiconductor crystal 108 can be formed after raising the temperature of the SOI wafer 102 on which the intermediate layer of the 321546 34 201019376 is formed to a predetermined temperature. The first compound semiconductor crystal 110 can be formed by forming a predetermined surface of the seed compound semiconductor crystal 108 protruding from the surface of the barrier layer 1〇4 as a seed surface of the crystal nucleus and growing laterally along the barrier layer 104. The wafer 102 is formed. The surface orientation is (1 〇〇), and the opening 1 〇 5 is formed in the <〇〇1> direction. 'The seed surface of the seed compound semiconductor crystal 108 is the (11 〇) plane and is equivalent to the (110) plane. In the case where the opening 1〇5 is formed in the <011> direction, the seed surface of the ® seed compound semiconductor crystal 108 is a (πι) plane and a plane equivalent to the (ll) A plane because it is annealed. Seeding Since the crystallinity of the semiconductor crystal 108 is improved, the first compound semiconductor crystal 11〇 having good crystallinity can be formed. The first compound semiconductor crystal 11〇 can be a lattice matching or quasi-lattice matching with the seed compound semiconductor crystal 108. a compound semiconductor of the hi-v group or the group. For example, the first compound semiconductor crystal 11 〇 参 is GaAs, InGaAs, SixGe^O^xO. The second compound semiconductor crystal 112 may be a predetermined surface of the first compound semiconductor crystal 11〇 As the seed surface, it is formed to grow laterally along the barrier layer 1〇4. As described above, the second compound semiconductor crystal 112 may grow laterally in a direction different from the first compound semiconductor crystal 110. The second compound semiconductor crystal 112 may be The crystal layer (10) is lattice-matched or pseudo-lattice-matched. The second compound semiconductor crystal 112 crystallizes and grows on the specific surface of the first compound semiconductor crystal 110 having good crystallinity as a seed surface, so that a second compound semiconductor having good crystallinity can be formed. Crystallization 321546 35 201019376 112. Therefore 'the second compound semiconductor crystal 112 has no The defect-free region of the defect. The second compound semiconductor crystal 112 may comprise a crystal layer of Ge; [〇6 lattice-matched or pseudo-lattice-matched ιι-νι group compound semiconductor or 111-¥ compound semiconductor. First compound semiconductor crystal The 112 series includes, for example, a GaAs or InGaAs layer. The portion of the SOI wafer 102 that is in contact with the Ge crystal layer 1〇6 may include the SOI wafer 1〇2 and the Ge crystal layer 1〇6 in the SOI wafer 102. The interface is connected to the Sh-xGex layer (0&lt;χ&lt;1). That is, the Ge atoms in the Ge crystal layer ι 6 can be diffused to the SOI wafer 102 to form a SiGe layer. In this case, the crystallinity of the epitaxial layer formed over the Ge crystal layer 106 can be improved. Further, the average composition X of Ge in the Sh-xGex layer can be 60% or more in a region from the interface between the s〇I wafer 102 and the Ge crystal layer 106 of 5 nm or more and 1 〇 nm or less. In such a case, the crystallinity of the epitaxial layer formed on the Ge crystal layer 1 〇 6 can be particularly improved. In the present embodiment, the second compound semiconductor crystal 112 is a compound semiconductor in which the specific surface of the first compound semiconductor crystal 11〇 is a seed surface and is laterally grown along the barrier layer 1〇4, but the seed compound semiconductor The crystal 108 and the first compound semiconductor crystal 11〇 may also be a compound semiconductor crystal formed by a body. The second compound semiconductor crystal may be a compound semiconductor which is grown laterally on the barrier layer 1〇4 as a seed surface on the specific surface of the compound semiconductor crystal which is integrally formed as described above. The compound semiconductor crystal formed by the above-mentioned body may be a compound semiconductor crystal grown by using the crystal reed (10) as a core, and formed into a compound semiconductor crystal having a surface protruding from the surface of the barrier layer ι 4 321546 36 201019376. Thereby, at least a portion of the barrier layer 4 is formed between the second compound semiconductor crystal 112 and the insulating layer 164 of the wafer 102. An active element having an active region can be formed on the defect-free region of the second compound semiconductor crystal 112. The active device is, for example, a MISFEPMISFET having a barrier insulating film 114, a gate electrode 116, and a source/drain electrode 118. The MOSFET (Metal-〇xide_Semic〇nduct〇r)

Field-Effect Transistor;金屬氧化物半導體場效電晶 © 體）。主動元件亦可為HEMT。 阳 閘極絕緣膜114使閘極電極116與第二化合物半導體 結晶112電性絕緣。閘極絕緣膜114為例如：A1GaAs(砷 紹鎵）膜、AlInGaP(磷化鋁銦鎵）膜、氧化矽膜、氮化矽膜 氧化鋁膜、氧化鎵膜、氧化釓膜、氧化铪膜'、氧化錯膜、、 氧化鑭膜、以及此等絕緣膜的混合物或層積膜。 問極電極116為控制電極的一個例子。問極電極 ❹控制源極及沒極等之輸出入電極間的電流或電壓1 極116可包含：銘、銅、金、銀、銘、鶴等之金屬；2 =濃=的石夕等之半導體；氮化组;或 物（si 1icide)等。 ^ 源極Λ及極電極118為輸“f極的—個例子 汲極電極118分別與源極區 /原極. , 、 3及/及極區域拯叙 (contact)。源極/汲極電極118可包 我權 •銘、銅、金、如 鉑、鎢等之金屬或者經過高濃度摻 氮化组；或者金屬魏物等。 寻之牛導體； 321546 37 201019376 在源極/汲極電極118的下部，分別形成源極區域及汲 極區域。另外，位在閘極電極116的下部且形成源極區域 * 及汲極區域之間的通道區域之活性層，可為第二化合物半 導體結晶112本身，亦可為形成於第二化合物半導體結晶 112之上的層。在第二化合物半導體結晶112與活性層之 間，可形成緩衝層。活性層或缓衝層，可為GaAs層、InGaAs 層、AlGaAs層、InGaP層、ZnSe(砸化鋅）層等。 如第5圖所示，電子裝置100具有六個MISFET。六個 MISFET之中，三個三個一組，各組係藉由閘極電極116及 ❹ 源極/汲極電極118的配線而相互連接。另外，分別以形成 於SOI晶圓102之上的複數個Ge結晶層106的各個為核 而結晶成長成的第二化合物半導體結晶112，係在阻礙層 104之上互不相接而形成。 · 因為複數個第二化合物半導體結晶112互不相接而形 成，所以與鄰接的第二化合物半導體結晶112之間不會形 成界面。因此，不會有因該界面而發生之缺陷。形成於第 ◎ 二化合物半導體結晶112之上的主動元件，只要良好的結 晶性在其活性層實現的話，就不會發生因第二化合物半導 體結晶112不相接形成而產生的不良情形。 希望增加各主動元件的驅動電流時，就將各主動元件 例如並聯連接。另外，在第5至7圖中例示的電子裝置中， 係針對每個開口 105形成兩個MISFET分立於開口 105的兩 側。兩個MISFET可藉由化合物半導體層的蝕刻等之除去方 式或者離子注入等之不活性化方式使兩者相分離而形成。 38 321546 201019376 ' 本實施形態中，雖針對使Ge結晶層106選擇性地在開 、 口 105的内部成長而形成之情況進行說明，惟亦可藉由對 形成於S i結晶層16 6之上的Ge膜進行钱刻等使之圖案化 來形成Ge結晶層106。另外，本實施形態中，Ge結晶層 106雖形成於單一的Si結晶層166之上，惟Ge結晶層106 亦可形成於藉由蝕刻等而形成為單一的或相互分離的Si 結晶層166之上。藉此，將Ge結晶層106形成於例如形成 為島狀的Si結晶層166之上。結果，Ge結晶層106的邊 參緣部就會發揮作為缺陷捕捉部之功能。 本實施形態中，雖針對種子結晶層包含Ge結晶之情況 進行說明，惟種子結晶層亦可包含SixGeHCOSxd)。種子 結晶層亦可包含Si的含有率較低之SixGe!-x。種子結晶層 亦可包含在500°C以下的溫度形成之GaAs。此外，種子結 晶層亦可包含複數個層。 本實施形態中，雖針對Si晶圓162、絕緣層164、Si ©結晶層166、Ge結晶層106、以及與經過退火處理的Ge結 . 晶層106晶格匹配或準晶格匹配之化合物半導體，在與Si 晶圓162的主面172大致垂直的方向依上述順序配置之情 況進行說明，惟各部的位置關係並不限定於此。例如，化 合物半導體亦可與Ge結晶層106之與Si晶圓162的主面 172大致垂直的面之至少一個相接，而與Ge結晶層106晶 格匹配或準晶格匹配。此時，Ge結晶層106與化合物半導 體，係在與Si晶圓162的主面172大致平行的方向並排而 配置。 39 321546 201019376 另外，作為另一個例子，可在Si晶圓丨62的至少一部 份，使Si晶圓162、絕緣層164、以結晶層166、及阻礙 層104在與Si晶圓162的主s 172大致垂直的方向依上述 順序配置，使Si結晶層166、Ge結晶層1〇6、及化合物半 導體’在與主面172大致平行的方向依此順序配置。y結 晶層166可藉由蝕刻等而單一地或相互分離地配置在絕緣 層164之上。化合物半導體係與經過退火處理之以結晶層 106晶格匹配或準晶格匹配而形成。^結晶層166、以結 晶層106、以及上述化合物半導體，可配置在絕緣層⑻ 之上。 在此例令，阻礙層104可形成為覆蓋住&amp;結晶層166 之與Si晶圓162的主面172大致平行的面之形態。另外， 阻礙層104係形成為讓Si結晶層166之與&amp;晶圓162的 主面172大致垂直的面的至少一部份露出之形態。以結晶 層106可與Si結晶層166之與Si晶圓162的主面172大 致垂直的面之中未為阻礙層1(34所覆蓋的面相接而形成。 化合物半導體可與Ge結晶層⑽之與Si晶圓162的主面 172大致垂直的面的至少一個相接，而與以結晶層ι〇6晶 格匹配或準晶格匹配。另外，化合物半導體亦可盥以έ士晶 層1〇6之與si曰曰曰圓162的主面172 Α致平行的面相接;: 與Ge結晶層1 〇 6晶格匹配或準晶格匹配。 本實施形態中，雖然阻礙層104係形成於Si結晶層 166之上’Ge結晶層106係在形成於阻礙層1〇4之開口 1〇5 的内部形成’但並不限於此形態。阻礙層1〇4亦可在以結 321546 40 201019376 晶層106形成之後，才形成於Ge結晶層106所在區域以外 V 之區域。例如，電子裝置100可具備：以經過退火處理的 Ge結晶層106作為遮罩，使Si結晶層166熱氧化而形成 之阻礙層104。此時，阻礙層104係圍繞Ge結晶層106而 形成。 另外，電子裝置100可具備：與經過退火處理的Ge結 晶層106晶格匹配或準晶格匹配之化合物半導體。阻礙層 104可在使化合物半導體於Ge結晶層106上結晶成長之 ® 前，藉由熱氧化而設置。 第8至第12圖顯示電子裝置100之製造過程的斷面 例。第8圖顯示第5圖的A-A線斷面的製造過程的一部份 之斷面例。如第8圖所示，準備：在至少一部份的區域以 Si晶圓162、絕緣層164、Si結晶層166這樣的順序具備 有該Si晶圓162、絕緣層164及Si結晶層166之SOI晶 圓102。其次，將阻礙結晶成長之阻礙層104形成於SOI ^ 晶圓102的Si結晶層166上。阻礙層104係藉由CVD (Chemical Vapor Deposition)法、滅鍍法而形成。然後， 在阻礙層104形成到達SOI晶圓102之開口 105。開口 105 係藉由例如光刻法而形成。此外，阻礙層10 4亦可藉由對 S i結晶層16 6的一部份施行熱氧化來形成。Field-Effect Transistor; metal oxide semiconductor field effect crystal [body]. The active component can also be a HEMT. The positive gate insulating film 114 electrically insulates the gate electrode 116 from the second compound semiconductor crystal 112. The gate insulating film 114 is, for example, an A1GaAs (arsenic gallium) film, an AlInGaP (aluminum phosphide) film, a hafnium oxide film, a tantalum nitride film, a gallium oxide film, a hafnium oxide film, or a hafnium oxide film. , an oxidized film, a yttria film, and a mixture or laminated film of such insulating films. The pole electrode 116 is an example of a control electrode. The pole electrode ❹ controls the current or voltage between the source and the immersed electrode. The pole 1 may include: metal of Ming, copper, gold, silver, Ming, crane, etc.; 2 = concentrated = Shi Xi et al. Semiconductor; nitride group; or si 1icide. ^ Source Λ and pole electrode 118 are “f poles — an example of the drain electrode 118 and the source region / the primary pole. , , 3 and / and the polar region of the contact. Source / drain electrode 118 can include my rights, Ming, copper, gold, metals such as platinum, tungsten or the like, or a high concentration of nitrided groups; or metal Weiwu, etc. Seeking cattle conductor; 321546 37 201019376 at the source / drain electrode 118 The lower portion respectively forms a source region and a drain region. Further, an active layer located at a lower portion of the gate electrode 116 and forming a channel region between the source region* and the drain region may be the second compound semiconductor crystal 112 The layer itself may be a layer formed on the second compound semiconductor crystal 112. A buffer layer may be formed between the second compound semiconductor crystal 112 and the active layer, and the active layer or the buffer layer may be a GaAs layer or an InGaAs layer. , an AlGaAs layer, an InGaP layer, a ZnSe (zinc telluride) layer, etc. As shown in Fig. 5, the electronic device 100 has six MISFETs, three of the six MISFETs, each of which is controlled by a gate. The wiring of the electrode electrode 116 and the ❹ source/drain electrode 118 are connected to each other. Further, the second compound semiconductor crystals 112 which are crystallized and formed by the respective plurality of Ge crystal layers 106 formed on the SOI wafer 102 as a core are formed so as not to be in contact with each other on the barrier layer 104. Since the plurality of second compound semiconductor crystals 112 are not formed in contact with each other, an interface is not formed between the adjacent second compound semiconductor crystals 112. Therefore, defects due to the interface are not formed. The active element on the second compound semiconductor crystal 112 does not cause a problem due to the non-contact formation of the second compound semiconductor crystal 112 as long as good crystallinity is achieved in the active layer. It is desirable to increase the number of active elements. When the current is driven, the active elements are connected in parallel, for example. In addition, in the electronic device illustrated in FIGS. 5 to 7, two MISFETs are formed for each opening 105 on both sides of the opening 105. Two MISFETs may be used. It is formed by phase-separating the compound semiconductor layer by etching or the like, or inactivation by ion implantation, etc. 38 321546 201019 376 ' In the present embodiment, the case where the Ge crystal layer 106 is selectively grown inside the opening 105 is described, but the Ge formed on the Si crystal layer 16 6 may be used. The film is patterned by etching or the like to form a Ge crystal layer 106. Further, in the present embodiment, the Ge crystal layer 106 is formed on the single Si crystal layer 166, but the Ge crystal layer 106 may be formed by Etching or the like is formed as a single or mutually separated Si crystal layer 166. Thereby, the Ge crystal layer 106 is formed on, for example, an Si crystal layer 166 formed in an island shape. As a result, the edge portion of the Ge crystal layer 106 functions as a defect trapping portion. In the present embodiment, the case where the seed crystal layer contains a Ge crystal will be described, but the seed crystal layer may include SixGeHCOSxd). The seed crystal layer may also contain SixGe!-x having a low Si content. The seed crystal layer may also contain GaAs formed at a temperature below 500 °C. In addition, the seed crystal layer may also comprise a plurality of layers. In the present embodiment, the Si wafer 162, the insulating layer 164, the Si © crystal layer 166, the Ge crystal layer 106, and the compound semiconductor which is lattice-matched or quasi-lattice-matched with the annealed Ge junction. The case where the directions are substantially perpendicular to the main surface 172 of the Si wafer 162 in the above-described order will be described, but the positional relationship of each portion is not limited thereto. For example, the compound semiconductor may also be in contact with at least one of the faces of the Ge crystal layer 106 that are substantially perpendicular to the major surface 172 of the Si wafer 162, and may be lattice matched or quasi-lattice matched to the Ge crystal layer 106. At this time, the Ge crystal layer 106 and the compound semiconductor are arranged side by side in a direction substantially parallel to the main surface 172 of the Si wafer 162. 39 321546 201019376 In addition, as another example, the Si wafer 162, the insulating layer 164, the crystalline layer 166, and the barrier layer 104 may be in the main portion of the Si wafer 162 in at least a portion of the Si wafer 62. The substantially vertical direction of s 172 is arranged in the above-described order, and the Si crystal layer 166, the Ge crystal layer 1〇6, and the compound semiconductor ' are arranged in this order in a direction substantially parallel to the main surface 172. The yt crystalline layer 166 may be disposed on the insulating layer 164 singly or separately from each other by etching or the like. The compound semiconductor is formed by lattice matching or quasi-lattice matching of the crystal layer 106 after annealing. The crystal layer 166, the crystal layer 106, and the above compound semiconductor may be disposed on the insulating layer (8). In this example, the barrier layer 104 may be formed to cover a surface of the &amp; crystal layer 166 that is substantially parallel to the main surface 172 of the Si wafer 162. Further, the barrier layer 104 is formed in such a manner that at least a portion of the surface of the Si crystal layer 166 which is substantially perpendicular to the main surface 172 of the wafer 162 is exposed. The crystal layer 106 may be formed not to be in contact with the surface covered by the barrier layer 1 (the surface of the Si crystal layer 166 substantially perpendicular to the main surface 172 of the Si wafer 162. The compound semiconductor may be combined with the Ge crystal layer (10) At least one of the faces substantially perpendicular to the major surface 172 of the Si wafer 162 is in contact with the lattice layer or the quasi-lattice lattice matching with the crystal layer ι 6 . In addition, the compound semiconductor may also be a gentle layer 1 〇6 is in contact with the parallel surface of the main surface 172 of the Si曰曰曰 circle 162;: lattice matching or quasi-lattice matching with the Ge crystal layer 1 〇6. In the embodiment, the barrier layer 104 is formed. On the Si crystal layer 166, the 'Ge crystal layer 106 is formed inside the opening 1〇5 formed in the barrier layer 1〇4, but is not limited thereto. The barrier layer 1〇4 may also be in the junction 321546 40 201019376 After the formation of the crystal layer 106, it is formed in a region other than the region where the Ge crystal layer 106 is located. For example, the electronic device 100 may be configured to thermally oxidize the Si crystal layer 166 by using the annealed Ge crystal layer 106 as a mask. The barrier layer 104. At this time, the barrier layer 104 is formed to surround the Ge crystal layer 106. In addition, the electronic device 100 may include a compound semiconductor that is lattice-matched or pseudo-lattice-matched to the annealed Ge crystal layer 106. The barrier layer 104 may be used before the compound semiconductor is crystallized on the Ge crystal layer 106. It is provided by thermal oxidation. Figures 8 to 12 show cross-sectional examples of the manufacturing process of the electronic device 100. Fig. 8 shows a cross-sectional example of a part of the manufacturing process of the AA line cross-section of Fig. 5. As shown in FIG. 8, it is prepared to provide SOI crystals of the Si wafer 162, the insulating layer 164, and the Si crystal layer 166 in the order of at least a portion of the Si wafer 162, the insulating layer 164, and the Si crystal layer 166. Circle 102. Next, the barrier layer 104 which hinders crystal growth is formed on the Si crystal layer 166 of the SOI ^ wafer 102. The barrier layer 104 is formed by a CVD (Chemical Vapor Deposition) method or a de-plating method. The barrier layer 104 forms an opening 105 that reaches the SOI wafer 102. The opening 105 is formed by, for example, photolithography. Further, the barrier layer 104 can also be thermally oxidized by a portion of the Si layer 166. form.

第9圖顯示第5圖的A-A線斷面的製造過程之斷面 例。如第9圖所示，在開口 105中形成Ge結晶層106。藉 此，準備：在至少一部份，具備有依序為Si晶圓162、絕 緣層164、Si結晶層166、及Ge結晶層106的部件之SOI 41 321546 201019376 晶圓102 °Ge結晶層106可接受退火虚理。 第10圖顯示第5圖的A-A線斷面圖的製造過程的下一 步之斷面例。如第10圖所示，使種子化合物半導體处曰 ⑽以Ge結晶層⑽為核而形成到比阻礙層⑽的表面: 出。亦即，種子化合物半導體結晶⑽係形成為從阻礙層 104的表面突出之形態。 接著’以種子化合物半導體結晶108之預定的面作為 種子面而形成第-化合物半導體結晶11G。此階段之斷面 會隻知與第7圖-樣。形成GaAs來作為種子化合物半導體 結晶108及第—化合物半導體結日曰日11〇的一個例子之情 况，可利用MOCVD法或採用以有機金屬作為原料的ΜβΕ法 之磊晶成長法。此情況，在原料氣體方面，可利用 (trimethyl gal 1 ium，二甲基鎵）、AsH3(arsine ;神化氫） 等氣體。成長溫度可為例如6〇(rc以上7〇(rc以下。 第11圖顯示第5圖的a-a線斷面圖的製造過程的下一 歩之斷面例。如第11圖所示，第二化合物半導體結晶112， 係以弟一化合物半導體結晶的預定的面作為種子面， 而在阻礙層1〇4之上橫向成長。形成GaAs來作為第二化合 物半導體結晶112的一個例子之情況，可利用M〇CVD法或 採用以有機金屬作為原料的MBE法之磊晶成長法。此情 /兄’在原料氣體方面，可利用TM-Ga(trimethy 1 gal 1 ium)、 AsB3(arsine)等氣體。 要促進在例如（001)面上的橫向成長，較佳為在低溫成 長的條件下使結晶橫向成長。具體言之，可使結晶在7〇〇 42 321546 201019376 °(：以下的溫度條件，更佳為在65(Tc以下的溫度條件下成 長。在使結晶在例如&lt;Π〇&gt;方向橫向成長之情況，較佳為在Fig. 9 is a view showing a cross-sectional view of the manufacturing process of the A-A line section in Fig. 5. As shown in Fig. 9, a Ge crystal layer 106 is formed in the opening 105. Thereby, it is prepared to have at least a portion of the SOI 41 321546 201019376 wafer 102 ° Ge crystal layer 106 having the components of the Si wafer 162, the insulating layer 164, the Si crystal layer 166, and the Ge crystal layer 106 in sequence. Annealing acclusion can be accepted. Fig. 10 is a view showing a cross-sectional view of the next step of the manufacturing process of the cross-sectional view taken along line A-A of Fig. 5. As shown in Fig. 10, the seed compound semiconductor portion (10) is formed on the surface of the barrier layer (10) by using the Ge crystal layer (10) as a core: That is, the seed compound semiconductor crystal (10) is formed in a form protruding from the surface of the barrier layer 104. Next, the first compound semiconductor crystal 11G is formed by using a predetermined surface of the seed compound semiconductor crystal 108 as a seed surface. The section at this stage will only be known as Figure 7. In the case where GaAs is formed as an example of the seed compound semiconductor crystal 108 and the first compound semiconductor junction, the epitaxial growth method using the MOCVD method or the ΜβΕ method using an organic metal as a raw material can be used. In this case, gases such as (trimethyl gal 1 ium, dimethyl gallium) and AsH 3 (arsine; deuterated hydrogen) can be used as the raw material gas. The growth temperature may be, for example, 6 〇 (rc or more 7 〇 (rc or less. Fig. 11 is a cross-sectional view showing the next step in the manufacturing process of the aa cross-sectional view of Fig. 5. As shown in Fig. 11, the second compound The semiconductor crystal 112 is formed by using a predetermined surface of the crystal of the compound semiconductor as a seed surface and laterally growing on the barrier layer 1 to 4. As an example of the second compound semiconductor crystal 112, GaAs can be used. The 〇CVD method or the epitaxial growth method using the MBE method using an organic metal as a raw material. In this case, a gas such as TM-Ga (trimethy 1 gal 1 ium) or AsB3 (arsine) can be used as a raw material gas. To promote lateral growth on, for example, the (001) plane, it is preferred to grow the crystal laterally under conditions of low temperature growth. Specifically, the crystal can be crystallized at 7〇〇42 321546 201019376 ° (: below temperature conditions, more preferably It is grown at a temperature of 65 (Tc or less). In the case where the crystal is grown laterally, for example, in the &lt;Π〇&gt; direction, it is preferably

AsHs的分壓較高的條件下使結晶成長。更具體言之，較佳 為使結晶在AsHs的分壓在ixi〇-3atm以上的條件下成長。 藉此’可使&lt;110〉方向的成長速率比&lt;_11〇&gt;方向的成長速率 大。 第12圖顯示第5圖的a-A線斷面圖的製造過程的下一 歩之斷面例。如第12圖所示，在第二化合物半導體結晶 參112之上’依序形成將作為閘極絕緣膜114之絕緣膜、以 及將作為閘極電極116之導電膜。採用例如光刻法來使所 形成的導電膜及絕緣膜圖案化。藉此，形成閘極絕緣膜114 及閘極電極116。然後’形成將作為源極/汲極電極118之 導電膜。採用例如光刻法來使所形成的導電膜圖案化，就 得到第6圖所示之電子裝置1 〇〇。 第13及14圖顯示電子裝置1〇〇的其他製造過程之斷 ❿面例。如弟13圖所示，準備：在至少一部份的區域，以 Si晶圓162、絕緣層164、Si結晶層166、Ge結晶層106 這樣的順序具備有該Si晶圓162、絕緣層164、Si結晶層 、及Ge結晶層1〇6之SOI晶圓102。藉由蝕刻等使Ge 結晶層106圖案化，使之形成為單一或相分離的形狀。 例如’在SOI晶圓1〇2形成結晶性的Ge膜之後，藉由 餘刻該Ge膜到使之一部份殘存，而在s〇i晶圓1〇2的Si 、、’°郎層166之上形成Ge結晶層106。關於上述的蝕刻，可 利用例如光刻法。Ge結晶層106的最大寬度尺寸，可為5 321546 43 201019376 以下，較佳為2/^m以下。本說明書中，「寬度」表示 在與SOI晶圓1〇2之一側的主面大致平行的方向的長度。 如第14圖所示，在s〇I晶圓1〇2之形成了以結晶層 106的區域以外的區域形成阻礙層1〇[阻礙層1〇4係採用 例如將Ge結晶層1〇6用作為防止氧化的遮罩之局部氧化法 來加以形成。之後的工序，與第1〇圖以後的工序一樣。 第15圖顯示電子裝置2〇〇的平面例。第15圖中省略 了閘極電極及源極/汲極電極。電子裝置2〇〇中的第二化合 物半導體結晶112 ,可具有捕捉缺陷之缺陷捕捉部12〇。缺 陷捕捉部120可從形成以結晶層1〇6及種子化合物半導體 結晶108的所在之開π 1〇5作為起，點，而形成到第二化合 物半導體結晶112的端部。 缺陷捕捉部120之配置’係藉由例如以預定的配置形. 成開口 105來加以控制。此處，係依據電子裝置2〇〇的目 的來適宜地設計上述預定的配置。可形成複數個開口 1〇5。 而且，可等間隔形成上述複數個開口 1〇5。複數個開口 可依循規祕㈣成，勤周期性地形成。在複數個開口 105的每一個的内部形成種子化合物半導體結晶1〇8。 第16圖顯示電子裝置的平面例。第16圖中省略 了閘極電極及源極/汲極電極。電子裝置_中的第二化合 物半導體結晶112，除具有電子裝置2⑽中的缺陷觀^ 120之外還具有缺陷捕捉部13〇。缺陷捕捉部1加可 -化合物半導體結晶u〇的種子面或在阻礙層收以預定 的間隔形成的缺陷中心作為起點，而形成到第二化合物半 321546 201019376 導體結晶112的端部。 、 缺陷中心可藉由在種子面或阻礙層104形成物理性的 傷痕來生成。物理性的傷痕可藉由例如機械性的刮搔、摩 擦、或離子注入等來形成。此處’係依據電子裝置300的 目的來適宜地設計上述預定的間隔。可形成複數個上述的 缺陷中心。而且，可等間隔形成上述複數個缺陷中心。上 述複數個缺陷中心可依循規則性而形成，例如周期性地形 成。 © 缺陷捕捉部120及缺陷捕捉部130，可在第二化合物 半導體結晶112的結晶成長階段形成。藉由形成缺陷捕捉 部120及缺陷捕捉部130，可使存在於第二化合物半導體 結晶112的内部之缺陷集中到缺陷捕捉部12〇或缺陷捕捉 部130。結果，就可減低第二化合物半導體結晶112中之 缺陷捕捉部120及缺陷捕捉部130以外的區域的應力等， 而提咼結晶性。因此，可減低第二化合物半導體結晶112 ❹中之形成電子裝置的區域的缺陷。 在SOI晶圓1〇2的（1〇〇)面之上，使化合物半導體橫向 成長之情況，相較於使化合物半導體在s〇I晶圓1〇2的 &lt;0-11&gt;方向成長，使化合物半導體在矽晶圓的&lt;〇11&gt;方向成 長較為容易。使化合物半導體在s〇i晶圓102的&lt;0一丨丨〉方 向成長之情況，在橫向成長出來的化合物半導體的端面， 會出現化合物半導體之（111)B面。因為此（m)B面很安 定，所以容易形成平坦的面。因而，可在化合物半導體之 (111)B面上形成閘極絕緣膜、源極電極、閘極電極及汲極 321546 45 201019376 電極’而形成電子裝置。 另方面，使化合物半導體在SOI晶圓102的&lt;011〉 方向檢向成長之情況，在橫向成長出來的化合物半導體的 端面，會有化合物半導體之（111)β面反向呈現。此情況， 因為上側的（1〇〇)面有較廣的面積可用，所以可在（1〇〇)面 上形成電子裝置。另外，在SOI晶圓1G2的&lt;_&gt;方向及 1&gt;方向亦可以以較南的神化氫分廢條件使化 合物半導體横向成長。使化合物半導體在這些方向成長之 清況在棱向成長出來的化合物半導體的端面，容易出現 ，合物半導體之⑴0)面或⑽）面。在化合物半導體之此 等（110)面或（101)面之上，也能夠形成閘極絕緣膜、源極 電極閘極電極及沒極電極，而形成電子褒置。 第Π圖顯示電子裝置400輯面例。帛17.圖之斷面 例相當於第5圖中之A_A線斷面。電子農置棚除了具有 緩衝層402之外，可具有與電子裝置10G-樣的構成。 緩衝層402係與Ge結晶層106晶格匹配或準晶格匹 配。緩衝層402形成於Ge結晶層106與種子化合物半導體 結晶108之間。緩衝層4〇2可為含有？之πι ν族化合物 半導體層。緩衝層402可為InGaP㉟。InGaP層係藉由例 如蟲晶成長法而形成。The crystals grow under conditions of higher partial pressure of AsHs. More specifically, it is preferred that the crystal grows under the condition that the partial pressure of AsHs is ixi 〇 -3 atm or more. Thereby, the growth rate in the &lt;110&gt; direction can be made larger than the growth rate in the &lt;_11〇&gt; direction. Fig. 12 is a view showing an example of the next section of the manufacturing process of the cross-sectional view taken along line a-A of Fig. 5. As shown in Fig. 12, an insulating film which serves as the gate insulating film 114 and a conductive film which serves as the gate electrode 116 are sequentially formed on the second compound semiconductor crystallized portion 112. The formed conductive film and insulating film are patterned by, for example, photolithography. Thereby, the gate insulating film 114 and the gate electrode 116 are formed. Then, a conductive film to be used as the source/drain electrode 118 is formed. The formed conductive film is patterned by, for example, photolithography to obtain the electronic device 1 shown in Fig. 6. Figures 13 and 14 show examples of broken surfaces of other manufacturing processes of the electronic device. As shown in FIG. 13, it is prepared that the Si wafer 162 and the insulating layer 164 are provided in the order of at least a portion of the Si wafer 162, the insulating layer 164, the Si crystal layer 166, and the Ge crystal layer 106. The Si crystal layer and the SO crystal wafer 102 of the Ge crystal layer 1〇6. The Ge crystal layer 106 is patterned by etching or the like to form a single or phase separated shape. For example, 'after forming a crystalline Ge film on the SOI wafer 1〇2, by leaving the Ge film to a part, the Si, '° Lang layer on the s〇i wafer 1〇2 A Ge crystal layer 106 is formed over 166. Regarding the above etching, for example, photolithography can be used. The maximum width dimension of the Ge crystal layer 106 may be 5321546 43 201019376 or less, preferably 2/^m or less. In the present specification, "width" means a length in a direction substantially parallel to the main surface on one side of the SOI wafer 1〇2. As shown in Fig. 14, the barrier layer 1 is formed in a region other than the region in which the crystal layer 106 is formed on the wafer 〇1 wafer 2 [the barrier layer 1 〇 4 is used, for example, for the Ge crystal layer 1 〇 6 It is formed as a partial oxidation method of a mask for preventing oxidation. The subsequent steps are the same as the steps after the first drawing. Fig. 15 shows an example of the plane of the electronic device 2A. The gate electrode and the source/drain electrodes are omitted in Fig. 15. The second compound semiconductor crystal 112 in the electronic device 2 may have a defect capturing portion 12 that traps defects. The defect trapping portion 120 can be formed at an end portion of the second compound semiconductor crystal 112 from the point where the opening layer π 1 〇 5 where the crystal layer 1 〇 6 and the seed compound semiconductor crystal 108 are formed is formed. The configuration of the defect capturing portion 120 is controlled by, for example, forming the opening 105 in a predetermined configuration. Here, the predetermined configuration described above is appropriately designed in accordance with the purpose of the electronic device 2''. A plurality of openings 1 〇 5 can be formed. Further, the plurality of openings 1〇5 may be formed at equal intervals. A plurality of openings can be formed periodically according to the rules (four). Seed compound semiconductor crystals 1〇8 are formed inside each of the plurality of openings 105. Fig. 16 shows a plane example of the electronic device. The gate electrode and the source/drain electrodes are omitted in Fig. 16. The second compound semiconductor crystal 112 in the electronic device has a defect capturing portion 13A in addition to the defect view 120 in the electronic device 2 (10). The defect trapping portion 1 is formed by adding a seed surface of the compound semiconductor crystal u〇 or a defect center formed at a predetermined interval in the barrier layer as a starting point to the end portion of the second compound half 321546 201019376 conductor crystal 112. The defect center can be generated by forming a physical flaw on the seed surface or the barrier layer 104. Physical scratches can be formed by, for example, mechanical scraping, rubbing, or ion implantation. Here, the predetermined interval described above is appropriately designed in accordance with the purpose of the electronic device 300. A plurality of the above defect centers can be formed. Moreover, the plurality of defect centers described above can be formed at equal intervals. The plurality of defect centers described above may be formed in accordance with regularity, such as periodically. The defect capturing unit 120 and the defect capturing unit 130 can be formed in the crystal growth stage of the second compound semiconductor crystal 112. By forming the defect trap portion 120 and the defect trap portion 130, the defects existing inside the second compound semiconductor crystal 112 can be concentrated to the defect trap portion 12 or the defect trap portion 130. As a result, stress and the like in the regions other than the defect capturing portion 120 and the defect capturing portion 130 in the second compound semiconductor crystal 112 can be reduced, and the crystallinity can be improved. Therefore, the defects of the region in which the electronic device is formed in the second compound semiconductor crystal 112 可 can be reduced. On the (1 〇〇) plane of the SOI wafer 1 〇 2, the lateral growth of the compound semiconductor is compared with the growth of the compound semiconductor in the &lt;0-11&gt; direction of the 〇I wafer 1〇2, It is easier to grow the compound semiconductor in the &lt;〇11&gt; direction of the germanium wafer. When the compound semiconductor is grown in the &lt;0 丨丨&gt; direction of the s〇i wafer 102, the (111) B plane of the compound semiconductor appears on the end face of the compound semiconductor grown in the lateral direction. Since this (m) B plane is very stable, it is easy to form a flat surface. Therefore, an electronic device can be formed by forming a gate insulating film, a source electrode, a gate electrode, and a drain electrode 321546 45 201019376 on the (111) B surface of the compound semiconductor. On the other hand, when the compound semiconductor is detected to grow in the &lt;011&gt; direction of the SOI wafer 102, the (111) β plane of the compound semiconductor may be reversely present on the end face of the compound semiconductor grown in the lateral direction. In this case, since the upper (1 〇〇) plane has a wide area available, an electronic device can be formed on the (1 〇〇) plane. Further, in the &lt;_&gt; direction and the 1&gt; direction of the SOI wafer 1G2, the compound semiconductor can be laterally grown by the southerly deuterated hydrogen waste condition. The growth of the compound semiconductor in these directions is likely to occur on the end face of the compound semiconductor which grows in the rib direction, and the (1) 0) plane or the (10) plane of the compound semiconductor. On the (110) plane or the (101) plane of the compound semiconductor, a gate insulating film, a source electrode gate electrode, and a gate electrode can be formed to form an electron barrier. The figure shows an example of the surface of the electronic device 400.帛 17. Section of the figure The example corresponds to the A_A line section in Figure 5. The electronic farm can have a configuration similar to that of the electronic device 10G except for the buffer layer 402. Buffer layer 402 is lattice matched or quasi-lattice matched to Ge crystal layer 106. The buffer layer 402 is formed between the Ge crystal layer 106 and the seed compound semiconductor crystal 108. Buffer layer 4〇2 can be contained? Πι ν group compound semiconductor layer. The buffer layer 402 can be InGaP35. The InGaP layer is formed by, for example, a crystal growth method.

InGaP層亦可利用例如M〇CVD法或採用以有機金屬作 為原料的MBE法來形成。這些成長法中的原料氣體可採 用例如 TM-GaCtrimethyl gallium)、TM_In(trimethyl indlum ;三曱基銦）、pH3(ph〇sphine)。使 層磊晶成 321546 46 201019376 &quot; 長之情況，係在例如650°C之溫度形成結晶薄膜。藉由形 J 成緩衝層402，使得種子化合物半導體結晶108的結晶性 更加提南。 PH3處理的較佳處理溫度，可為例如500°c以上900°C 以下。比500°C低則處理的效果不會顯現，比900°C高則 Ge結晶層106會變質所以都不好。更佳的處理溫度，可為 例如600°C以上800°C以下。曝露處理（exposing treatment)，可藉由電蒙等使PH3活性化。 ® .緩衝層402’可為单一的層’亦可包含複數的層。緩 衝層402可在600°C以下，較佳為在550°C以下形成。如此， 種子化合物半導體結晶108的結晶性會提高。緩衝層402 可為在.600°C以下，較佳為550°C以下之溫度下形成的GaAs 層。緩衝層402亦可在400°C以上形成·。此情況，可藉由 氣體之P化合物對於Ge結晶層106之與緩衝層402相向的 面進行表面處理。 ^ 第18圖顯示電子裝置500的斷面例。第18圖之斷面 ❿ 例相當於第5圖中之A-A線斷面。電子裝置500的構成， 除了源極/汲極電極502的配置不同之外，可為與電子裝置 100 —樣的構成。在電子裝置500中，MISFET具有源極/ 没極電極118及源極/沒極電極5 0 2。 源極/淡極電極5 0 2為第一輸出入電極的一個例子。源 極/汲極電極118為第二輸出入電極的一個例子。如第18 圖所示，第二化合物半導體結晶112的成長面係為源極/ 汲極電極502所覆蓋。亦即，源極/汲極電極502亦形成於 47 321546 201019376 第二化合物半導體結晶112的側面。 藉由使源極/沒極電極502亦形成於第二化合物半導 體結晶112的側面，就可在與第二化合物半導體結晶⑴ 或形成其上的活性層（有時也稱為載子移動層）中之：子的 移動方向的延長線交叉的位置設置輸出人電極。藉此，載 子的移動會變得容易，電子裝置500的性能會提高\ 第19圖顯示電子裝置600的斷面例。第19圖之斷面 例相當於第5圖中之Α-Α線斷面。電子裝置_的構成， 除了源極/汲極電極602的配置不同之外，與電子裝置5〇〇 的構成-樣。在電子裝置_中，MISFET具有源極/沒極 電極602及源極/汲極電極502。 第二化合物半導體結晶112之開口 1〇5之上的區域， 係藉由例如蝕刻加以去除。如第19圖所示，經上述蝕刻而 路出之第二化合物半導體結晶112的侧面係為源極/汲極 電極602所覆蓋。藉此，電子裳置_中之載子的移動會 變得更各易，電子裝置6〇〇的性能會更為提高。此外，在 蝕刻Ge膜而形成Ge結晶膜1〇6之後才形成阻礙層1〇4之 情況，開口 105發揮作為Ge結晶膜106的形成區域之功能。 另外，源極/汲極電極602透過經蝕刻而露出之開口 1〇5内的種子化合物半導體結晶1〇8或Ge結晶膜1〇6而連 接至Si結晶層166。藉此，使MISFEt之一方的輸出入端 子維持在晶圓電位，可減低雜訊。 第20圖顯示電子裝置7〇〇的斷面例。第2〇圖之斷面 例相當於第5圖中之A-A線斷面。電子裝置700的構成， 321546 48 201019376 除了具備有下部閘極絕緣膜702及下部閘極電極7〇4之 • 外，與電子裝置100 —樣。 下部閘極電極704,係隔著第二化合物半導體結晶112 而與閘極電極116相向配置。下部閘極電極7〇4可形成於 阻礙層104的表面上形成之溝部中。下部閘極絕緣膜7〇2， 係形成於下部閘極電極704與第二化合物半導體結晶112 之間。 在電子裝置700中以如上所述的方式配置閘極電極 © 116及下部閘極電極704，即可簡便地實現雙閘極構造。藉 此’可提高閘極的控制性，使電子裝置700的開關 (switching)性能等提高。 第21圖顯示半導體晶圓801的平面圖。半導體晶圓 801係在SOI晶圓802之上具備有形成元件的區域803。區 域803係如圖所示’在s〇I晶圓802的表面配置複數個。 而且，區域8 0 3係等間隔配置。 q S01晶圓802等同於SOI晶圓102。亦即’在Si結晶 層166之上等間隔設置複數個Ge結晶層1〇6。 第22圖顯示區域803之一例。在區域803形成阻礙層 804。阻礙層804等同於電子裝置10〇的阻礙層1〇4。阻礙 層804為絕緣性的。阻礙層804係為例如氧化矽層、氮化 矽層、氮氧化矽層或氧化鋁層或將此等層加以層積而成的 層。開口 806等同於電子裴置1〇〇的開口 1〇5。亦即，開 口 806具有與開口 1〇5 一樣的深寬比及面積。阻礙層8〇4 係在SOI晶圓802之上形成有複數個。複數個阻礙層8〇4 49 321546 201019376 分別隔著間隔而配置。例如，阻礙層804係形成為—邊為 50 // m以上400 // m以下的正方形。此外’各個阻礙層 可相隔50 # m以上500 // m以下的間隔而形成，亦可等間隔 而形成。 在本實施形態之半導體晶圓801中，係在第22圖所示 的開口 806形成作為電子元件之異質接面雙極性電b曰曰體 (heterojunction bipolar transistor)(以下，有時稱之 為HBT)。包圍著開口 806而形成的阻礙層804之上，分別 形成有與HBT的集極連接之集極電極8〇8、與射極連接之 射極電極81G、以及與基極連接之基極電極812。其中，電 極可用配線或配線的打線接合墊(b〇nding 、加以代 替。另外’電子元件的-個例子之HBT，可在每一個開口 m形成-個。以_為例之電子元件可相互 並聯連接。 第23圖顯示半導體晶圓801輯面圖之一例，皇中同 時顯示形成於以阻礙層_加以被覆之區域（被覆區域）的 開口 806之HBT。半導體晶圓8〇1具備有s〇i晶圓纽、阻 礙層8〇4、以結晶層820、緩衝層822、及化合物半導體功 能層824。 SOI晶圓802在复$小— /、至夕一邛份之區域，以Si晶圓862 絕緣層864、Si結晶層^ &amp; — 增8bb故樣的順序具有該Si晶圓862The InGaP layer can also be formed by, for example, M〇CVD or an MBE method using an organic metal as a raw material. The raw material gases in these growth methods may be, for example, TM-GaCtrimethyl gallium), TM_In (trimethyl indlum; trimethyl indium), and pH 3 (ph〇sphine). The layer is epitaxially formed into 321546 46 201019376 &quot; In the long case, a crystalline film is formed at a temperature of, for example, 650 °C. By forming the buffer layer 402, the crystallinity of the seed compound semiconductor crystal 108 is further increased. The preferred treatment temperature for the PH3 treatment may be, for example, 500 ° C or more and 900 ° C or less. When the temperature is lower than 500 ° C, the effect of the treatment does not appear, and if it is higher than 900 ° C, the Ge crystal layer 106 is deteriorated, so that it is not good. A more preferable treatment temperature is, for example, 600 ° C or more and 800 ° C or less. In the exposing treatment, PH3 can be activated by electricity or the like. The buffer layer 402' may be a single layer' or may comprise a plurality of layers. The buffer layer 402 can be formed at 600 ° C or lower, preferably at 550 ° C or lower. Thus, the crystallinity of the seed compound semiconductor crystal 108 is improved. The buffer layer 402 may be a GaAs layer formed at a temperature of .600 ° C or lower, preferably 550 ° C or lower. The buffer layer 402 can also be formed at 400 ° C or higher. In this case, the surface of the Ge crystal layer 106 facing the buffer layer 402 may be surface-treated by a P compound of a gas. ^ Fig. 18 shows an example of a cross section of the electronic device 500. The section of Figure 18 ❿ is equivalent to the section A-A in Figure 5. The configuration of the electronic device 500 may be configured in the same manner as the electronic device 100 except that the arrangement of the source/drain electrodes 502 is different. In the electronic device 500, the MISFET has a source/nom electrode 118 and a source/nom electrode 5 0 2 . The source/light electrode 5 0 2 is an example of the first input/output electrode. The source/drain electrode 118 is an example of the second input/output electrode. As shown in Fig. 18, the growth surface of the second compound semiconductor crystal 112 is covered by the source/drain electrode 502. That is, the source/drain electrode 502 is also formed on the side of the 47321546, 201019376 second compound semiconductor crystal 112. By forming the source/dot electrode 502 on the side of the second compound semiconductor crystal 112, the active layer (also sometimes referred to as a carrier moving layer) on or formed with the second compound semiconductor crystal (1) In the middle: the position of the extension line of the moving direction of the child is set to the output person electrode. Thereby, the movement of the carrier becomes easy, and the performance of the electronic device 500 is improved. Fig. 19 shows an example of the cross section of the electronic device 600. The section of Fig. 19 is equivalent to the section of the Α-Α line in Fig. 5. The configuration of the electronic device _ is different from that of the electronic device 5 除了 except for the arrangement of the source/drain electrodes 602. In the electronic device, the MISFET has a source/no electrode 602 and a source/drain electrode 502. The region above the opening 1〇5 of the second compound semiconductor crystal 112 is removed by, for example, etching. As shown in Fig. 19, the side surface of the second compound semiconductor crystal 112 which is etched by the above etching is covered by the source/drain electrode 602. Thereby, the movement of the carrier in the electronic device will become more convenient, and the performance of the electronic device 6〇〇 will be further improved. Further, the barrier layer 1〇4 is formed after the Ge film is formed by etching the Ge film, and the opening 105 functions as a formation region of the Ge crystal film 106. Further, the source/drain electrode 602 is connected to the Si crystal layer 166 through the seed compound semiconductor crystal 1〇8 or the Ge crystal film 1〇6 in the opening 1〇5 exposed by etching. Thereby, the output of the MISFEt is maintained at the wafer potential, which reduces noise. Fig. 20 shows an example of a cross section of the electronic device 7A. The section of Fig. 2 corresponds to the section A-A in Fig. 5. The configuration of the electronic device 700, 321546 48 201019376, is the same as that of the electronic device 100 except that the lower gate insulating film 702 and the lower gate electrode 7〇4 are provided. The lower gate electrode 704 is disposed to face the gate electrode 116 via the second compound semiconductor crystal 112. The lower gate electrode 7〇4 may be formed in the groove formed on the surface of the barrier layer 104. The lower gate insulating film 7〇2 is formed between the lower gate electrode 704 and the second compound semiconductor crystal 112. In the electronic device 700, the gate electrode © 116 and the lower gate electrode 704 are arranged as described above, and the double gate structure can be easily realized. By this, the controllability of the gate can be improved, and the switching performance of the electronic device 700 can be improved. Figure 21 shows a plan view of a semiconductor wafer 801. The semiconductor wafer 801 is provided with a region 803 in which an element is formed on the SOI wafer 802. The area 803 is arranged as shown in the figure on the surface of the wafer 802. Moreover, the area 803 is arranged at equal intervals. q S01 wafer 802 is equivalent to SOI wafer 102. That is, a plurality of Ge crystal layers 1 〇 6 are disposed at equal intervals on the Si crystal layer 166. Fig. 22 shows an example of the area 803. A barrier layer 804 is formed in the region 803. The barrier layer 804 is equivalent to the barrier layer 1〇4 of the electronic device 10〇. The barrier layer 804 is insulative. The barrier layer 804 is, for example, a layer of a hafnium oxide layer, a tantalum nitride layer, a hafnium oxynitride layer or an aluminum oxide layer or a layer of these layers. The opening 806 is equivalent to the opening 1〇5 of the electronic device 1〇〇. That is, the opening 806 has the same aspect ratio and area as the opening 1〇5. The barrier layer 8〇4 is formed in a plurality on the SOI wafer 802. A plurality of barrier layers 8〇4 49 321546 201019376 are arranged at intervals. For example, the barrier layer 804 is formed as a square having a side of 50 // m or more and 400 // m or less. Further, the respective barrier layers may be formed at intervals of 50 #m or more and 500 // m or less, or may be formed at equal intervals. In the semiconductor wafer 801 of the present embodiment, a heterojunction bipolar transistor (hereinafter sometimes referred to as HBT) as an electronic component is formed in the opening 806 shown in FIG. ). On the barrier layer 804 formed around the opening 806, a collector electrode 8A8 connected to the collector of the HBT, an emitter electrode 81G connected to the emitter, and a base electrode 812 connected to the base are respectively formed. . Among them, the electrodes can be wired or wired with wire bonding pads (b〇nding, instead. In addition, 'HBT of an example of electronic components can be formed in each opening m. The electronic components in the example can be connected in parallel with each other. Fig. 23 shows an example of a top view of a semiconductor wafer 801. The middle and the middle show the HBT formed in the opening 806 of the region (covered region) covered by the barrier layer. The semiconductor wafer 8〇1 is provided with s〇 i wafer button, barrier layer 8〇4, crystal layer 820, buffer layer 822, and compound semiconductor functional layer 824. SOI wafer 802 is in the area of $ 小 / / / / , Si Si Si Si Si 862 Insulating layer 864, Si crystal layer ^ &amp; - Adding 8bb in the same order as the Si wafer 862

絕緣層864、及Si結晶層只狀c · H 日日禮866。Si晶圓862、絕緣層864， 及Si結晶層866，係等同於 於電子裝置100之Si晶圓162， 絕緣層164、及Si結晶層1 β。c. θ ^。^Λ 嘴ib6 si晶圓862包含有主面872&lt; 321546 50 201019376 — 主面872等同於Si晶圓162的主面172。 ' 阻礙層804形成於Si結晶層866之上，阻礙化合物半 導體功能層824的結晶成長。阻礙層804阻礙化合物半導 體功能層824的磊晶成長。阻礙層804等同於阻礙層104。 阻礙層804係設成覆蓋Si結晶層866的一部份。而 且，阻礙層804形成有貫通到Si結晶層866之開口 806。 阻礙層804的表面的形狀可為正方形。阻礙層804可在表 面的中心具有開口 806。阻礙層804可與Si結晶層866相 ®接而形成。The insulating layer 864 and the Si crystal layer are only c · H 日 日 866. The Si wafer 862, the insulating layer 864, and the Si crystal layer 866 are equivalent to the Si wafer 162 of the electronic device 100, the insulating layer 164, and the Si crystal layer 1β. c. θ ^. ^ 嘴 mouth ib6 si wafer 862 includes main surface 872 &lt; 321546 50 201019376 - main surface 872 is equivalent to main surface 172 of Si wafer 162. The barrier layer 804 is formed over the Si crystal layer 866 to hinder the crystal growth of the compound semiconductor functional layer 824. The barrier layer 804 hinders the epitaxial growth of the compound semiconductor functional layer 824. The barrier layer 804 is equivalent to the barrier layer 104. The barrier layer 804 is layered to cover a portion of the Si crystalline layer 866. Further, the barrier layer 804 is formed with an opening 806 penetrating through the Si crystal layer 866. The shape of the surface of the barrier layer 804 may be square. The barrier layer 804 can have an opening 806 in the center of the surface. The barrier layer 804 can be formed by bonding the Si crystal layer 866.

Ge結晶層820具有與Ge結晶層106 —樣的構成。例 如，Ge結晶層820係在阻礙層804的開口 806的内部結晶 成長而形成。Ge結晶層820係選擇性地在開口 806的内部 結晶成長。 阻礙層804阻礙Ge結晶在阻礙層804的表面之磊晶成 長。結果，阻礙層804的表面就不會有Ge結晶層820形成。 ^ 另一方面，因為在開口 806露出之Si結晶層866並不為阻 礙層804所覆蓋，所以在開口 806，Ge結晶層820會形成 於Si結晶層866之上。Ge結晶層820可與Si結晶層866 相接而形成，可與Si結晶層866之間隔著中間層而形成。 緩衝層822係與Ge結晶層820晶格匹配或準晶格匹 配。緩衝層822具有與缓衝層402 —樣的構成。緩衝層822 形成於Ge結晶層820與化合物半導體功能層824之間。緩 衝層822可為包含P之III-V族化合物半導體層。缓衝層 822係為例如InGaP層。InGaP層係藉由例如蟲晶成長法而 51 321546 201019376 形成。 -The Ge crystal layer 820 has a configuration similar to that of the Ge crystal layer 106. For example, the Ge crystal layer 820 is formed by crystal growth of the inside of the opening 806 of the barrier layer 804. The Ge crystal layer 820 selectively crystallizes and grows inside the opening 806. The barrier layer 804 hinders the epitaxial growth of the Ge crystal on the surface of the barrier layer 804. As a result, the surface of the barrier layer 804 is not formed by the Ge crystal layer 820. On the other hand, since the Si crystal layer 866 exposed at the opening 806 is not covered by the barrier layer 804, the Ge crystal layer 820 is formed over the Si crystal layer 866 at the opening 806. The Ge crystal layer 820 may be formed in contact with the Si crystal layer 866, and may be formed by interposing an intermediate layer with the Si crystal layer 866. Buffer layer 822 is lattice matched or quasi-lattice matched to Ge crystal layer 820. The buffer layer 822 has a configuration similar to that of the buffer layer 402. The buffer layer 822 is formed between the Ge crystal layer 820 and the compound semiconductor functional layer 824. The buffer layer 822 may be a III-V compound semiconductor layer containing P. The buffer layer 822 is, for example, an InGaP layer. The InGaP layer is formed by, for example, a crystal growth method 51 321546 201019376. -

InGaP層與S i結晶層86 6相接而蟲晶成長之情況， *When the InGaP layer is in contact with the S i crystal layer 86 6 and the crystal growth occurs, *

InGaP層並不在阻礙層804的表面形成，而是選擇性地在 Ge結晶層820的表面成長。作為緩衝層822的另一個例子， 緩衝層822可為在500°C以下的溫度在Si結晶層866之上 結晶成長而形成的GaAs層。另外，半導體晶圓801亦可不 包含緩衝層822。此時，Ge結晶層820之與化合物半導體 功能層824相向的面可接受以含有P之氣體進行之表面處 理。 ◎ 化合物半導體功能層824係與Ge結晶層820晶格匹配 或準晶格匹配。在化合物半導體功能層824形成例如HBT。 HBT為電子元件的一個例子。化合物半導體功能層824可 與Ge結晶層820相接而形成。亦即，化合物半導體功能層 824可Ge結晶層820相接而形成’或與Ge結晶層820之 間隔著緩衝層822而形成。化合物半導體功能層824可藉 由結晶成長而形成。例如，化合物半導體功能層824係藉 ❹ 由蠢晶成長而形成。 化合物半導體功能層824可為與Ge結晶層820晶格匹 配或準晶格匹配之III-V族化合物層或II-VI族化合物 層。化合物半導體功能層824可為與Ge結晶層820晶格匹 配或準晶格匹配之III-V族化合物層，且作為III族元素 者可包含Al、Ga、In中之至少一者，作為V族元素者可包 含N、P、As、Sb中之至少一者。例如，化合物半導體功能 層824係為GaAs層、或InGaAs層。 52 321546 201019376 在化合物半導體功能層824,形成作為電子元件之 • Ηβτ。關於在化合物半導體功能層824形成的電子元件，本 實施形態中雖舉ΗΒΤ為例，但電子元件並不限於ΗΒΤ，亦 可為發光二極體、高電子移動率電晶體（以下，有時稱之為 ΗΕΜΤ)、太能電池、薄膜感測器αΗη film sensor)。 在化合物半導體功能層824的表面，分別形成ΗΒΤ之 集極台面（mesa)、射極台面及基極台面。在集極台面、射 極台面及基極台面的表面’透過接觸孔（c〇ntact h〇le)而 ©形成集極電極808、射極電極81〇及基極電極812。化合物 半導體功能層824包含HBT的集極層、射極層及基極層。 亦即’集極層在緩衝層822之上形成，射極層在緩衝層822 與集極層之間形成，基極層在缓衝層822與射極層之間形 成。 . 集極層可為將載子濃度為3 〇xl〇18cnf3,膜厚5〇〇11111之 n GaAs層’與載子濃度為1. 〇xi〇i6cm_3,膜厚5〇〇nm之n-GaAs ❺層依所列順序層積而成的層積膜。射極層可為將載子濃度 為3. 0xl017cm_3 ’膜厚30nm之n—InGaAs層，與載子濃度為 3.0xl018cnf3，膜厚l〇〇nm之n+GaAs層，與載子濃度為 1. 0xl019cnT3，膜厚1〇〇 nm之η+InGaAs層依所列順序層積 而成的層積膜。基極層可為載子濃度為5. 0x1019cm-3，膜厚 50 nm之rTGaAs層。此處，載子濃度、膜厚之值係表示設 計值。 可在化合物半導體功能層824以外之Si層的至少一部 份’形成MISFET 880。MISFET 880係如第23圖所示，可 53 321546 201019376 具有阱（wei)882、及閘極電極888。第23圖中雖未顯示， 但可在阱882形成源極區域及汲極區域。另外，可在阱882 及閘極電極888之間形成閘極絕緣膜。 化合物半導體功能層824以外之Si層，可為si晶圓 862或Si結晶層866。MISFET 880可在Si結晶層866之 未為Ge結晶層8 2 0所覆蓋的區域形成。The InGaP layer is not formed on the surface of the barrier layer 804, but selectively grows on the surface of the Ge crystal layer 820. As another example of the buffer layer 822, the buffer layer 822 may be a GaAs layer formed by crystal growth on the Si crystal layer 866 at a temperature of 500 ° C or lower. In addition, the semiconductor wafer 801 may not include the buffer layer 822. At this time, the face of the Ge crystal layer 820 facing the compound semiconductor functional layer 824 can be subjected to surface treatment with a gas containing P. ◎ The compound semiconductor functional layer 824 is lattice-matched or pseudo-lattice matched to the Ge crystal layer 820. For example, an HBT is formed in the compound semiconductor functional layer 824. HBT is an example of an electronic component. The compound semiconductor functional layer 824 can be formed in contact with the Ge crystal layer 820. That is, the compound semiconductor functional layer 824 may be formed by the Ge crystal layer 820 being brought into contact with each other or with the buffer layer 822 interposed therebetween. The compound semiconductor functional layer 824 can be formed by crystal growth. For example, the compound semiconductor functional layer 824 is formed by the growth of a stupid crystal. The compound semiconductor functional layer 824 may be a III-V compound layer or a II-VI compound layer which is lattice-matched or quasi-lattice-matched to the Ge crystal layer 820. The compound semiconductor functional layer 824 may be a III-V compound layer that is lattice-matched or pseudo-lattice-matched to the Ge crystal layer 820, and may include at least one of Al, Ga, and In as a group III element, as a group V. The element may include at least one of N, P, As, and Sb. For example, the compound semiconductor functional layer 824 is a GaAs layer or an InGaAs layer. 52 321546 201019376 In the compound semiconductor functional layer 824, Ηβτ is formed as an electronic component. Although the electronic component formed in the compound semiconductor functional layer 824 is exemplified in the present embodiment, the electronic component is not limited to germanium, and may be a light emitting diode or a high electron mobility transistor (hereinafter sometimes referred to as It is ΗΕΜΤ), solar battery, film sensor αΗη film sensor). On the surface of the compound semiconductor functional layer 824, a collector mesa, an emitter mesa, and a base mesa are formed, respectively. On the surface of the collector mesa, the emitter mesa, and the base mesa, a collector electrode 808, an emitter electrode 81, and a base electrode 812 are formed through a contact hole. The compound semiconductor functional layer 824 includes a collector layer, an emitter layer, and a base layer of the HBT. That is, the collector layer is formed over the buffer layer 822, the emitter layer is formed between the buffer layer 822 and the collector layer, and the base layer is formed between the buffer layer 822 and the emitter layer. The collector layer may be an n-GaAs layer having a carrier concentration of 3 〇xl 〇18cnf3, a film thickness of 5〇〇11111, and an n-GaAs having a carrier concentration of 1. 〇xi〇i6cm_3 and a film thickness of 5 〇〇 nm. A laminated film in which the tantalum layers are laminated in the order listed. The emitter layer may be an n-InGaAs layer having a carrier concentration of 3.00xl017cm_3' film thickness of 30 nm, an n+GaAs layer having a carrier concentration of 3.0×10 018cnf3, a film thickness of l〇〇nm, and a carrier concentration of 1. 0xl019cnT3, a laminated film in which the η+InGaAs layer having a film thickness of 1 〇〇nm is laminated in the order listed. The base layer may be an rTGaAs layer having a carrier concentration of 5.0 x 1019 cm-3 and a film thickness of 50 nm. Here, the values of the carrier concentration and the film thickness indicate design values. The MISFET 880 can be formed in at least a portion of the Si layer other than the compound semiconductor functional layer 824. The MISFET 880 is shown in Fig. 23, and has a well 886 and a gate electrode 888. Although not shown in Fig. 23, the source region and the drain region may be formed in the well 882. Further, a gate insulating film can be formed between the well 882 and the gate electrode 888. The Si layer other than the compound semiconductor functional layer 824 may be a Si wafer 862 or an Si crystal layer 866. The MISFET 880 can be formed in a region of the Si crystal layer 866 that is not covered by the Ge crystal layer 820.

Si晶圓862可為單結晶y晶圓。此時，MiSFET 可在單結晶Si晶圓之未為Ge結晶層820及絕緣層864所 覆蓋的區域形成。此外，在Si晶圓862或Si結晶層866， 不僅可形成對S i進行加工而形成之主動元件、功能元件之 類的電子元件，亦可形成：在Si層之上形成的配線、包含 Si之配線、以及將上述部件加以組合而形成的電子電路、 以及 MEME(Micro Electro Mechanical System ;微機電系 統）至少一者。 本實施形態中，雖針對種子結晶層包含藉由結晶成長 而形成的Ge結晶之情況進行說明，但不限於此情況。與電 子裝置1〇〇的情況一樣，種子結晶層亦可為SixGei x(〇sx &lt;1)。種子結晶層亦可為Si的含有率低之SixGei-x。此外， 種子結晶層可包含在50(TC以下的溫度形成的GaAs。 第24圖顯示半導體晶圓11 〇 1的平面圖之一例。半導 體晶圓1101係在SOI晶圓11 〇2之上具備有孤立之島狀的 Ge結晶層1120。SOI晶圓11〇2係等同於電子裝置1〇〇的 SOI晶圓102或半導體晶圓801的SOI晶圓802。如第24 圖所示，Ge結晶層1120係在SOI晶圓1102的表面形成有 321546 54 201019376 ‘·複數個，且例如等間隔結晶成長而形成。本實施形態，係 顯示在Ge結晶層112〇之上形成Ηβτ作為電子元件的例 子。另外，WHBT為例之電子元件，可在每—個島狀的以 結晶層1120形成一個。電子元件可相互連接，也可並 接。The Si wafer 862 can be a single crystal y wafer. At this time, the MiSFET can be formed in a region of the single crystal Si wafer which is not covered by the Ge crystal layer 820 and the insulating layer 864. Further, in the Si wafer 862 or the Si crystal layer 866, not only an active element such as an active element or a functional element formed by processing Si, but also a wiring formed on the Si layer, including Si, may be formed. The wiring and the electronic circuit formed by combining the above components, and at least one of MEME (Micro Electro Mechanical System). In the present embodiment, the case where the seed crystal layer contains Ge crystal formed by crystal growth is described, but the present invention is not limited thereto. As in the case of the electronic device 1 ,, the seed crystal layer may also be SixGei x (〇sx &lt; 1). The seed crystal layer may also be SixGei-x having a low content of Si. Further, the seed crystal layer may include GaAs formed at a temperature of 50 TC or less. Fig. 24 shows an example of a plan view of the semiconductor wafer 11 。 1. The semiconductor wafer 1101 is isolated on the SOI wafer 11 〇 2 The island-shaped Ge crystal layer 1120. The SOI wafer 11〇2 is equivalent to the SOI wafer 102 of the electronic device 1 or the SOI wafer 802 of the semiconductor wafer 801. As shown in Fig. 24, the Ge crystal layer 1120 A plurality of 321546 54 201019376′· are formed on the surface of the SOI wafer 1102, and are formed by, for example, isocratic crystal growth. This embodiment shows an example in which Ηβτ is formed on the Ge crystal layer 112〇 as an electronic component. The WHBT is an electronic component as an example, and may be formed in each of the island-like crystal layers 1120. The electronic components may be connected to each other or may be connected in parallel.

Ge結晶層1120係等同於電子裝置1〇〇之以結晶層 106、或半導體晶圓801之Ge結晶層82〇。Ge結晶層1〇6 或Ge結晶層820，係選擇性地在開口 105或開口 806的内 ❹部成長。另-方面’ Ge結晶層1120則在：將以膜形成於 SOI μ圓11〇2之上後，藉由钱刻、機械性的刮搔、摩擦、 離子注入等而單一地或相互分離地形成之點，與以結晶層 106或Ge結晶層820不同。島狀的Ge結晶層1120，係單 一地或相互分離地形成的Ge結晶層之一例。島狀的.Ge結 晶層的界面會發揮作為缺陷捕捉部之功能。亦即，藉由對 Ge結晶層Π20進行退火處理，可減低Ge結晶層112〇内 φ 部的缺陷密度。 弟25圖顯示半導體晶圓iioi的斷面例，其中同時顯 不^/成於Ge結晶層1120之上的HBT。半導體晶圓iioi具 備有SOI晶圓11〇2、Ge結晶層1120、InGaP層1122、及 化合物半導體功能層H24。SOI晶圓H02具有Si晶圓 U62、絕緣層ι164、及Si結晶層1166。Si晶圓1162、絕 緣層1164、及Si結晶層1166，係等同於電子裝置100之 Sl晶圓162、絕緣層164、及Si結晶層166。Si晶圓1162 包含有主面1172。主面1172等同於Si晶圓162的主面172。 321546 55 201019376The Ge crystal layer 1120 is equivalent to the crystal layer 106 of the electronic device 1 or the Ge crystal layer 82 of the semiconductor wafer 801. The Ge crystal layer 1〇6 or the Ge crystal layer 820 selectively grows in the inner portion of the opening 105 or the opening 806. The other aspect of the 'Ge crystal layer 1120 is: after the film is formed on the SOI μ circle 11〇2, it is formed singly or separately by money etching, mechanical scraping, rubbing, ion implantation or the like. The point is different from the crystal layer 106 or the Ge crystal layer 820. The island-shaped Ge crystal layer 1120 is an example of a Ge crystal layer formed separately or separately from each other. The interface of the island-shaped .Ge junction layer functions as a defect trapping portion. That is, by annealing the Ge crystal layer Π20, the defect density of the φ portion in the Ge crystal layer 112 can be reduced. Figure 25 shows a cross-sectional view of a semiconductor wafer iioi in which HBT is formed on the Ge crystal layer 1120 at the same time. The semiconductor wafer iioi is provided with an SOI wafer 11 2, a Ge crystal layer 1120, an InGaP layer 1122, and a compound semiconductor functional layer H24. The SOI wafer H02 has a Si wafer U62, an insulating layer ι164, and an Si crystal layer 1166. The Si wafer 1162, the insulating layer 1164, and the Si crystal layer 1166 are equivalent to the Sl wafer 162 of the electronic device 100, the insulating layer 164, and the Si crystal layer 166. The Si wafer 1162 includes a major surface 1172. Main surface 1172 is equivalent to main surface 172 of Si wafer 162. 321546 55 201019376

Ge結晶層1120可在Si結晶層U66之上形成為孤立 的島狀。Ge結晶層1120可藉由在Si結晶層U66之上結 晶成長而形成。The Ge crystal layer 1120 may be formed as an isolated island shape over the Si crystal layer U66. The Ge crystal layer 1120 can be formed by crystal growth on the Si crystal layer U66.

InGaP層1122為緩衝層的一個例子。丨nGap層1122具 有與緩衝層822 —樣的構成。化合物半導體功能層1124具 有與化合物半導體功能層824 —樣的構成。 在化合物半導體功能層1124的表面，分別形成ΗβΤ之 集極台面、射極台面及基極台面。在集極台面、射極台面 及基極台面的表面，透過接觸孔（c〇ntact h〇le)而形成集 極電極1108、射極電極1110及基極電極1112。化合物半 導體功能層1124中包含HBT的集極層、射極層及基極層。 本實施形態中，雖針對種子結晶層包含Ge結晶之情況 進行說明，但與電子裝置1〇〇及半導體晶圓8〇1的情況一 樣’種子結晶層可包含SixGei-x(〇sx&lt;i)。種子結晶層亦可 為Si的含有率低之SixGei χ。此外，種子結晶層可包含在 500 C以下的溫度形成的（jaAs或in(；aAs層。另外，本實施 形態會在製造過程中形成InGaAs層1123及附隨層1125。 第26至30圖顯示半導體晶圓11〇1的製造過程之斷面 例如第26圖所示，準備：在至少一部份的區域具備有依 序為Si晶圓1162、絕緣層1164、及以結晶層1166的部 件之SOI aa圓1丨〇2。在Si結晶層1166的表面，藉由例如 磊晶成長法來形成Ge膜1130〇Ge膜1130亦可利用以GeH4 (鍺烷）作為原料氣體之CVD法或ΜβΕ法來形成。 如第27圖所示’藉由使Ge膜1130圖案化 321546 56 201019376 • (Patterning)，形成島狀的Ge結晶層1120。利用例如光 • 刻法來使Ge膜1130圖案化。 如第28圖所示，對於圖案化形成的Ge結晶層1120進 行退火處理。本實施形態中，對於經圖案化而形成為島狀 的Ge結晶層1120重複進行複數次兩階段之退火處理。藉 此’就可使在蠢晶成長或圖案化階段存在之缺陷，移動到 Ge結晶層112〇的邊緣部。 藉此’就可減低例如後來形成的磊晶薄膜中之由於晶 ❹圓材料而發生的缺陷。結果，形成於化合物半導體功能層 1124之電子元件的性能就會提高。 如第29圖所示，在Ge結晶層1120之上使結晶成長而 形成InGaP層1122。InGaP層1122可與Ge結晶層Π20相The InGaP layer 1122 is an example of a buffer layer. The 丨nGap layer 1122 has a configuration similar to that of the buffer layer 822. The compound semiconductor functional layer 1124 has a structure similar to that of the compound semiconductor functional layer 824. On the surface of the compound semiconductor functional layer 1124, a collector mesa, an emitter mesa, and a base mesa of ΗβΤ are formed, respectively. On the surfaces of the collector mesa, the emitter mesa, and the base mesa, a collector electrode 1108, an emitter electrode 1110, and a base electrode 1112 are formed through a contact hole. The compound semiconductor functional layer 1124 includes a collector layer, an emitter layer, and a base layer of the HBT. In the present embodiment, the case where the seed crystal layer contains the Ge crystal will be described. However, as in the case of the electronic device 1 and the semiconductor wafer 8〇1, the seed crystal layer may include SixGei-x (〇sx&lt;i) . The seed crystal layer may also be SixGei® having a low Si content. Further, the seed crystal layer may be formed at a temperature of 500 C or less (jaAs or in (; aAs layer. Further, in this embodiment, the InGaAs layer 1123 and the accompanying layer 1125 are formed in the manufacturing process. Figs. 26 to 30 show The cross section of the manufacturing process of the semiconductor wafer 11〇1 is as shown in FIG. 26, and is prepared to have, in at least a portion of the region, a Si wafer 1162, an insulating layer 1164, and a portion of the crystalline layer 1166. SOI aa circle 1 丨〇 2. On the surface of the Si crystal layer 1166, a Ge film 1130 〇 Ge film 1130 is formed by, for example, epitaxial growth method, and CVD method or ΜβΕ method using GeH4 (decane) as a material gas can also be used. As shown in Fig. 27, by patterning the Ge film 1130 by 321546 56 201019376 • (Patterning), an island-shaped Ge crystal layer 1120 is formed. The Ge film 1130 is patterned by, for example, photolithography. As shown in Fig. 28, the patterned Ge crystal layer 1120 is annealed. In the present embodiment, the Ge crystal layer 1120 formed into an island shape by patterning is repeatedly subjected to a plurality of two-stage annealing treatment. 'It can make the growth or patterning stage The defect existing in the segment moves to the edge portion of the Ge crystal layer 112. Thus, defects such as those occurring in the epitaxial film formed later can be reduced. As a result, the compound semiconductor functional layer 1124 is formed. The performance of the electronic component is improved. As shown in Fig. 29, the crystal is grown on the Ge crystal layer 1120 to form the InGaP layer 1122. The InGaP layer 1122 can be combined with the Ge crystal layer Π20.

接而形成。InGaP層1122可為緩衝層的一個例子。inGap 層1122可精由蠢晶成長法來形成。本實施形態中，在未形 成Ge結晶層1120之Si結晶層1166之上，也會形成InGaP ❹層1123。InGaP層1123的結晶性比InGaP層1122差，所 以並不在InGaP層1123之上形成電子元件。丨…沾層1123 係藉由例如姓刻來加以去除。Then formed. The InGaP layer 1122 can be an example of a buffer layer. The inGap layer 1122 can be formed by a stupid crystal growth method. In the present embodiment, the InGaP germanium layer 1123 is also formed on the Si crystal layer 1166 in which the Ge crystal layer 1120 is not formed. The crystallinity of the InGaP layer 1123 is inferior to that of the InGaP layer 1122, so that electronic components are not formed over the InGaP layer 1123.丨... The layer 1123 is removed by, for example, a surname.

InGaP層1122及InGaP層1123’係藉由例如MOCVD法 或以有機金屬作為原料的MBE法來磊晶成長生成。在原料 氣體方面，可利用 TM-Ga(trimethyl gallium)、TM-In (trimethyl indium)、PH3(phosphine)。InGaP 層之蟲晶成 長’係例如在650°C之高溫環境中讓結晶薄膜形成。 如第30圖所示，在InGaP層1122之上形成化合物半 57 321546 201019376 導體功能層1124。化合物半導體功能層1124係藉由例如 磊晶成長法而形成。化合物半導體功能層n24可與 層1122相接而形成。另外，在InGap層1123之上，會有 附隨層1125與化合物半導體功能層1124同時形成。附隨 層1125的結晶性比化合物半導體功能層1124差，所以並 不在附隨層1125之上形成電子元件。附隨層1125係藉由 例如#刻來加以去除。 化合物半導體功能層U24可為GaAs層、或包含inGaAs 等之GaAs系層積膜。GaAs層或GaAs系層積膜，可藉由例 如M0CVD法或以有機金屬作為原料的ΜβΕ法來使之磊晶成 長。在原料氣體方面，可利用TM—Ga(trimethyl galHum)、The InGaP layer 1122 and the InGaP layer 1123' are epitaxially grown by, for example, MOCVD or an MBE method using an organic metal as a raw material. As the raw material gas, TM-Ga (trimethyl gallium), TM-In (trimethyl indium), and PH3 (phosphine) can be used. The insect crystal growth of the InGaP layer is formed by, for example, forming a crystalline film in a high temperature environment of 650 °C. As shown in Fig. 30, a compound half 57 321546 201019376 conductor functional layer 1124 is formed over the InGaP layer 1122. The compound semiconductor functional layer 1124 is formed by, for example, an epitaxial growth method. The compound semiconductor functional layer n24 can be formed in contact with the layer 1122. Further, on the InGap layer 1123, an accompanying layer 1125 is formed simultaneously with the compound semiconductor functional layer 1124. The crystallinity of the accompanying layer 1125 is inferior to that of the compound semiconductor functional layer 1124, so that electronic components are not formed on the accompanying layer 1125. The accompanying layer 1125 is removed by, for example, #刻刻. The compound semiconductor functional layer U24 may be a GaAs layer or a GaAs-based laminated film including inGaAs or the like. The GaAs layer or the GaAs-based laminated film can be epitaxially grown by, for example, a M0CVD method or an 有机βΕ method using an organic metal as a raw material. In terms of raw material gases, TM-Ga (trimethyl galHum) can be used.

AsiKarsine)等之氣體。成長溫度為例如6〇〇。(：至65〇^。 在化合物半導體功能層1124形成Ηβτ等之電子元件，就得 到半導體晶圓1101。 在本實施形態，雖然針對在Ge結晶層1120形成後的 階段進行退火處理之情況進行說明，但亦可在InGap層 1122形成後的階段進行退火處理。亦即，在以結晶層 形成後，可先不進行退火處理而接著形成InGap層1122及 InGaP層1123。然後，可在形成InGap層1122及InGap層 1123後，才對Ge結晶層112〇、inGaP層1122及InGap層 1123進行退火處理。 第31圖顯不半導體晶圓12〇1之斷面例。半導體晶圓 1201與半導體晶圓1101幾乎一樣，但在：不使用以結晶 層1120,而使用在500。(：以下的溫度結晶成長成的GaAs 321546 58 201019376 •層，來作為形成於Si結晶層1166與化合物半導體機功層 1124之間的種子結晶層12〇2之點，與半導體晶圓ιι〇ι不 同。以下的說明’將以與半導體晶圓11()1不同之點為主來 進行說明。 第32及33圖顯示半導體晶圓12〇1的製造過程之斷面 例。如第32圖所示，準備S0I晶圓11〇2，並在5〇〇χ：以下 的溫度使GaAs層1204在SOI#曰圓11〇2的表面結晶成長。AsiKarsine) and other gases. The growth temperature is, for example, 6 〇〇. (: to 65 〇 ^. The semiconductor wafer 1101 is obtained by forming an electronic component such as Ηβτ in the compound semiconductor functional layer 1124. In the present embodiment, the case where the annealing treatment is performed in the stage after the Ge crystal layer 1120 is formed will be described. However, the annealing process may be performed after the formation of the InGap layer 1122. That is, after the formation of the crystal layer, the annealing process may be performed without subsequently forming the InGap layer 1122 and the InGaP layer 1123. Then, the InGap layer may be formed. After the 1122 and InGap layers 1123, the Ge crystal layer 112, the inGaP layer 1122, and the InGap layer 1123 are annealed. Fig. 31 shows a cross-section of the semiconductor wafer 12〇1. The semiconductor wafer 1201 and the semiconductor wafer 1101 is almost the same, but in the case where the crystal layer 1120 is not used, the layer of GaAs 321546 58 201019376 • which is crystallized at the following temperature is used as the layer formed on the Si crystal layer 1166 and the compound semiconductor machine layer 1124. The point of the seed crystal layer 12〇2 is different from that of the semiconductor wafer. The following description will be described focusing on the semiconductor wafer 11 (1). And Fig. 33 shows a cross-sectional view of the manufacturing process of the semiconductor wafer 12〇1. As shown in Fig. 32, the SOI wafer 11〇2 is prepared, and the GaAs layer 1204 is placed at SOI# at a temperature of 5 〇〇χ: The surface of the ellipse 11〇2 crystal grows.

GaAs層1204之形成，可利用例如M0CVD法或以有機金屬 ❹作為原料之MBE法。在原料氣體方面，可利用TE_Ga (triethyl gaiiium;三乙基鎵）、AsH3(arsine)cGaAs 層 1204的成長溫度可為例如45{rc。接著，如第33圖所示， 以例如光刻法對GaAs層1204進行蝕刻，形成孤立島狀的 種子結晶層1202·。之後的工序與半導體晶圓11〇1的製造 工序一樣。 第34圖顯示半導體晶圓1301之斷面例。半導體晶圓 ❿1301在：不使用Ge結晶層112〇，而以氣體之p化合物對 於SOI晶圓11〇2的表面施行表面處理之點，與半導體晶圓 1101不同。 第35圖顯示半導體晶圓1301的製造過程之斷面例。 如第35圖所示，對於SOI晶圓1102的表面施行例如pH3 之曝露處理。曝露處理，可在高溫環境下實施，且可藉由 電漿等使PH3活性化。PH3為氣體之P化合物的一個例子。 在實施過PH3之曝露處理的SOI晶圓1102的表面，使 例如GaAs膜結晶成長後，以光刻法對GaAs膜進行蝕刻， 59 321546 201019376 藉以形成孤立島狀的化合物半導體功能層1124。此外，亦 可在以氣體之P化合物對於Si晶圓的表面施行表面處理 後，形成在500°C以下的溫度形成之GaAs層來作為種子結 晶層。藉此，使化合物半導體功能層1124的結晶性提高。 [實施例] (實施例1) 依照第8至9圖所示之程序，製作出在SOI晶圓1〇2 之上具備有形成有開口 1〇5的阻礙層104、及在開口 1〇5 的内部結晶成長成的Ge結晶層106之半導體晶圓。在SOI 晶圓102之上製作出25000個Ge結晶層106。另外，依照 第8至12圖所示之程序，在各個上述Ge結晶層106製作 出電子裝置100。如此，製造出25000個電子裝置。 採用早結晶Si晶圓來作為SOI晶圓102之Si晶圓 162。以CVD法形成si〇2來作為阻礙層104後’以光刻法在 阻礙層104形成開口 1〇5。使開口 105的深寬比為1。使用 GeH4作為原料氣體而以CVD法形成Ge結晶層106。使Ge 結晶層106之與SOI晶圓102的表面大致平行的方向之最 大寬度為2/zm。形成Ge結晶層106之後，實施：重複進 行以800°C進行1〇分鐘的高溫退火處理、及以680。(：進行 10分鐘的低溫退火處理之兩階段退火處理。實施十次上述 兩階段退火處理。按照以上的程序獲得上述半導體晶圓。 在上述半導體晶圓的Ge結晶層106之上，形成GaAs 結晶來作為種子化合物半導體結晶108、第一化合物半導 體結晶110及第二化合物半導體結晶112。GaAs結晶，係 60 321546 201019376 ' 使用TM-Ga及AsH3作為原料氣體，且令成長溫度為650°C， * 而以M0CVD法來使之結晶成長。第二化合物半導體結晶 112，係令AsH3的分壓為lxl(T3atm而使之結晶成長。在第 二化合物半導體結晶112之上，形成高電阻AlGaAs之閘極 絕緣膜114、Pt(鉑）之閘極電極116、及W(鎢）之源極/汲 極電極118而得到電子裝置100。 在形成有Ge結晶層106之半導體晶圓，檢查是否有形 成於Ge結晶層106的表面之缺陷。檢查係以蝕孔法實施。 ❿ 結果，並未在Ge結晶層106的表面發現缺陷。另外，檢查 十個電子裝置100看看其中是否有貫穿缺陷。檢查係以利 用TEM進行之面内斷面觀察來實施。結果，經發現有貫穿 缺陷之電子裝置100為0個。 根據本實施形態，在深寬比為（，3)/3以上的開口 105 形成Ge.結晶層10 6 ’所以可在形成Ge結晶層10 6的時點’ 形成具有結晶性良好的表面之Ge結晶層106。另外，根據 Λ 本實施形態，對Ge結晶層106施行退火處理，可更加提高 ❿For the formation of the GaAs layer 1204, for example, an M0CVD method or an MBE method using an organometallic ruthenium as a raw material can be used. In terms of the material gas, the growth temperature of the TE_Ga (triethyl gaiiium; triethylgallium) or AsH3 (arsine) cGaAs layer 1204 can be, for example, 45 {rc. Next, as shown in Fig. 33, the GaAs layer 1204 is etched by, for example, photolithography to form an isolated island-shaped seed crystal layer 1202·. The subsequent steps are the same as the manufacturing process of the semiconductor wafer 11〇1. Fig. 34 shows an example of a cross section of the semiconductor wafer 1301. The semiconductor wafer ❿1301 is different from the semiconductor wafer 1101 in that the surface of the SOI wafer 11 〇 2 is surface-treated with the p compound of the gas without using the Ge crystal layer 112 。. Fig. 35 shows a cross-sectional view of the manufacturing process of the semiconductor wafer 1301. As shown in Fig. 35, the surface of the SOI wafer 1102 is subjected to an exposure treatment such as pH3. The exposure treatment can be carried out in a high temperature environment, and the PH3 can be activated by plasma or the like. PH3 is an example of a P compound of a gas. After the GaAs film is crystal grown on the surface of the SOI wafer 1102 subjected to the exposure treatment of PH3, the GaAs film is etched by photolithography, and 59 321546 201019376 is formed to form an isolated island-shaped compound semiconductor functional layer 1124. Further, a surface of the Si wafer may be subjected to surface treatment with a gas P compound to form a GaAs layer formed at a temperature of 500 ° C or lower as a seed crystal layer. Thereby, the crystallinity of the compound semiconductor functional layer 1124 is improved. [Embodiment] (Embodiment 1) According to the procedure shown in Figs. 8 to 9, the barrier layer 104 having the opening 1〇5 formed on the SOI wafer 1〇2 and the opening 1〇5 are formed. The internal crystal is grown into a semiconductor wafer of Ge crystal layer 106. 25,000 Ge crystal layers 106 are formed on the SOI wafer 102. Further, the electronic device 100 is fabricated in each of the Ge crystal layers 106 in accordance with the procedure shown in Figs. In this way, 25,000 electronic devices were manufactured. An early crystalline Si wafer is used as the Si wafer 162 of the SOI wafer 102. After si 〇 2 is formed by the CVD method as the barrier layer 104, an opening 1 〇 5 is formed in the barrier layer 104 by photolithography. The aspect ratio of the opening 105 is made 1. The Ge crystal layer 106 is formed by a CVD method using GeH4 as a material gas. The maximum width of the Ge crystal layer 106 in a direction substantially parallel to the surface of the SOI wafer 102 is 2/zm. After the Ge crystal layer 106 is formed, it is carried out by repeating the high temperature annealing treatment at 800 ° C for 1 minute and at 680. (: a two-stage annealing treatment of a low-temperature annealing treatment for 10 minutes. The above two-stage annealing treatment is performed ten times. The semiconductor wafer is obtained according to the above procedure. On the Ge crystal layer 106 of the semiconductor wafer, GaAs crystal is formed. The seed compound semiconductor crystal 108, the first compound semiconductor crystal 110, and the second compound semiconductor crystal 112. GaAs crystal, 60 321546 201019376 'Use TM-Ga and AsH3 as raw material gases, and let the growth temperature be 650 ° C, * The second compound semiconductor crystal 112 is obtained by the M0CVD method, and the partial pressure of AsH3 is lxl (T3atm to crystallize and grow. On the second compound semiconductor crystal 112, a gate of high-resistance AlGaAs is formed. The insulating film 114, the gate electrode 116 of Pt (platinum), and the source/drain electrode 118 of W (tungsten) are used to obtain the electronic device 100. In the semiconductor wafer on which the Ge crystal layer 106 is formed, it is checked whether or not it is formed. The defect of the surface of the Ge crystal layer 106. The inspection was performed by the etching method. ❿ As a result, no defects were found on the surface of the Ge crystal layer 106. In addition, ten electric charges were examined. The apparatus 100 looks at whether or not there is a through defect. The inspection is performed by in-plane cross-sectional observation by TEM. As a result, it is found that there are zero electronic devices 100 through the defect. According to the present embodiment, the aspect ratio is The opening 105 of (3)/3 or more forms the Ge. crystal layer 106', so that the Ge crystal layer 106 having a surface having good crystallinity can be formed at the time point of forming the Ge crystal layer 106. Further, according to the present embodiment By annealing the Ge crystal layer 106, the ruthenium can be further improved.

Ge結晶層106的結晶性。由於Ge結晶層106的結晶性提 高，因此以Ge結晶層106為核之種子化合物半導體結晶 108、以種子化合物半導體結晶108的特定面作為種子面之 第一化合物半導體結晶110、以及以第一化合物半導體結 晶110的特定面作為種子面之第二化合物半導體結晶112 的結晶性會提高。 藉由以上的構成，使在第二化合物半導體結晶112之 上形成的電子裝置100的活性層的結晶性提高，在屬於低 61 321546 201019376 價的晶圓之SOI晶圓102之上形成的電子裝置100的性能 也就提高了。此外，根據本實施形態之電子裝置100，在 形成於SOI晶圓102之上之第二化合物半導體結晶112形 成電子元件，因此電子裝置100的寄生電容會減低，因而 電子裝置100的動作速度會提高。而且，可減少流到Si晶 圓16 2之漏電流。 (實施例2) 如以下所述製作具備有2500個區域803之半導體晶圓 801。採用單結晶Si晶圓來作為SOI晶圓802之Si晶圓 862。以CVD法形成氧化矽之阻礙層804後，以光刻法形成 開口 806。使開口 806的深寬比為1。使開口 806的形狀形 成為一邊為100# m的正方形。相鄰的開口 806相互之間係 隔著500 // m的間隔而配置。在開口 806的内部形成Ge結 晶層820。Ge結晶層820，係使用GeH4作為原料氣體而以 M0CVD法加以形成。使Ge結晶層820之與SOI晶圓802的 表面大致平行的方向之最大寬度為2/zm。形成Ge結晶層 820之後，實施：重複進行以800°C進行2分鐘的高溫退火 處理、及以68CTC進行2分鐘的低温退火處理之兩階段退 火處理。實施十次上述兩階段退火處理。 針對形成有Ge結晶層820之半導體晶圓801，檢查是 否有形成於Ge結晶層820的表面之缺陷。檢查係以蝕孔法 實施。結果，並未在Ge結晶層的表面發現缺陷。根據以上 的結果可知：使Ge結晶層820選擇性地在由阻礙層804所 區劃出來的開口 806的内部成長，並對Ge結晶層820施行 62 321546 201019376 • f數次兩階段的退火處理，會使Ge結晶層82G的結晶性 *高。再者，藉由形成論P層來作為緩衝層822，可得 具有結晶性良好之作為化合物半導體功能層824的G展 之半導體晶圓801。 ’ 接著’同樣地使用形成的半導體晶圓8G1來製作 裝置。電子裝置係如以下所述般製作。在各個區域8〇3的 Ge結晶層820之上，形成Ιη(ί.緩衝層奶。緩衝層咖， 如㈣感作為㈣氣體，且令成長溫度 為650 C，而以MOCVD法來加以形成。 cm— 在緩衝層822之上，依序形成載子漠度為3〇χΐ〇]8 3,膜厚SOOmn之n+GaAs層，以及載子濃度為Η# 二，5GGnm之n’GaAs層’來作為腿的集極層。在 术之上，形成載子濃度為5. 〇xl〇1W3，膜厚5〇咖之 ’來作為hbt的基極層。在基極層之上，依序形 度為3. 0咖W，膜厚3-之n-InGap層，及載 ·。副％'膜厚100nm之n+GaAS層，以及載子 二-為 1.0Xlrcm'膜厚 1〇〇nm 之 η+ί 的射極層。此處，載子濃度、膜厚之值係/示設= 物本=可形成包含有基極層、射極層、集極層之化合 係使用功Γ能層824。基極層、射極層、集極層之GaAS層， ; a及AsH3作為原料氣體，且令成長溫度為650 拉s M M〇CVD法來加以形成。然後，藉由钱刻，形成基 处曰 '射極層、及集極層電極連接部。在化合物半導體功 4的表面，形成集極電極、射極電極&quot;ο、及基 321546 63 201019376 極電極812，而製作出HBT。關於射極層及集極層，係以真 · 空蒸艘法蒸鑛AuGeNi(金鍺鎳）層來形成。關於基極層，係 ’ 以真空蒸鑛法蒸鑛AuZn(金鋅）層來形成。然後，藉由在氫 氣環境中以420°C施行10分鐘的熱處理，來形成各電極。 使各電極與上述驅動電路電性連接，而製作出電子裝置。 藉此，可製作小型且消耗電力少之電子裝置。而且， 以掃描式電子顯微鏡（以下，有時稱之為SEM)觀察化合物 半導體功能層824的表面，並未在表面發現//m等級（order) 的凹凸。 ❹ (實施例3) 製作在Si結晶層866與Ge結晶層820之間具備有作 為緩衝層之在500 C以下的溫度形成的GaAs層之半導體晶 圓801。上述半導體晶圓801，除了在Si結晶層866與Ge 結晶層820之間形成缓衝層之外，以與實施例2 —樣的方 式製作。作為缓衝層之GaAs層，係使用TM-Ga及AsEb作為 原料氣體，且令成長溫度為450°C，而以M0CVD法來形成。Crystallinity of the Ge crystal layer 106. Since the crystallinity of the Ge crystal layer 106 is improved, the seed compound semiconductor crystal 108 having the Ge crystal layer 106 as a core, the first compound semiconductor crystal 110 having a specific surface of the seed compound semiconductor crystal 108 as a seed surface, and the first compound The crystallinity of the second compound semiconductor crystal 112 as the seed surface on the specific surface of the semiconductor crystal 110 is improved. With the above configuration, the crystallinity of the active layer of the electronic device 100 formed on the second compound semiconductor crystal 112 is improved, and the electronic device formed on the SOI wafer 102 belonging to the wafer having a low price of 61,321,546 and 201019376 is formed. The performance of 100 is also improved. Further, according to the electronic device 100 of the present embodiment, since the second compound semiconductor crystal 112 formed on the SOI wafer 102 forms an electronic component, the parasitic capacitance of the electronic device 100 is reduced, and thus the operating speed of the electronic device 100 is improved. . Moreover, the leakage current flowing to the Si crystal circle 16 2 can be reduced. (Example 2) A semiconductor wafer 801 having 2,500 regions 803 was produced as follows. A single crystal Si wafer is used as the Si wafer 862 of the SOI wafer 802. After the barrier layer 804 of yttrium oxide is formed by a CVD method, an opening 806 is formed by photolithography. The aspect ratio of the opening 806 is made 1. The shape of the opening 806 is formed into a square having a side of 100# m. Adjacent openings 806 are arranged at intervals of 500 // m between each other. A Ge crystal layer 820 is formed inside the opening 806. The Ge crystal layer 820 is formed by a MOSCVD method using GeH4 as a material gas. The maximum width of the Ge crystal layer 820 in a direction substantially parallel to the surface of the SOI wafer 802 is 2/zm. After the formation of the Ge crystal layer 820, a two-stage annealing treatment at a high temperature annealing treatment at 800 ° C for 2 minutes and a low temperature annealing treatment at 68 CTC for 2 minutes was repeated. The above two-stage annealing treatment was carried out ten times. For the semiconductor wafer 801 on which the Ge crystal layer 820 is formed, it is checked whether or not there is a defect formed on the surface of the Ge crystal layer 820. The inspection was carried out by the etch method. As a result, defects were not found on the surface of the Ge crystal layer. According to the above results, it is known that the Ge crystal layer 820 is selectively grown inside the opening 806 partitioned by the barrier layer 804, and the Ge crystal layer 820 is subjected to two stages of annealing treatment of 62 321546 201019376 • f. The crystallinity* of the Ge crystal layer 82G is made high. Further, by forming the P layer as the buffer layer 822, a semiconductor wafer 801 having a high crystallinity as the compound semiconductor functional layer 824 can be obtained. Then, the formed semiconductor wafer 8G1 was used in the same manner to fabricate the device. The electronic device was fabricated as described below. On the Ge crystal layer 820 of each region 8〇3, Ιη (ί buffer layer milk, buffer layer coffee, such as (4) sensible as (4) gas, and a growth temperature of 650 C, was formed by MOCVD. Cm—On the buffer layer 822, a n+GaAs layer with a carrier mobility of 3〇χΐ〇]8 3, a film thickness of SOOmn, and a carrier concentration of Η#2, 5GGnm n'GaAs layer are sequentially formed. Comes as the collector layer of the leg. On the top of the surgery, the carrier concentration is 5. 〇xl〇1W3, and the film thickness is 5 〇 来 as the base layer of hbt. On the base layer, in order The degree is 3.0 coffee W, the film thickness 3-n-InGap layer, and the carrier. The %%' film of n+GaAS layer with a thickness of 100 nm, and the carrier 2- is 1.0Xlrcm' film thickness of 1 nm. The emitter layer of η+ί. Here, the value of the carrier concentration and the film thickness is / shown = the volume of the material = the formation of the base layer, the emitter layer, and the collector layer 824. The base layer, the emitter layer, the collector layer of the GaAS layer, a and AsH3 are used as raw material gases, and the growth temperature is formed by a 650 s MM CVD method. Then, by engraving, a base is formed. At the 'electrode layer, and the collector layer a pole connecting portion. On the surface of the compound semiconductor work 4, a collector electrode, an emitter electrode &quot;, and a base 321546 63 201019376 pole electrode 812 are formed, and an HBT is formed. The emitter layer and the collector layer are true. · An empty steaming method is used to form a layer of AuGeNi (gold-nickel-nickel). With regard to the base layer, it is formed by steaming an AuZn (gold-zinc) layer by vacuum distillation. Then, by using 420 in a hydrogen atmosphere. Each electrode is formed by heat treatment for 10 minutes at ° C. The electrodes are electrically connected to the drive circuit to fabricate an electronic device, thereby making it possible to manufacture an electronic device that is small and consumes less power. The surface of the compound semiconductor functional layer 824 was observed by a microscope (hereinafter sometimes referred to as SEM), and no unevenness of /m order was observed on the surface. ❹ (Example 3) Fabrication of Si crystal layer 866 and Ge crystal A semiconductor wafer 801 having a GaAs layer formed at a temperature of 500 C or less as a buffer layer is provided between the layers 820. The semiconductor wafer 801 has a buffer layer formed between the Si crystal layer 866 and the Ge crystal layer 820. In addition, with Example 2 The GaAs layer as a buffer layer was formed by M0CVD using TM-Ga and AsEb as source gases and having a growth temperature of 450 °C.

Q 藉此，可使化合物半導體功能層824的結晶性提高。 (實施例4) 製作以PH3氣體對Ge結晶層820的表面進行過處理之 半導體晶圓801。上述半導體晶圓801，除了並未使用InGaP 之缓衝層822、以及以PH3氣體對Ge結晶層820之與化合 物半導體功能層824相向的面進行處理後才形成化合物半 導體功能層824之點外，以與實施例2 —樣的方式製作。 藉此，可使化合物半導體功能層824的結晶性提高。 64 321546 201019376 (實施例5) • 依照第26至30圖所示之程序，製作出半導體晶圓 1101。採用單結晶Si晶圓來作為SOI晶圓1102之Si晶圓 1162。在SOI晶圓之上形成Ge膜1130。Ge膜1130，係使 用GeH4作為原料氣體而以M0CVD法來形成。以光刻法使Ge 膜1130圖案化，而形成島狀的Ge結晶層1120。使Ge結 晶層1120的大小為邊長15 /i m之方形，且以50 // m之間隔 等間隔配置。形成Ge結晶層1120之後，實施··重複進行 ❹ 以800°C進行10分鐘的高溫退火處理、及以680°C進行10 分鐘的低溫退火處理之兩階段退火處理。實施十次上述兩 階段退火處理。 針對形成有Ge結晶層1120之半導體晶圓1101，檢查 是否有形成於Ge結晶層1120的表面之缺陷。檢查係以蝕 孔法實施。結果，並未在Ge結晶層1120的表面發現缺陷。 接著，與實施例2之情況一樣，在Ge結晶層1120之 我上形成HBT，而製作出電子裝置。藉此，可製作出小型且 ❿ 消耗電力少之電子裝置。另外，以SEM觀察化合物半導體 功能層1124的表面，並未在表面發現/zm等級的凹凸。 (實施例6) 除了形成Ge結晶層1120之後，還以800°C實施20分 鐘的高溫退火處理以外，與實施例5 —樣，製作形成有Ge 結晶層1120之半導體晶圓1101。針對上述半導體晶圓 1101，檢查是否有形成於Ge結晶層1120的表面之缺陷。 檢查係以蝕孔法實施。結果，並未在Ge結晶層1120的表 65 321546 201019376 面發現缺陷。 接著，與實施例2之情況一樣，在Ge結晶層1120之 上形成HBT，而製作出電子裝置。藉此，可製作出小型且 消耗電力少之電子裝置。另外，以SEM觀察化合物半導體 功能層1124的表面，並未在表面發現/zm等級的凹凸。 (實施例7) 在形成Ge結晶層1120之後，實施：重複進行以900 °C進行10分鐘的高溫退火處理、及以780°C進行10分鐘 的低溫退火處理之兩階段退火處理。除了實施十次上述兩 階段退火處理之外，與實施例5 —樣，製作形成有Ge結晶 層1120之半導體晶圓1101。針對上述半導體晶圓1101， 檢查是否有形成於Ge結晶層1120的表面之缺陷。檢查係 以蝕孔法實施。結果，並未在Ge結晶層1120的表面發現 缺陷。 接著，與實施例2之情況一樣，在Ge結晶層1120之 上形成HBT，而製作出電子裝置。藉此，可製作出小型且 消耗電力少之電子裝置。另外，以SEM觀察化合物半導體 功能層1124的表面，並未在表面發現em等級的凹凸。 (實施例8) 第36圖係在實施例8至實施例16使用之半導體晶圓 的斷面的不意圖。該半導體晶圓具備有Si晶圓2102、阻 礙層2104、Ge結晶層2106、及化合物半導體2108。化合 物半導體2108係包含例如種子化合物半導體結晶108。Si 晶圓2102可指SOI晶圓中之Si結晶層。此處，SOI晶圓 66 321546 201019376 ’ 以基底晶圓、絕緣層、Si結晶層這樣的順序具有該基底晶 ' 圓、絕緣層及Si結晶層。 第37至41圖顯示退火處理溫度與Ge結晶層2106的 平坦性之關係。第37圖顯示未退火處理之Ge結晶層2106 的斷面形狀。第38圖、第39圖、第40圖及第41圖分別 顯示以700°C、800°C、850°C、900°C實施退火處理之情況 之Ge結晶層2106的斷面形狀。Ge結晶層2106的斷面形 狀係以雷射顯微鏡加以觀察。各圖的縱軸表示在與Si晶圓 ® 2102的主面垂直的方向之距離，表示Ge結晶層2106的膜 厚。各圖的橫轴表示在與Si晶圓2102的主面平行的方向 之距離。 各圖中，Ge結晶層2106係以以下的程序形成。首先， 以熱氧化法在Si晶圓2102的表面形成Si〇2層之阻礙層 2104 ,然後在阻礙層2104形成被覆區域及開口。阻礙層 2104的外形與被覆區域的外形相同。Si晶圓2102係使用 _ 市售的單結晶Si晶圓。被覆區域的平面形狀，為一邊的長 度為400 # m之正方形。其次，以CVD法使Ge結晶層2106 選擇性地在開口的内部成長。 從第37至41圖可知：退火處理溫度越低Ge結晶層 2106的表面的平坦性越良好。而且可知：尤其是在退火處 理溫度不到900°C之情況，Ge結晶層2106的表面顯現出良 好的平坦性。 (實施例9) 製作具備有Si晶圓2102、阻礙層2104、Ge結晶層 67 321546 201019376 2106、及作為元件形成層而發揮功能的化合物半導體2108 之半導體晶圓，調查在形成於阻礙層21〇4之開口 1〇5的内 部成長之結晶的成長速度、與被覆區域的大小及開口 1〇5 的大小之關係。實驗係藉由改變形成於阻礙層21〇4之被覆 區域的平面形狀及開口 1〇5的底面形狀，然後對於在一定 時間的期間成長之化合物半導體21G8的膜厚進行量測而 實施。 首先’以以下的程序’在Si晶圓2102的表面，形成 被覆區域及開口 1〇5。以晶圓_的-個例子，係使用市 售的單結晶si晶圓。以熱氧化法，在Si晶圓聰的表面， 形成作為阻礙層2104的一個例子之Si〇2層。 —對上述Si〇2層進行姓刻，形成預定大小的祕層。預 層、:係形成三個以上。此時’係設計成預定 1〇2層的平面形狀都為相同大小的正方形。另外， 在3正方形的Sl02層的中心，形成預定大小 ^開:挪。此時’係設計成預定大小的正方形抓層的 每:個2開：：5的中心一致。上述正方形的Si〇2層的 正方二.Π:個，105。本說明書中，有時將上述 度。 ㈣長度，稱為被覆區域的-邊的長 其次’以MOCVD法，使G紝曰 述開口哪成長。麵魏衫:二06選擇性地在上 體的流量及成膜時間，係=二用獅。原料氣 M〇⑽法，形成作別6又疋為设定的值。接著，以 成作為化合物半導體⑽的-個例子之GaAs 321546 68 201019376 結晶。以620 C ’ 8 Mpa之條件，使GaAs結晶在門口 的内部之Ge結晶層2106的表面磊晶成長。在原料氣1〇5 面’係使用三甲基鎵（trimethyl gal 1 ium)及石申化氫；方 (arsine)。原料氣體的流量及成膜時間，係分別設定為# 定的值。 形成化合物半導體2108之後，對於化合物半導體21〇8 的膜厚進行量測。化合物半導體2108的膜厚，係以針式段 差計（KLA Tencor 公司製 ’ Surface Profiler P-10)，量 ® 測化合物半導體2108的三個量測點的膜厚，然後將該三處 的膜厚加以平均而算出。此時，也將該三個量測點的膜厚 的標準偏差算出。上述膜厚，亦可藉由以穿透式電子顯微 鏡或掃描式電子顯微鏡進行之斷面觀察法，直接量測化合 物半導體2108的三個量測點的膜厚，然後將該三處的膜厚 加以平均來算出。 依照以上的程序’針對將被覆區域的一邊的長度設定 ❹為5〇#111、100_、2〇〇以111、300//111、400&quot;111或 500/^之 各個情況’改變開口 1 〇5的底面形狀，而量測化合物半導 體2108的膜厚。針對開口 1〇5的底面形狀為一邊為1〇 的正方形、一邊為20//m的正方形、短邊為30 長邊為 40 Am的長方形之三種情況進行實驗。 此外’在被覆區域的一邊的長度為5〇〇# m之情況，係 一體地开&gt;成複數個上述正方形的Si〇2層。此情況，一邊的 長度為500 /zm之被覆區域雖然並非以5〇〇//m間隔配置， 但為了方便起見’將之表示為被覆區域的一邊的長度為5〇〇 69 321546 201019376 個被覆區 _之情況。另外，為了方便起見，將鄰接的 域之間的距離表示為Oem。 將實施例9的實驗結果顯示於第42及 =實=之各情況中之化合物半導體21〇8的膜厚2 ㈣°第43圖顯示實施例9之各情況中之化合物半導體 2108的膜厚的變動係數。 等體 第42圖顯示化合物半導體21〇8的成 區朗^及開口_大小之_。第4_，縱= =在一疋％間的期間成長出的化合物半導體2⑽的膜厚 [A]，橫軸表示被覆區域的_邊的長度[口]。本實施例中， 口為化。物半導體纖⑽厚係在—料 .出的膜厚，所以將賴厚除以該_，就得聽合物^ 體2108的成長速度的近似值。 /第42圖中’菱形的描緣點（Pkt)表示開口 1〇5的底面 形狀為-邊為的正方形之情況的實驗數據，四角形 的描繪點表示開口 105的底面形狀為-邊為20_的正方 形之情況的實驗數據。同圖中，三角形的财點表示開口 的底面形狀為長邊為仙❹短邊為心⑺的長方形之 情況的實驗數據。 仗第42圖可知：上述成長速度係隨著被覆區域的大小 =大而單調地增加。此外，可知：上述成長速度在被覆區 、的邊的長度在400# m以下之情況，係呈大致線性地增 而因開σ 1〇5 #底面开》狀所引起的變動的情形很小。 了知.相較於被覆區域的一邊的長度在400# m 321546 70 201019376 •以下之情況，被覆區域的-邊的長度為5〇〇“m之情況的成 長速度呈現急遽的增加，而因開口 1〇5的底面形狀所引起 的變動的情形也變大。因此，阻礙層之與Si結晶層平行的 面上之最大寬度，以在400/zm以下為佳。 第43 ®顯示化合物半導體21〇8的成長速度的變動係 數、與相鄰接的兩個被覆區域之間的距離之關係。此 變動係數係指標準偏差相對於平均值之比，可將上述三個 量測點力膜厚的標準偏差除以該膜厚的平肖值而算出。第 43圖中’縱軸表示在—定時_期間成長出的化合物半導 體2108的膜厚[人]的變動係數，橫軸表示相鄰接的被覆區 域之間的距離Um]。第43圖顯示相鄰接的兩個被覆區域 之間的距離為 bm、2Mm、5〇#m、1〇Mm、2〇〇_、_ f'、400#m及450&quot;m之情況的實驗數據。第“圖中， 菱形的描緣點表示開口 1()5的底面形狀為一邊為的 正方形之情況的實驗數據。 ❿ 第43圖中，相鄰接的兩個被覆區域之間的距離為〇 #ra、100’、200 //m、心、棚㈣及彻_之實驗 數據’係分別對應於第42圖中之被覆 長 刷—·„、2一、斷…二 況的貫驗數據。相鄰接的兩個被覆區域之間的距離為2〇 ’及50_之數據’係按照與其他的實驗數據一樣的程 序’分=針對被覆區域的-邊的長度為彻⑽及彻_ 之情況量測化合物半導體21〇8的膜厚而獲得。 從第4 3圖可知：相較於相鄰接的兩個被覆區域之間的 71 321546 201019376 3為〇_之情況’在上述距離為2〇//m之情況，化合物 丰導體2108的成長速度非常地穩定。從上述結果，可知： 在相鄰接的兩個被覆區域只是分開一點點的情況，在開口 105的内部成長之結晶的成長速度也會穩定化。此外，可 知：在相鄰接的兩個被覆區域之間配置讓結晶成長的區 域，上述結晶的成長速度就會穩定化。另外，可知：即使 是相鄰接的兩個被覆區域之間的距離為Mm之情況，也可Q Thereby, the crystallinity of the compound semiconductor functional layer 824 can be improved. (Example 4) A semiconductor wafer 801 in which the surface of the Ge crystal layer 820 was treated with a PH3 gas was produced. The semiconductor wafer 801 is formed by using the buffer layer 822 of InGaP and the surface of the Ge crystal layer 820 facing the compound semiconductor functional layer 824 with PH3 gas to form the compound semiconductor functional layer 824. It was produced in the same manner as in Example 2. Thereby, the crystallinity of the compound semiconductor functional layer 824 can be improved. 64 321546 201019376 (Embodiment 5) • A semiconductor wafer 1101 is fabricated in accordance with the procedure shown in FIGS. 26 to 30. A single crystal Si wafer is used as the Si wafer 1162 of the SOI wafer 1102. A Ge film 1130 is formed over the SOI wafer. The Ge film 1130 is formed by a MOCVD method using GeH4 as a material gas. The Ge film 1130 is patterned by photolithography to form an island-shaped Ge crystal layer 1120. The size of the Ge crystal layer 1120 is a square having a side length of 15 /i m and is arranged at equal intervals of 50 // m. After the formation of the Ge crystal layer 1120, the ruthenium was subjected to a high-temperature annealing treatment at 800 ° C for 10 minutes and a two-stage annealing treatment at 680 ° C for 10 minutes. Ten of the above two-stage annealing treatments were carried out ten times. For the semiconductor wafer 1101 in which the Ge crystal layer 1120 is formed, it is checked whether or not there is a defect formed on the surface of the Ge crystal layer 1120. The inspection was carried out by the etch method. As a result, no defects were found on the surface of the Ge crystal layer 1120. Next, as in the case of Example 2, an HBT was formed on the Ge crystal layer 1120 to fabricate an electronic device. As a result, an electronic device that is small and consumes less power can be produced. Further, the surface of the compound semiconductor functional layer 1124 was observed by SEM, and no unevenness of /zm grade was observed on the surface. (Example 6) A semiconductor wafer 1101 in which a Ge crystal layer 1120 was formed was produced in the same manner as in Example 5 except that the Ge crystal layer 1120 was formed and a high temperature annealing treatment was performed at 800 °C for 20 minutes. With respect to the above-described semiconductor wafer 1101, it is checked whether or not there is a defect formed on the surface of the Ge crystal layer 1120. The inspection is carried out by the etch method. As a result, defects were not found on the surface of the Ge crystal layer 1120 at 65 321546 201019376. Next, as in the case of Example 2, an HBT was formed on the Ge crystal layer 1120 to fabricate an electronic device. Thereby, an electronic device that is small and consumes less power can be produced. Further, the surface of the compound semiconductor functional layer 1124 was observed by SEM, and no unevenness of /zm grade was observed on the surface. (Example 7) After forming the Ge crystal layer 1120, a two-stage annealing treatment of a high-temperature annealing treatment at 900 ° C for 10 minutes and a low-temperature annealing treatment at 780 ° C for 10 minutes was repeated. A semiconductor wafer 1101 in which a Ge crystal layer 1120 was formed was produced in the same manner as in Example 5 except that the above two-stage annealing treatment was carried out ten times. For the semiconductor wafer 1101 described above, it is checked whether or not there is a defect formed on the surface of the Ge crystal layer 1120. The inspection is carried out by the etch method. As a result, no defects were found on the surface of the Ge crystal layer 1120. Next, as in the case of Example 2, an HBT was formed on the Ge crystal layer 1120 to fabricate an electronic device. Thereby, an electronic device that is small and consumes less power can be produced. Further, the surface of the compound semiconductor functional layer 1124 was observed by SEM, and em-level irregularities were not observed on the surface. (Embodiment 8) Figure 36 is a schematic view showing a cross section of a semiconductor wafer used in Embodiments 8 to 16. The semiconductor wafer is provided with an Si wafer 2102, a barrier layer 2104, a Ge crystal layer 2106, and a compound semiconductor 2108. The compound semiconductor 2108 contains, for example, a seed compound semiconductor crystal 108. The Si wafer 2102 can refer to a Si crystalline layer in an SOI wafer. Here, the SOI wafer 66 321546 201019376 ' has the base crystal 'circle, the insulating layer, and the Si crystal layer in the order of the base wafer, the insulating layer, and the Si crystal layer. Figures 37 to 41 show the relationship between the annealing treatment temperature and the flatness of the Ge crystal layer 2106. Figure 37 shows the cross-sectional shape of the unannealed Ge crystal layer 2106. Figs. 38, 39, 40, and 41 show the cross-sectional shape of the Ge crystal layer 2106 in the case where annealing treatment is performed at 700 °C, 800 °C, 850 °C, and 900 °C, respectively. The cross-sectional shape of the Ge crystal layer 2106 was observed by a laser microscope. The vertical axis of each graph indicates the distance in the direction perpendicular to the main surface of the Si wafer ® 2102, and indicates the film thickness of the Ge crystal layer 2106. The horizontal axis of each figure indicates the distance in the direction parallel to the main surface of the Si wafer 2102. In each of the figures, the Ge crystal layer 2106 is formed by the following procedure. First, a barrier layer 2104 of Si 2 layer is formed on the surface of the Si wafer 2102 by thermal oxidation, and then a barrier region and an opening are formed in the barrier layer 2104. The outer shape of the barrier layer 2104 is the same as the outer shape of the covered region. The Si wafer 2102 is a commercially available single crystal Si wafer. The planar shape of the covered area is a square having a length of 400 #m. Next, the Ge crystal layer 2106 is selectively grown inside the opening by the CVD method. As is apparent from the graphs 37 to 41, the lower the annealing treatment temperature, the better the flatness of the surface of the Ge crystal layer 2106. Further, it is understood that the surface of the Ge crystal layer 2106 exhibits good flatness particularly in the case where the annealing treatment temperature is less than 900 °C. (Example 9) A semiconductor wafer including a Si wafer 2102, a barrier layer 2104, a Ge crystal layer 67 321546 201019376 2106, and a compound semiconductor 2108 functioning as an element formation layer was produced, and it was investigated that it was formed on the barrier layer 21. The relationship between the growth rate of the internal growth crystal of the opening 1〇5 of 4, the size of the coating area, and the size of the opening 1〇5. The experiment was carried out by changing the planar shape of the covering region formed in the barrier layer 21〇4 and the shape of the bottom surface of the opening 1〇5, and then measuring the film thickness of the compound semiconductor 21G8 which was grown for a certain period of time. First, a coating region and an opening 1〇5 are formed on the surface of the Si wafer 2102 by the following procedure. In the case of wafers, a commercially available single crystal Si wafer was used. An Si 2 layer as an example of the barrier layer 2104 is formed on the surface of the Si wafer by thermal oxidation. - The above-mentioned Si〇2 layer is engraved to form a secret layer of a predetermined size. The pre-layer, the system is formed by three or more. At this time, the plan is designed such that the planar shapes of the predetermined layers are all squares of the same size. In addition, in the center of the 3 square S02 layer, a predetermined size is formed. At this time, the center of each of the squares of the predetermined size is designed to be uniform. The square of the Si〇2 layer of the above square is two squares, 105. In this manual, the above degree is sometimes used. (4) The length, which is called the length of the side of the covered area. Next, by the MOCVD method, let G say which opening grows. Face Wei shirt: 2 06 selectively in the upper body flow and film formation time, the system = two with a lion. The raw material gas M〇(10) method forms the value of the setting 6 and the setting. Next, GaAs 321546 68 201019376, which is an example of the compound semiconductor (10), is crystallized. The GaAs crystal was epitaxially grown on the surface of the Ge crystal layer 2106 inside the gate at 620 C ' 8 Mpa. In the raw material gas 1〇5 surface, trimethyl gallium (trimethyl gal 1 ium) and shishen hydrogen; arsine are used. The flow rate of the material gas and the film formation time are set to values of #. After the formation of the compound semiconductor 2108, the film thickness of the compound semiconductor 21〇8 was measured. The film thickness of the compound semiconductor 2108 is measured by a needle-type step (KLA Tencor Corporation's Surface Profiler P-10), and the film thickness of the three measurement points of the compound semiconductor 2108 is measured, and then the film thicknesses of the three places are measured. Calculated by averaging. At this time, the standard deviation of the film thicknesses of the three measurement points was also calculated. The film thickness can be directly measured by a cross-sectional observation method by a transmission electron microscope or a scanning electron microscope, and the film thicknesses of the three measurement points of the compound semiconductor 2108 can be directly measured, and then the film thicknesses of the three places are measured. Calculate by averaging. According to the above procedure, 'the length of one side of the covered area is set to 5 〇 #111, 100_, 2 〇〇 to 111, 300//111, 400 &quot; 111 or 500 / ^ each case 'change opening 1 〇 5 The bottom surface shape is measured while the film thickness of the compound semiconductor 2108 is measured. The experiment was carried out for the case where the shape of the bottom surface of the opening 1〇5 was a square having a side of 1 、, a square having a side of 20//m, and a short side having a length of 30 and a long side of 40 Am. Further, in the case where the length of one side of the covered region is 5 〇〇 #m, the Si 〇 2 layer of the above plurality of squares is integrally opened. In this case, although the coated area having a length of 500 /zm on one side is not arranged at intervals of 5 〇〇//m, for the sake of convenience, 'the length of one side of the covered area is 5〇〇69 321546 201019376. District _ the case. In addition, for the sake of convenience, the distance between adjacent domains is expressed as Oem. The results of the experiment of Example 9 are shown in the film thickness of the compound semiconductor 21A8 in the case of the 42nd and the == (4). FIG. 43 shows the film thickness of the compound semiconductor 2108 in each case of the embodiment 9. Coefficient of variation. Etc. Figure 42 shows the composition of the compound semiconductor 21〇8 and the size of the opening_size. 4th, vertical = = film thickness [A] of the compound semiconductor 2 (10) grown during a period of 疋%, and the horizontal axis represents the length [mouth] of the _ side of the covered region. In this embodiment, the port is simplified. Since the semiconductor fiber (10) is thick and thick, the thickness of the film is increased. Therefore, by dividing the thickness of the semiconductor fiber by _, the approximate value of the growth rate of the compound 2108 is obtained. / Fig. 42 shows the experimental data of the case where the shape of the bottom surface of the opening 1〇5 is a square with the side being the square, and the drawing point of the square indicates that the shape of the bottom surface of the opening 105 is - the side is 20_ Experimental data for the case of the square. In the same figure, the financial point of the triangle indicates the experimental data of the case where the bottom surface of the opening is a rectangle whose long side is the short side of the fairy and the heart is (7). As can be seen from Fig. 42, the above growth rate monotonously increases as the size of the covered area = large. In addition, it is understood that the above-mentioned growth rate is substantially linearly increased in the case where the length of the side of the covered area is 400# m or less, and the fluctuation caused by the opening σ 1〇5 # bottom opening is small. It is known that the length of one side of the covered area is 400# m 321546 70 201019376 • In the following case, the growth rate of the side of the covered area is 5〇〇"m, which is a sharp increase, and the opening is increased. The variation caused by the shape of the bottom surface of 1〇5 also becomes large. Therefore, the maximum width of the surface of the barrier layer parallel to the Si crystal layer is preferably 400/zm or less. The 43® shows the compound semiconductor 21〇 The coefficient of variation of the growth rate of 8 and the relationship between the adjacent two covered regions. The coefficient of variation refers to the ratio of the standard deviation to the average value, and the thickness of the above three measurement points can be thick. The standard deviation is calculated by dividing the flat value of the film thickness. In Fig. 43, the vertical axis represents the coefficient of variation of the film thickness [human] of the compound semiconductor 2108 grown during the -time period, and the horizontal axis represents the adjacent The distance Um between the covered areas. Figure 43 shows that the distance between two adjacent covered areas is bm, 2Mm, 5〇#m, 1〇Mm, 2〇〇_, _f', 400# Experimental data for the case of m and 450&quot;m. In the figure, the look of the diamond The dots indicate experimental data in the case where the shape of the bottom surface of the opening 1 () 5 is a square having one side. ❿ In Fig. 43, the distance between the adjacent two covered areas is 〇#ra, 100', 200 //m, heart, shed (four) and the experimental data of the _ corresponding to the figure 42 The data of the covered long brush—·„, 2, and 2... The distance between the two adjacent covered areas is 2〇' and the data of 50_ is the same as other experimental data. The program 'score= is obtained by measuring the film thickness of the compound semiconductor 21〇8 for the length of the side of the covered region (10) and the case of the _. From the 4th figure, it can be seen that compared with the adjacent two 71 321546 201019376 3 between the covered areas is the case of 〇 _ where the above distance is 2 〇 / / m, the growth rate of the compound abundance conductor 2108 is very stable. From the above results, it can be seen that: In the case where the coverage areas are only a little separated, the growth rate of the crystal grown inside the opening 105 is also stabilized. Further, it is understood that the crystal growth region is disposed between the adjacent two covered regions, and the crystal is crystallized. The growth rate will be stabilized. In addition, we can see that even The distance between two adjoining covering the area where Mm, may be

:::等間隔配置複數個開。1〇5’而抑制上述結晶的成 長速度的變動。 (實施例10)::: Configure multiple openings at equal intervals. 1〇5', the variation of the growth rate of the above crystals is suppressed. (Embodiment 10)

將被覆區域的一邊的長度設定為200 _、500 _、7〇〇 P、1〇〇〇_、l500 //m、2〇〇〇_、3〇〇〇心或 425〇_， 再針對各個纽’以與實施例9 -樣的料製作半導體晶 圓’並量測形成於開口 1G5的内部之化合物半導體測的 膜厚。本實_，係以在^晶圓2iq2之上配置複數個相 冋大小的Sl〇2層之方式形成該Si〇4。而且，以上述複數 個Si〇2層相互分開之方式形成該層。與實施例9 一樣， 針對開口 105的底面形狀為一邊為1Mm的正方形、一邊 為2—紅方形、短邊為長邊為心_長方形 之二種情況進行實驗。Ge結晶層2⑽及化合物半導體謂 的成長條件設定為與實施例9相同的條件。 (實施例11) 除了使三甲基鎵（trimethyl galHum)的供給量減 半、使化合物半導體⑽的成長速度減到大約—半以外， 321546 72 201019376 ，和實施例ίο的情況一樣，量測形成於開口 1〇5的内部之化 '合物半導體2108的膜厚。實施例11，係將被覆區域的一 邊的長度设定為 2〇〇//m、500#瓜、1000 /zm、2000/zm、3000 或425〇em，再針對開口 1〇5的底面形狀為一邊為ι〇 //m的正方形之情況進行實驗。 將貫施例10及實施例Π的實驗結果，顯示於第44 圖、第45至49圖 '第50至54圖、及表1。第44圖中顯 :實施例ίο的各種情況中之化合物半導體21〇8的膜厚的 ❻平句值弟45至49圖中顯示實施例1 〇的各種情況中之化 口物半V體2108的電子顯微鏡影像。第5〇至54圖中顯示 只施例11的各種情況中之化合物半導體2108的電子顯微 鏡影像。表1中顯示實施例1〇及實施例n的各種情況中 之化合物半導體21〇8的成長速度、及Ra•值。 第44圖顯示化合物半導體2108的成長速度、與被覆 區域的^小及開口 1()5的大小之關係。第44圖中，縱轴表 ❿不在疋時間的期間成長出的化合物半導體21〇8的膜 厚’橫軸表示被覆區域的一邊的長度[_]。本實施例中: 因為化合物半導體21〇8的膜厚係在一定時間的期間成長 出的膜#所以將該膜厚除以該時間，就得到化合物半 體2108的成長速度的近似值。 第44圖中，菱形的描繪點表示開口 的底面形狀為 邊為的正方形之情況的實驗數據，四肖形的插緣 點表示開口 105的底面形狀為一邊為20_的正方形之情 況的實驗數據。同圓中，三角形的描緣點表示開口 1〇5的 321546 73 201019376 為長邊為4〇#m短邊為3{)/zm的長方形之倩況的 貫驗數據。 /第4圖可知.一直到被覆區域的一邊的長度為4250 //m’上述成長速度都隨著被覆區域的大小變大而穩定地增 加因此，阻礙層之與Si結晶層平行的面上之最大寬度， 以在4250 以下為佳。從第42圖所示的結果及第44圖 厂、、°果了知.在相鄰接的兩個被覆區域只是分開一點 點=情況，在開口 1〇5的内部成長之結晶的成長速度也會 穩疋化此外，可知：在相鄰接的兩個被覆區域之間配置 讓結晶成長的區域’上述結晶的成長速度就會穩定化。 第45至49圖顯示針對實施例1〇的各種情況以電子顯 微鏡觀察化合物半導體21〇8的表面所見之結果。第沾圖、 第46圖、第47圖、第48圖、第49圖，分別顯示.被覆區 域的一邊的長度為 4250 /zin、2000/(/in、i〇〇〇#m、5〇Mra' 200/zm之情況的結果。從第45至49圖可知：隨著被覆區 域的大小變大，化合物半導體21〇8的表面狀態會惡化。 第50至54圖顯示針對實施例u的各種情況以電子顯 微鏡觀察化合物半導體21〇8的表面所見之結果。第5〇圖、 第51圖、第52圖、第53圖、第54圖，分別顯示被覆區 域的一邊的長度為 4250# m、2000 //m、l〇〇0/z m、5〇〇#m、 200 /zm之情況的結果。從第5〇至54圖可知：隨著被覆區 域的大小變大，化合物半導體2108的表面狀態會惡化。此 外，可知：與實施例10的結果相比較，化合物半導體21〇8 的表面狀態有改善。 321546 74 201019376 ' 表1顯示實施例10及實施例11的各種情況中之化合 物半導體2108的成長速度[A/min]、及Ra值[//in]。其中， 化合物半導體210 8的膜厚，係以針式段差計加以量測，Ra 值係根據雷射顯微鏡裝置的觀察結果而算出。從表1可 知：化合物半導體2108的成長速度越小，表面粗度越有改 善。此外，可知：化合物半導體2108的成長速度在30Onm/ min以下之情況，Ra值在0. 02//m以下。 [表1 ] 被覆區域的 一邊的長度 [β m] 實施例10 實施例11 成長速度 [A/min] Ra值 [/zm] 成長速度 [A/min] Ra值 [/zm] 200 526 0. 006 286 0. 003 500 789 0. 008 442 0. 003 1000 1216 0. 012 692 0. 005 2000 2147 0. 017 1264 0. 007 3000 3002 0. 020 1831 0. 008 4250 3477 0. 044 2190 0. 015 ❿ (實施例12) 與實施例9 一樣，製作具備有Si晶圓2102、阻礙層 2104、Ge結晶層2106、及作為化合物半導體2108的一個 例子之GaAs結晶之半導體晶圓。本實施例，係在Si晶圓 2102的表面之（100)面形成阻礙層2104。第55至57圖中 顯示形成於上述半導體晶圓之GaAs結晶的表面的電子顯 75 321546 201019376 微鏡影像。 私虎第55圖顯不使GaAS結晶在開口 105(配置成開口 105 2面形狀的一邊的方向、與&amp;晶圓2102的侧&gt; 方向實 二Γ丁者)的内部成長之情況的結果。本實施例中，被覆 的千面形狀為—邊的長度為3QMm的正方形。開口 服的底面形狀為一邊為1Mm的正方形。第Η圖中 頭表=&lt;010&gt;方向。如第55圖所示，得到形狀整齊的結晶月'。 处第55圖可知：在GaAs結晶的四個侧面分別出現 (1W)面、（1-10)面、⑽）面及⑴〇)面。此外，可知·· 在圖_ GaAs結晶的左上角出現⑴面，在圖中 晶的右下角出現U-U)面。（1Η)面及（卜⑴面皆為= (-1-1-1)面等效的面，皆為安定的面。 力另外，可知：在圖中GaAs結晶的左下角及右上角，並 沒有出現這樣的面。例如，雖然⑴n面可出現在圖中的左 下角’但（111)面並未出現。關於此點，可想成是因為圖中 的左下角夾在比（111)面安定的（11〇)面及（1〇1)面之間的 第56圖顯不使GaAs結晶在開口 105(配置成開口 1〇5 的底面形狀的-邊的方向、與Si晶圓2m的侧〉方向實 質地平行者）的内部成長之情況的結果。第56圖顯示從上 方傾斜45°觀察所見的結果。本實施例中，被覆區域的平 面形狀為—邊的長度為5Mm的正方形。開口挪的底面 形狀為一邊長度為10 Am的正方形。第56圖中，箭頭表 不&lt;010〉方向。如第56圖所示’得到形狀整齊的結 321546 76 201019376 — 第57圖顯示使GaAs結晶在開口 105(配置成開口 105 ' 的底面形狀的一邊的方向、與Si晶圓2102的&lt;011〉方向實 質地平行者）的内部成長之情況的結果。本實施例中，被覆 區域的平面形狀為一邊的長度為400 // m的正方形。開口 105的底面形狀為一邊長度為10//Π1的正方形。第57圖中， 箭頭表示&lt;011〉方向。如第57圖所示，得到與第55及56 圖相較，形狀紊亂的結晶。關於此點，可想成是GaAs結晶 的側面出現比較不安定的（111)面，結果導致結晶的形狀產 ❹生紊亂的緣故。 (實施例13) 與實施例9 一樣，製作具備有Si晶圓2102、阻礙層 2104、Ge結晶層2106、及作為化合物半導體2108的一個 例子之GaAs層之半導體晶圓。本實施例中，係在Ge結晶 層2106與化合物半導體2108之間形成中間層。本實施例 中，被覆區域的平面形狀為一邊的長度為200 //m的正方 ^ 形。開口 105的底面形狀為一邊為10/zm的正方形。藉由 CVD法，在開口 105的内部形成膜厚850nm的Ge結晶層2106 後，以800°C實施退火處理。 使Ge結晶層2106退火之後，將形成有Ge結晶層2106 之Si晶圓2102的溫度設定為550°C，藉由MOCVD法而形 成中間層。以三曱基鎵（trimethyl gallium)及珅化氳 (arsine)作為原料氣體而使中間層成長。中間層的膜厚係 為30nm。然後，使已形成了中間層之Si晶圓21股·的溫度 升高到640°C後，藉由MOCVD法而形成作為化合物半導體 77 321546 201019376 2108的一個例子之GaAs層。GaAs層的膜厚係為500nm。 ’ 除此以外的條件，都採用與實施例9 一樣的條件而製作出 - 半導體晶圓。 第58圖中顯示以穿透式電子顯微鏡觀察製造出的半 導體晶圓的斷面所見的結果。如第58圖所示，在Ge結晶 層2106及GaAs層都沒有觀察到差排。由此可知：採用上 述的構成，就可在Si晶圓上形成良質的Ge層、以及與該 Ge層晶格匹配或準晶格匹配之化合物半導體層。 (實施例14) ❹ 與實施例13 —樣，製作出具備有Si晶圓2102、阻礙 層2104、Ge結晶層2106、中間層、及作為化合物半導體 2108的一個例子之GaAs層之半導體晶圓後，利用得到的 半導體晶圓而製作出HBT元件構造。HBT元件構造係以以 下的程序製作。首先，與實施例13的情況一樣，製作出半 導體晶圓。本實施例中，被覆區域的平面形狀為一邊的長 度為50/zm的正方形。開口 105的底面形狀為一邊為20/zmSet the length of one side of the covered area to 200 _, 500 _, 7 〇〇 P, 1 〇〇〇 _, l 500 //m, 2 〇〇〇 _, 3 〇〇〇 或 or 425 〇 _, and then A semiconductor wafer was fabricated in the same manner as in Example 9 and the film thickness of the compound semiconductor formed inside the opening 1G5 was measured. In the present invention, the Si〇4 is formed by arranging a plurality of S1〇2 layers of the same size on the wafer 2iq2. Further, the layer is formed in such a manner that the plurality of Si 2 layers are separated from each other. In the same manner as in the ninth embodiment, the bottom surface of the opening 105 was tested in the case of a square having 1 Mm on one side, a 2-red square on one side, and a long side as a heart- rectangle on the short side. The growth conditions of the Ge crystal layer 2 (10) and the compound semiconductor were set to the same conditions as in Example 9. (Example 11) In addition to halving the supply amount of trimethylgal galHum and reducing the growth rate of the compound semiconductor (10) to about -half, 321546 72 201019376, as in the case of the example ί, measurement formation The film thickness of the composite semiconductor 2108 is formed inside the opening 1〇5. In the eleventh embodiment, the length of one side of the covered region is set to 2 〇〇//m, 500# melon, 1000/zm, 2000/zm, 3000 or 425 〇em, and the shape of the bottom surface of the opening 1〇5 is Experiment on the case of a square of ι〇//m. The experimental results of Example 10 and Example 显示 are shown in Fig. 44, Fig. 45 to Fig. 49, Fig. 50 to Fig. 54, and Table 1. 44 shows the film thickness of the compound semiconductor 21〇8 in the various cases of the embodiment ίο. The values of the film of the compound semiconductors 〇8 are shown in Figs. 45 to 49, and the sulphate half V body 2108 in each case of the embodiment 1 〇 is shown. Electron microscope image. Electron microscopy images of the compound semiconductor 2108 in each of the cases of Example 11 are shown in Figures 5 to 54. Table 1 shows the growth rates and Ra• values of the compound semiconductors 21〇8 in the respective cases of Example 1 and Example n. Fig. 44 shows the relationship between the growth rate of the compound semiconductor 2108, the size of the coated region, and the size of the opening 1 () 5. In Fig. 44, the vertical axis represents the film thickness of the compound semiconductor 21〇8 which is not grown during the 疋 time period. The horizontal axis indicates the length [_] of one side of the covered region. In the present embodiment, the film thickness of the compound semiconductor 21〇8 is a film grown during a certain period of time. Therefore, by dividing the film thickness by the time, an approximate value of the growth rate of the compound half 2108 is obtained. In Fig. 44, the rhombic drawing point indicates experimental data in the case where the bottom surface shape of the opening is a square having a side, and the four-corner cutting edge point indicates experimental data in the case where the bottom surface shape of the opening 105 is a square having one side of 20_. . In the same circle, the triangle's stroke point indicates the opening 1〇5 of 321546 73 201019376 is the continuous data of the rectangle with the long side being 4〇#m and the short side being 3{)/zm. / Fig. 4 shows that the length of one side of the covered area is 4250 //m', and the growth rate is steadily increased as the size of the covered area becomes larger. Therefore, the surface of the barrier layer parallel to the Si crystal layer is The maximum width is preferably below 4250. From the results shown in Fig. 42 and Fig. 44, it is known that the two covered areas in the adjacent area are only slightly separated = the growth rate of the crystal grown inside the opening 1〇5 is also Further, it is understood that the growth rate of the crystal is stabilized in a region where crystal growth is arranged between two adjacent coating regions. Figures 45 to 49 show the results of observing the surface of the compound semiconductor 21A8 by an electron microscope for each case of Example 1. The first staining map, the 46th image, the 47th image, the 48th image, and the 49th image respectively show that the length of one side of the covered region is 4250 /zin, 2000/(/in, i〇〇〇#m, 5〇Mra The result of the case of '200/zm. As can be seen from the 45th to 49th graphs, as the size of the covered region becomes larger, the surface state of the compound semiconductor 21〇8 deteriorates. FIGS. 50 to 54 show various cases for the example u. The results of observing the surface of the compound semiconductor 21〇8 by an electron microscope are shown in Fig. 5, Fig. 51, Fig. 52, Fig. 53, and Fig. 54, respectively, showing the length of one side of the coated region being 4250 #m, 2000. The result of the case of //m, l〇〇0/zm, 5〇〇#m, 200 /zm. From the fifth to the 54th figure, as the size of the covered area becomes larger, the surface state of the compound semiconductor 2108 will Further, it was found that the surface state of the compound semiconductor 21〇8 was improved as compared with the result of Example 10. 321546 74 201019376 ' Table 1 shows the growth of the compound semiconductor 2108 in each case of Example 10 and Example 11. Speed [A/min], and Ra value [//in]. Among them, compound semiconductor 210 8 The film thickness was measured by a needle type step meter, and the Ra value was calculated based on the observation result of the laser microscope apparatus. As is clear from Table 1, the smaller the growth rate of the compound semiconductor 2108, the more the surface roughness is improved. When the growth rate of the compound semiconductor 2108 is 30 or less/min or less, the Ra value is 0.02/m or less. [Table 1] The length of one side of the covered region [β m] Example 10 Example 11 Growth rate [ A/min] Ra value [/zm] Growth rate [A/min] Ra value [/zm] 200 526 0. 006 286 0. 003 500 789 0. 008 442 0. 003 1000 1216 0. 012 692 0. 005 2000 2147 0. 017 1264 0. 007 3000 3002 0. 020 1831 0. 008 4250 3477 0. 044 2190 0. 015 ❿ (Embodiment 12) As in the ninth embodiment, the Si wafer 2102 and the barrier layer 2104 are formed. The Ge crystal layer 2106 and the GaAs crystal semiconductor wafer as an example of the compound semiconductor 2108. In this embodiment, the barrier layer 2104 is formed on the (100) plane of the surface of the Si wafer 2102. Figs. 55 to 57 Displaying an electron display formed on the surface of the GaAs crystal of the above semiconductor wafer 75 321546 201019376 Images. The 55th picture of the private tiger shows the result of the growth of GaAS crystallized inside the opening 105 (the direction in which the opening 105 2 surface is arranged, and the side of the &amp; wafer 2102 side) . In the present embodiment, the shape of the thousand surface to be covered is a square having a length of 3QMm. The shape of the bottom surface of the opening suit is a square having a side of 1 Mm. In the figure, the header table = &lt;010&gt; direction. As shown in Fig. 55, a neat crystal crystallization month is obtained. As can be seen from Fig. 55, the (1W) plane, the (1-10) plane, the (10) plane, and the (1) 〇 plane appear on the four sides of the GaAs crystal. Further, it can be seen that the (1) plane appears in the upper left corner of the graph GaAs crystal, and the U-U) plane appears in the lower right corner of the crystal in the figure. (1Η) face and (b) (1) face are all equivalent faces of = (-1-1-1) face, all of which are stable faces. Forces, it is known that: in the figure, the lower left and upper right corners of GaAs crystal, and Such a face does not appear. For example, although the (1) n-plane can appear in the lower left corner of the figure, the (111) face does not appear. In this regard, it can be thought of because the lower left corner of the figure is sandwiched by the (111) plane. The 56th diagram between the stable (11 〇) plane and the (1 〇 1) plane does not cause the GaAs crystal to be crystallized in the opening 105 (the direction of the bottom side of the bottom surface of the opening 1〇5, and the 2m of the Si wafer) The result of the internal growth of the side > the direction substantially parallel. Fig. 56 shows the result seen by tilting 45 degrees from above. In this embodiment, the planar shape of the covered area is a square having a side length of 5 Mm. The shape of the bottom surface of the opening is a square with a length of 10 Am. In Fig. 56, the arrow indicates the direction of &lt;010>. As shown in Fig. 56, 'the shape is neatly knotted 321546 76 201019376 - Fig. 57 shows the GaAs Crystallization in the direction of the opening 105 (the one side of the bottom surface shape of the opening 105 ′, and the Si wafer 2102 The result of the internal growth of the &lt;011> direction substantially parallel. In the present embodiment, the planar shape of the covered region is a square having a length of one side of 400 // m. The shape of the bottom surface of the opening 105 is one side having a length of 10 // Square of Π 1. In Fig. 57, the arrow indicates the direction of &lt;011>. As shown in Fig. 57, a crystal having a disordered shape as compared with Figs. 55 and 56 is obtained. A relatively unstable (111) plane appeared on the side of the crystal, and as a result, the shape of the crystal was disturbed. (Example 13) As in Example 9, a Si wafer 2102, a barrier layer 2104, and Ge crystal were prepared. The layer 2106 and the semiconductor wafer of the GaAs layer as an example of the compound semiconductor 2108. In this embodiment, an intermediate layer is formed between the Ge crystal layer 2106 and the compound semiconductor 2108. In this embodiment, the planar shape of the covered region The length of one side is a square shape of 200 //m. The shape of the bottom surface of the opening 105 is a square having a side of 10/zm. After the Ge crystal layer 2106 having a film thickness of 850 nm is formed inside the opening 105 by the CVD method, 800 ° C After annealing the Ge crystal layer 2106, the temperature of the Si wafer 2102 on which the Ge crystal layer 2106 is formed is set to 550 ° C, and an intermediate layer is formed by MOCVD. Trimethyl gallium is used. And an arsine as a material gas to grow the intermediate layer. The thickness of the intermediate layer is 30 nm. Then, the temperature of the Si wafer 21 having the intermediate layer formed is raised to 640 ° C. A GaAs layer as an example of the compound semiconductor 77 321546 201019376 2108 is formed by the MOCVD method. The film thickness of the GaAs layer was 500 nm. For the other conditions, a semiconductor wafer was fabricated under the same conditions as in Example 9. Fig. 58 shows the results seen by observing the cross section of the fabricated semiconductor wafer by a transmission electron microscope. As shown in Fig. 58, no difference was observed in both the Ge crystal layer 2106 and the GaAs layer. From this, it is understood that a favorable Ge layer and a compound semiconductor layer which is lattice-matched or quasi-lattice-matched to the Ge layer can be formed on the Si wafer by the above configuration. (Example 14) ❹ In the same manner as in Example 13, a semiconductor wafer including a Si wafer 2102, a barrier layer 2104, a Ge crystal layer 2106, an intermediate layer, and a GaAs layer as an example of the compound semiconductor 2108 was produced. The HBT element structure was fabricated using the obtained semiconductor wafer. The HBT element structure is produced by the following procedure. First, as in the case of Example 13, a semiconductor wafer was fabricated. In the present embodiment, the planar shape of the covered region is a square having a length of one side of 50/zm. The shape of the bottom surface of the opening 105 is 20/zm on one side.

Q 的正方形。除此以外的條件，都採用與實施例13 —樣的條 件而製作出半導體晶圓。 其次，藉由MOCVD法，在上述半導體晶圓的GaAs層的 表面，層積形成半導體層。藉此，得到：具有Si晶圓2102、 膜厚850nm的Ge結晶層2106、膜厚30nm的中間層、膜厚 500nm的未摻雜GaAs層、膜厚300nm的η型GaAs層、膜 厚20nm的η型InGaP層、膜厚3nm的η型GaAs層、膜厚 300nm的GaAs層、膜厚50 nm的p型GaAs層、膜厚20nm 78 321546 201019376 的η型InGaP層、膜厚120nm的η型GaAs層、及膜厚60nm 的η型InGaAs層，依所列順序配置而成之HBT元件構造。 然後，在得到的HBT元件構造上配設電極，而作成作為電 子元件或電子裝置的一個例子之HBT元件。在上述半導體 層中，使用Si來作為η型雜質。在上述半導體層中，使用 C(碳）來作為ρ型雜質。 第59圖顯示得到的ΗΒΤ元件的雷射顯微鏡像。圖中， 淺灰色部份表示電極。從第59圖可知：在配置於正方形的 〇 被覆區域的中央附近之開口 105的區域，有三個電極並 排。上述三個電極，在圖中由左至右，分別表示ΗΒΤ元件 的基極電極、射極電極及集極電極。對上述ΗΒΤ 7〇件的電 氣特性進行量測，可確認得到電晶體動作。此外，針對上 述ΗΒΤ元件，以穿透式電子顯微鏡觀察其斷面，觀察不到 差排的情形。 (實施例15) ^ 與實施例14 一樣，製作出三個具有與實施例14 一樣 的構造之ΗΒΤ元件。將製作出的三個ΗΒΤ元件並聯連接。 本實施例中，被覆區域的平面形狀為長邊為100/zm短邊為 50/zm的長方形。另外，在上述被覆區域的内部，設置三 個開口 105。開口 105的底面形狀皆為一邊為15/zm的正 方形。除此以外的條件，都採用與實施例14 一樣的條件而 製作出HBT元件。 第60圖顯示得到的HBT元件的雷射顯微鏡像。圖中， 淺灰色部份表示電極。從第60圖可知：三個HBT元件為並 79 321546 201019376 聯連接對上述電子元件的電氣特性進行量測，可確認得 到電晶體動作。 (實施例16) 改變開口 105的底面積而製作HBT元件，調查開口 1〇5 的底面積與得到的腿元件的電氣特性之關係。與實施例 14 一樣’製作出HBT元件。量測祖元件的基極表面咖％ 如⑷電阻值Rb[Q/口]及電流放大❹，以之作為Ηβτ元 件的電氣特性。電纽大率$，係將餘電流的值除以基 極電流的值而求得。本實施例中，係分別針對開口⑽的 底面形狀為-邊為·，的正方形、短邊為心m長邊為 的長方形一邊為3Mm的正方形、短邊為心m ^為·ffl的長方形、或短邊為·m長邊為δ0_的 長方形等情況，而製作出ΗΒΤ元件。 在開口 105的底面形狀為正方形之情況，係使開口⑻ 的底面形狀的正交的兩個邊中的一個邊與Si晶圓21〇2的 11〇&gt;方向平行’另—個邊與Si晶圓2102的_&gt;方向平 二，Ϊ開口 1〇5。在開〇 1〇5的底面形狀為長方形之 〈二二1〇5的底面形狀的長邊與以晶圓2102的 ι〇&gt;方向平行，短邊與Si晶圓21G2的·〉方向平行， ::口广被覆區域的平面形狀，則以一邊為 的正方开&gt; 之情況為主而進行實驗。 圖顯示上述贿元件之電流放大❹ 表面電阻值Rb之比、與聞 土® 第61圖令，縱軸表5的底面積[Μ之關係。 圖中，縱轴表不電流放大率石除以基極表面電阻值 321546 80 201019376 ' Rb所得到之值，橫轴表示開口 105的底面積。第61圖中雖 ' 未顯示電流放大率/3之值，但所得到的電流放大率係為70 至100左右之高值。另一方面，在Si晶圓2102的全面形 成同樣的HBT元件構造，而形成HBT元件之情況的電流放 大率/3，則在10以下。 由此可知：在Si晶圓2102的表面局部地形成上述HBT 元件構造，可製作出電氣特性優良的裝置。而且可知：尤 其是在開口 105的底面形狀的一邊的長度在80 // m以下、 ❹ 或者開口 105的底面積在1600 /zm2以下之情況，可製作出 電氣特性優良的裝置。此情況，設於開口 105的内部之種 子結晶的底面，其最大寬度也會在80/zm以下，或者就該 底面的面積而言，也會在16 0 0 // m2以下。此處，種子結晶 的底面的最大寬度，係指將種子結晶的底面的任意兩點連 成的各直線的長度之中最大的長度。 從第61圖可知：開口 105的底面積在900 # m2以下之 • 情況，相較於開口 105的底面積在1600 # m2之情況，電流 ❿ 放大率相對於基極表面電阻值Rb之比的變動較小。由此 可知：在開口 105的底面形狀的一邊的長度在40/zm以下、 或者開口 105的底面積在900 # m2以下之情況，能以很好的 良率製造上述裝置。此情況，設於開口 105的内部之種子 結晶的底面，其最大寬度也會在40/zm以下，或者就該底 面的面積而言，也會在900/z in2以下。 如上所述，可藉由包含：在Si晶圓的主面形成阻礙結 晶成長之阻礙層的階段、使阻礙層圖案化而在阻礙層形成 81 321546 201019376 在相對於晶圓的主面大致垂直的方向貫通而使晶圓露出之 ’ 開口的階段、使Ge層與開口的内部的晶圓相接而結晶成長 · 的階段、以及使功能層在Ge層上結晶成長的階段之半導體 晶圓之製造方法來製作半導體晶圓。可藉由包含：在Si晶 圓之上形成具有開口且阻礙結晶成長的阻礙層的階段、在 開口内形成Ge層的階段、·以及在形成Ge層之後形成功能 層的階段之半導體晶圓之製造方法來製作半導體晶圓。 如上所述，可製作：在S i晶圓的主面形成阻礙結晶成 長之阻礙層，在阻礙層形成在相對於晶圓的主面大致垂直 © 的方向貫通而使晶圓露出之開口，使Ge層與開口的内部的 晶圓相接而結晶成長，再使功能層在Ge層上結晶成長而得 到之半導體晶圓。可製作：包含Si晶圓、設在晶圓之上且 具有開口且阻礙結晶成長之阻礙層、形成於開口内之Ge . 層、以及在形成Ge層之後形成之功能層之半導體晶圓。 如上所述，可製造：在Si晶圓的主面形成阻礙結晶成 長之阻礙層，在阻礙層形成在相對於晶圓的主面大致垂直 〇 的方向貫通而使晶圓露出之開口，使Ge層與開口的内部的 晶圓相接而結晶成長，使功能層在Ge層上結晶成長，再在 功能層形成電子元件而得到之電子裝置。可製作：包含Si 晶圓、設在晶圓之上且具有開口且阻礙結晶成長的阻礙 層、形成於開口内的Ge層、在形成Ge層之後形成的功能 層、以及形成於功能層的電子元件之電子裝置。 (實施例17) 第62圖顯示製作出的半導體晶圓中的結晶的斷面之 82 321546 201019376 掃描式電子顯微鏡影像。第63圖顯示基於使第62圖的影 ' 像更容易看之目的而顯示的摹寫圖。該半導體晶圓，係^ 以下的方法製作。準備以（100)面作為主面之Si晶圓 2202，並在Si晶圓2202之上，形成作為絕緣膜之以〇2膜 2204。在Si〇2膜2204形成到達Si晶圓2202的主面之開口 105，然後藉由將單結晶鍺（mon〇germanium)用作為原料之 CVD法，在露出於該開口 1〇5的内部之Si晶圓22〇2的主 面形成Ge結晶2206。Si晶圓2202、Si〇2膜2204、及Ge ® 結晶2206係分別等同於s丨結晶層166、阻礙層1 、Ge 結晶106。 再來，藉由將三曱基鎵（1：1^11^1±71运311111111)及件化氯 (arsine)用作為原料之M0CVD法，使作為種子化合物半導 體之GaAs結晶2208在Ge結晶2206之上成長。GaA.s結晶 2208係等同於種子化合物半導體結晶1〇8eGaAs結晶22〇8 之成長’係先在550〇C下進行低溫成長，然後在640〇C之溫 ❹度下成長’在640 C之溫度下成長時之珅化氫（arsine)分 壓係為0. 05 kPa。結果，可確認得到GaAs結晶2208在Ge 結晶2206之上成長。而且，可確認得到在GaAs結晶2208 的種子面出現（110)面。 接著’再使作為橫向成長化合物半導體層之GaAs結晶 2208成長。橫向成長時的成長溫度為“(re，砷化氫 (arsine)分壓為 0.43 kPa。 第64圖顯示得到的結晶的斷面之掃描式電子顯微鏡 影像。第65圖顯示基於使第64圖的影像更容易看之目的 83 321546 201019376 而顯示的摹寫圖。從圖可確認：GaAs結晶22〇8在si〇2膜 2204之上具有橫向成長面，且可確認GaAs結晶&amp;⑽也在 SiCh膜2204上橫向成長。因為橫向成長出的部份為 為無缺陷區域’所以在該橫向成長出的部份形成好裝 置，就可形成性能優良的電子裝置。 、 (實施例18) 與貫施例17 —樣，使Ge結晶2206選擇性地在Si晶 圓2202之上成長，來形成半導體晶圓。對該半導體晶圓實 施重複十次800t及680t的溫度之循環退火處理。以能量 分散式X射線分析裝置（以下有時稱之為EDX)，對得^的 半導體晶圓（以下稱為試料幼之以結晶22〇6與si晶圓 2202的界面處的Si及Ge的元素濃度進行評價。另外，同 樣地使Ge結晶選擇性地在^晶圓22〇2上成長而形成半導 體晶圓，但並未對此半導體晶圓實施循環退火處理（以下將 此半導體晶圓稱為試料B)，並同樣以EDX對之進行評價。 第66圖顯示關於試料八之^元素的側面輪廓貝 (profile)。第67圖顯示關於試料A之以元素的側面輪 廓。第68圖顯示關於試料b之&amp;元素的侧面輪靡。第69 圖顯不關於試料B之Ge元素的侧面輪廓。第7〇圖顯示基 於使第66至69圖更容易看之目的而顯示的示意圖。從圖 中可確認：試料B中，Si晶圓22〇2與^結晶之間的界面 陡峻，相對的，試料A中’界面則為模糊不清的狀離，呈 現Ge擴散到Si晶圓22〇2中之模樣。Si晶圓22〇2、以〇2 膜2204 '及Ge結晶22〇6係分別等同於&amp;晶圓㈣、阻 321546 84 201019376 礙層2104、Ge結晶2106。 針對試料A及試料B，限定Si晶圓2202與Ge結晶2206 的界面中之量測區域，而量測Si及Ge的元素強度積分值。 第71圖係顯示關於試料A的量測區域之SEM影像。前述元 素強度積分值的量測區域，係在第71圖（SEM影像）中，Si 晶圓2202上有Ge結晶2206存在的位置，從該Si晶圓2202 與Ge結晶2206的界面（在前述SEM影像中觀察到的界面） 往Si晶圓2202侧深入1〇至I5nm的位置。 第72圖顯示關於第？！圖中所示的量測區域之y及 Ge的元素強度積分值。第73圖係顯示關於試料β的量測 區域之SEM影像。第74圖顯示關於第73圖中所示的量測 區域之Si及Ge的元素強度積分值。從圖可知：在試料Β 方面，幾乎檢.測不到Ge的訊號，有的只是Si的訊號，相 對的’在試料A方面，則檢測到較大的Ge的訊號。由此可 知：在試料A方面，Ge擴散到了 Si晶圓2202中。 ❿ 找出在Si晶圓2202與SiCh膜2204相接的區域將 元素之’朱度方向強度輪靡（profile)描緣出來時，以晶 2202中的Si強度與抓膜2204中的Si強度之總和為5 之，置，將此位置定為Si晶圓2202與Ge結晶的界面， 後量測從該界面往Si晶圓22G2側深入5至1〇 nm範圍 Ge及Si之各元素的元素強度比。從各元素強度比算出 於各το素之深度方向的積分值，再算出兩者的積 (Ge/Si)。 結果，在試料A方面比值為3 33 ,在試料B方面則為 321546 85 201019376 1. 10。由此，算出從Si晶圓2202與Ge結晶2206的界面 ’ 往Si晶圓2202側深入5至10 nm的範圍内之Ge的平均濃 · 度，在試料A方面為77%，在試料B方面則為52%。針對試 料A及試料B，進行利用穿透式電子顯微鏡而進行之差排 的觀察，發現試料A並不存在到達Ge結晶2206表面之差 棑。另一方面，在試料B則發現有以lxl09cnf2程度之密度 到達結晶表面之差排存在。從以上的結果可知：循環退火 處理之實施，具有使Ge結晶2206之差排減低之效果。 (實施例19) ❿ 在與實施例18的試料A —樣實施過循環退火處理之 Ge結晶2206上，藉由MOCVD法使GaAs結晶2208成長， 再在該GaAs結晶2208上層積形成由GaAs層及InGaP層所 構成之多層構造膜而作成試料C。另外，除了並未對Ge結 晶2206實施後退火處理（post anneal)之外，與上述一樣 形成GaAs結晶2208及多層構造膜而作成試料D。 針對試料C及試料D，實施與實施例18 —樣之EDX測 ❹ 定，量測從Si晶圓2202與Ge結晶的界面往Si晶圓2202 側深入5至1 Onm的範圍内之Ge及Si之各元素的元素強度 比。再算出深度方向的積分值，然後算出Ge及S i兩者的 積分值之比（Ge/Si)。此比值在試料C為2. 28，在試料D 為0.60。由此，算出從Si晶圓2202與Ge結晶的界面往 Si晶圓2202側深入5至10nm的範圍内之Ge的平均濃度， 在試料C為70%，在試料D為38%。 針對試料C及試料D，進行利用穿透式電子顯微鏡而 86 321546 201019376 ' 進行之差排的觀察，發現試料C並不存在到達由GaAs層及 • InGaP層所構成的多層構造膜之差排，相對的，在試料D 則觀測到有到達由GaAs層及InGaP層所構成的多層構造膜 之差排。從以上的結果可知：在從Si晶圓2202與Ge結晶 的界面往Si晶圓2202側深入5至1 Onm的範圍内之Ge的 平均濃度在60%以上之情況，可在Ge結晶上形成更高品質 的化合物半導體層。更佳之Ge的平均濃度為70%以上。 (實施例20) ❹ 實施例20中，將根據本發明的發明人的實驗數據來說 明改變阻礙層的寬度所造成之裝置用薄膜的成長速度的變 化。此處，所謂的裝置用薄膜，係指裝置用薄膜接受加工 後會成為半導體裝置的一部份之薄膜。在例如矽結晶上依 序層積形成複數層化合物半導體薄膜，再對層積形成的化 合物半導體薄膜進行加工而形成半導體裝置之情況，層積 形成的化合物半導體薄膜就屬於裝置用薄膜。此外，在層 Λ 積形成的化合物半導體薄膜與矽結晶之間形成的緩衝層也 屬於裝置用薄膜，作為缓衝層或化合物半導體薄膜的結晶-成長的核之種子層也屬於裝置用薄膜。 裝置用薄膜的成長速度，會影響平坦性、結晶性等裝 置用薄膜的特性。裝置用薄膜的特性，則對於形成於該裝 置用薄膜之半導體裝置的特性有很大的影響。因此，有必 要適切地控制裝置用薄膜的成長速度，來滿足從半導體裝 置的要求規格推導出來之裝置用薄膜的要求特性。以下說 明之實驗數據，顯示出裝置用薄膜的成長速度會依阻礙層 87 321546 201019376 的寬度等之不同而變化。使用該實驗數據，就可設計阻礙 層的形狀，使裝置用薄膜的成長速度成為從裝置用薄膜的 要求規格推導出來之適切的成長速度。 第75圖顯示在實施例20中作成之半導體裝置用晶圓 3000的平面圖案。半導體裝置用晶圓3〇〇〇係在基底晶圓 上具有阻礙層3002、裝置用薄膜3004及犧牲成長部3〇〇6。 阻礙層3002、裝置用薄膜3004及犧牲成長部3〇〇6係形成 為阻礙層3002包圍裝置用薄膜30〇4，犧牲成長部3〇〇6包 圍阻礙層3002之形態。 阻礙層3002係形成為具有大致為正方形之外形，且在 正方形的中心部份形成有大致為正方形之開口部。使開口 部的一邊a為30/zm或50/zm。使阻礙層3〇〇2之從外周邊 到内周邊的距離’亦即阻礙層3〇〇2的寬度b在5#瓜至 私m的範圍内變化。使用二氧化矽（Si〇〇來作為阻礙層 3002。二氧化矽在選擇M〇CVD之磊晶成長條件下，結晶^ 不會在其表面磊晶成長。阻礙層3002係藉由使用乾式熱氧 化法在基底晶圓上形成二氧化矽膜，再以光刻法使該二氧 化矽膜圖案化而形成。 在阻礙層3002以外的基底晶圓上，藉由M〇CVD法使化 &amp;物半導體結晶選擇性地磊晶成長。在阻礙層3002包圍的 開口部磊晶成長成的化合物半導體結晶即為裝置用薄膜 3004，在阻礙層3002的外侧包圍阻礙層3〇〇2之化合物半 體結晶則為犧牲成長部3006。使QaAs結晶、inQap結晶 或P型摻雜的GaAs結晶（p-GaAs結晶）成長來作為化合物 321546 88 201019376 •半導體結晶。使用三甲基鎵（Ga(CH3)3)來作為Ga原料，使 用砷化氫（AsH3)來作為As原料。使用三甲基銦（In(CH3)3) 來作為In原料，使用磷化氫（PH3)來作為P原料。作為p 型雜貝之碳（c)的摻雜’係藉由調整作為摻雜劑（d〇pant) 之&gt;臭化二氯炫（CBrCls)的添加量來加以控制。使磊晶成長 時的反應溫度為61〇°C。 第76圖係顯示使作為裝置用薄膜3004及犧牲成長部 3006之GaAs蟲晶成長時之裝置用薄膜3〇〇4的成長速度與 ®阻礙層3002的寬度的關係之曲線圖（graph)。第77圖係顯 示使作為裝置用薄膜3004及犧牲成長部3006之GaAs磊晶 成長時之裝置用薄膜3004的成長速度與面積比的關係之 曲線圖。第78圖係顯示使作為裝置用薄膜3004及犧牲成 長部3006之InGaP磊晶成長時之裝置用薄膜3〇〇4的成長 速度與阻礙層3002的寬度的關係之曲線圖。 第79圖係顯示使作為裝置用薄膜3004及犧牲成長部 ⑩3006之InGaP磊晶成長時之裝置用薄膜3004的成長速度 與面積比的關係之曲線圖。第80圖係顯示使作為裝置用薄 膜3004及犧牲成長部3006之p-GaAs蠢晶成長時之裝置用 薄膜3004的成長速度與阻礙層3002的寬度的關係之曲線 圖。第81圖係顯示使作為裝置用薄膜3004及犧牲成長部 3006之p-GaAs遙晶成長時之裝置用薄膜3004的成長速度 與面積比的關係之曲線圖。 第76至81圖之各圖中，縱轴表示化合物半導體結晶 的成長速度比。成長速度比，係假設在沒有阻礙層3002之 89 321546 201019376 整個平面上的成長速度為1時之與該整個平面上的成長速 度相比較之成長速度的比。面積比，係形成裝置用薄膜3004 · 之區域的面積相對於將形成裝置用薄膜3004之區域的面 積與形成阻礙層3 0 0 2之區域的面積相加而得的總面積之 比。 各圖中，以黑色四角形或黑色菱形標示之描繪點表示 實際的量測點。實線表示實驗線。實驗線係一變數之二次 函數，係以最小平方法求各多項式的係數而求出。為了比 較，以虛線表示沒有犧牲成長部3006的情況之裝置用薄膜 ❹ 3004的成長速度比。L1為阻礙層3002的開口部面積為50 // m□之情況，L2為阻礙層3002的開口部面積為30 /z m[ 之情況。所謂沒有犧牲成長部3006的情況，係指阻礙層 3002也覆蓋住相當於犧牲成長部3006的區域之情況。 如第76至81圖之各圖所示，阻礙層3002的寬度越大 成長速度越大，面積比越小成長速度越大。而且，實驗線 與量測點相當一致。由此可知：可進行阻礙層3002的設計 ◎ 以期能夠使用實驗線的二次函數來實現希望的成長速度。 另外，如此之實驗結果，可將之想成是因為如下所述 之結晶的成長機制來加以說明。亦即將成膜中之結晶原料 (Ga及As原子），想成是由從空間飛來的分子或在表面遷 移之分子所供給。本發明之發明人等認為：在進行選擇性 的蠢晶成長這類的MOCVD的反應琢境中，在表面遷移之分 子所進行之結晶原料的供給為主要的供給來源。在此情 況，飛來到阻礙層3002之原料分子（前驅體），除了從表面 90 321546 201019376 脫離者之外，會在阻礙層3002的表面遷移，而供給至裝置 用薄膜3004或犧牲成長部3006。此處，若阻礙層3002的 寬度大，則以表面遷移方式供給來的原料分子的絕對數就 會變大，使得裝置用薄膜3004的成長速度變大。此外，若 相對於總面積之裝置用薄膜3004的面積比小，則從阻礙層 3002供給至裝置用薄膜3〇〇4的原料分子就會相對地變 多。因此裝置用薄膜3004的成長速度會變大。The square of Q. Other than the above, a semiconductor wafer was produced in the same manner as in Example 13. Next, a semiconductor layer is laminated on the surface of the GaAs layer of the semiconductor wafer by the MOCVD method. Thereby, a Si wafer 2102, a Ge crystal layer 2106 having a film thickness of 850 nm, an intermediate layer having a thickness of 30 nm, an undoped GaAs layer having a thickness of 500 nm, an n-type GaAs layer having a thickness of 300 nm, and a film thickness of 20 nm were obtained. Η-type InGaP layer, n-type GaAs layer with a film thickness of 3 nm, GaAs layer with a film thickness of 300 nm, p-type GaAs layer with a film thickness of 50 nm, n-type InGaP layer with a film thickness of 20 nm, 78 321546, 201019376, and n-type GaAs with a film thickness of 120 nm The layer and the n-type InGaAs layer having a film thickness of 60 nm are arranged in the order of the HBT element. Then, an electrode is disposed on the obtained HBT element structure to form an HBT element as an example of an electronic component or an electronic device. In the above semiconductor layer, Si is used as an n-type impurity. In the above semiconductor layer, C (carbon) is used as the p-type impurity. Fig. 59 shows a laser microscope image of the obtained ruthenium element. In the figure, the light gray portion indicates the electrode. As is apparent from Fig. 59, three electrodes are arranged side by side in the region of the opening 105 disposed near the center of the square 〇-covered region. The above three electrodes, from left to right in the figure, respectively indicate the base electrode, the emitter electrode and the collector electrode of the ΗΒΤ element. The electrical characteristics of the above-mentioned 〇 7 pieces were measured, and it was confirmed that the operation of the transistor was obtained. Further, with respect to the above-described tantalum element, the cross section was observed by a transmission electron microscope, and the difference of the arrangement was not observed. (Example 15) ^ Three elements having the same configuration as that of Example 14 were produced in the same manner as in Example 14. The three ΗΒΤ elements produced are connected in parallel. In the present embodiment, the planar shape of the covered region is a rectangle having a long side of 100/zm and a short side of 50/zm. Further, three openings 105 are provided inside the above-mentioned covered area. The shape of the bottom surface of the opening 105 is a square having a side of 15/zm. Except for the other conditions, the HBT element was produced under the same conditions as in Example 14. Figure 60 shows a laser microscope image of the obtained HBT element. In the figure, the light gray portion indicates the electrode. It can be seen from Fig. 60 that the electrical characteristics of the above electronic components are measured by the connection of three HBT elements and 79 321546 201019376, and it can be confirmed that the operation of the transistor is obtained. (Example 16) An HBT element was produced by changing the bottom area of the opening 105, and the relationship between the bottom area of the opening 1〇5 and the electrical characteristics of the obtained leg element was examined. The HBT device was fabricated as in the case of Example 14. The base surface of the progenitor element is measured as (4) the resistance value Rb [Q/port] and the current amplification ❹ as the electrical characteristics of the Ηβτ element. The electric multiplier rate is obtained by dividing the value of the residual current by the value of the base current. In the present embodiment, the shape of the bottom surface of the opening (10) is a square having a side of the side, a square having a short side, a square having a long side of the heart m, a square having a length of 3 Mm, and a rectangle having a short side of a heart m ^ being · ffl, Or a short side is a rectangle in which the long side of m is δ0_, and a ΗΒΤ element is produced. In the case where the bottom surface of the opening 105 has a square shape, one of the two sides orthogonal to the shape of the bottom surface of the opening (8) is parallel to the 11 〇&gt; direction of the Si wafer 21〇2, and the other side is Si. The _&gt; direction of the wafer 2102 is flat, and the opening is 1〇5. The long side of the bottom surface of the opening 1〇5 has a rectangular shape, and the long side of the bottom surface of the second and second sides is parallel to the direction of the wafer 2102, and the short side is parallel to the direction of the Si wafer 21G2. In the case of the planar shape of the wide-area coating area, the experiment was performed mainly on the one side of the square opening. The graph shows the ratio of the current amplification ❹ surface resistance value Rb of the above-mentioned bribe element to the bottom area of the vertical axis table 5 [与". In the figure, the vertical axis indicates that the current amplification factor is divided by the base surface resistance value 321546 80 201019376 'The value obtained by Rb, and the horizontal axis indicates the bottom area of the opening 105. In Fig. 61, although the value of current amplification factor /3 is not shown, the current amplification factor obtained is a high value of about 70 to 100. On the other hand, the same HBT element structure is formed over the Si wafer 2102, and the current amplification ratio /3 in the case of forming the HBT element is 10 or less. This shows that the HBT element structure is partially formed on the surface of the Si wafer 2102, and an apparatus having excellent electrical characteristics can be produced. Further, it is understood that, in particular, when the length of one side of the shape of the bottom surface of the opening 105 is 80 // m or less, or the bottom area of the opening 105 is 1600 / zm 2 or less, an apparatus having excellent electrical characteristics can be produced. In this case, the bottom surface of the seed crystals provided inside the opening 105 may have a maximum width of 80/zm or less, or may be 1600/m2 or less in terms of the area of the bottom surface. Here, the maximum width of the bottom surface of the seed crystal refers to the length of the length of each straight line connecting any two points of the bottom surface of the seed crystal. It can be seen from Fig. 61 that the bottom area of the opening 105 is less than 900 #m2, and the ratio of the current 放大 amplification ratio to the base surface resistance value Rb is compared with the case where the bottom area of the opening 105 is 1600 # m2. The change is small. From this, it is understood that the above apparatus can be manufactured with good yield when the length of one side of the shape of the bottom surface of the opening 105 is 40/zm or less, or the bottom area of the opening 105 is 900 #m2 or less. In this case, the bottom surface of the seed crystal provided inside the opening 105 has a maximum width of 40/zm or less, or 900/z in2 or less in terms of the area of the bottom surface. As described above, it is possible to form the barrier layer in a step of forming a barrier layer for inhibiting crystal growth on the main surface of the Si wafer, and to form the barrier layer 81 321546 201019376 substantially perpendicular to the main surface of the wafer. Manufacturing of a semiconductor wafer in a stage in which an opening is formed in a direction to expose a wafer, a Ge layer is brought into contact with a wafer inside the opening, and crystal growth is performed, and a functional layer is crystallized on the Ge layer. The method is to fabricate a semiconductor wafer. The semiconductor wafer may be included in a stage of forming a barrier layer having an opening and hindering crystal growth on the Si wafer, a stage of forming a Ge layer in the opening, and a stage of forming a functional layer after forming the Ge layer. Manufacturing methods to fabricate semiconductor wafers. As described above, it is possible to form a barrier layer for preventing crystal growth on the main surface of the Si wafer, and to form an opening in which the barrier layer is formed to penetrate the wafer in a direction substantially perpendicular to the main surface of the wafer, thereby exposing the wafer. The Ge layer is formed by being in contact with the wafer inside the opening to crystallize and grow, and then the functional layer is crystallized and grown on the Ge layer. A semiconductor wafer including a Si wafer, a barrier layer provided on the wafer and having an opening and inhibiting crystal growth, a Ge layer formed in the opening, and a functional layer formed after forming the Ge layer can be fabricated. As described above, it is possible to form a barrier layer that inhibits crystal growth on the main surface of the Si wafer, and to form an opening in which the barrier layer is formed to penetrate the wafer substantially perpendicularly to the main surface of the wafer to expose the wafer. An electronic device in which a layer is in contact with a wafer inside the opening to crystallize and grow, and a functional layer is crystallized on the Ge layer, and an electronic component is formed in the functional layer. A Si wafer, a barrier layer provided on the wafer and having an opening and inhibiting crystal growth, a Ge layer formed in the opening, a functional layer formed after forming the Ge layer, and an electron formed in the functional layer The electronic device of the component. (Embodiment 17) Fig. 62 shows a scanning electron microscope image of a cross section of a crystal in a fabricated semiconductor wafer. Fig. 63 shows an abbreviated diagram displayed based on the purpose of making the image of Fig. 62 easier to see. The semiconductor wafer is fabricated by the following method. An Si wafer 2202 having a (100) plane as a main surface is prepared, and a 〇2 film 2204 as an insulating film is formed over the Si wafer 2202. In the Si〇2 film 2204, an opening 105 reaching the main surface of the Si wafer 2202 is formed, and then Si is exposed inside the opening 1〇5 by a CVD method using a single crystal germanium as a raw material. The main surface of the wafer 22〇2 forms a Ge crystal 2206. The Si wafer 2202, the Si〇2 film 2204, and the Ge ® crystal 2206 are equivalent to the s丨 crystal layer 166, the barrier layer 1, and the Ge crystal 106, respectively. Further, GaAs crystal 2208 as a seed compound semiconductor is formed in Ge crystal 2206 by using M0CVD method using trimethyl gallium (1:1^11^1±71 311111111) and piece of arsine as raw materials. Grow up above. GaA.s crystal 2208 is equivalent to seed compound semiconductor crystal 1〇8eGaAs crystal 22〇8 growth 'first low temperature growth at 550 ° C, then grow at 640 ° C temperature ' at 640 C temperature 05 kPa。 The arsine partial pressure system is 0. 05 kPa. As a result, it was confirmed that the GaAs crystal 2208 was grown on the Ge crystal 2206. Further, it was confirmed that the (110) plane appeared on the seed surface of the GaAs crystal 2208. Then, GaAs crystal 2208 which is a laterally grown compound semiconductor layer is grown. The growth temperature at the time of lateral growth is "re, the partial pressure of arsine is 0.43 kPa. Fig. 64 shows a scanning electron microscope image of the obtained crystal cross section. Fig. 65 shows that based on Fig. 64 The image is easier to see. 83 321546 201019376 The graph is displayed. It can be confirmed from the figure that the GaAs crystal 22〇8 has a lateral growth surface on the Si〇2 film 2204, and it can be confirmed that the GaAs crystal &amp; (10) is also in the SiCh film. 2204 is laterally grown. Since the laterally grown portion is a defect-free region, an electronic device having excellent performance can be formed by forming a device in the laterally grown portion. (Example 18) 17 Similarly, the Ge crystal 2206 is selectively grown on the Si wafer 2202 to form a semiconductor wafer. The semiconductor wafer is subjected to cyclic annealing treatment at a temperature of 800 t and 680 t. A radiographic analyzer (hereinafter sometimes referred to as EDX) evaluates the element concentration of Si and Ge at the interface between the crystal 22〇6 and the si wafer 2202 in a semiconductor wafer (hereinafter referred to as a sample). In addition, the same The Ge crystal is selectively grown on the wafer 22〇2 to form a semiconductor wafer, but the semiconductor wafer is not subjected to a cyclic annealing treatment (hereinafter referred to as a sample B), and is also EDX-paired. The evaluation is carried out. Figure 66 shows the side profile of the element of the sample VIII. Figure 67 shows the side profile of the element with respect to sample A. Figure 68 shows the side wheel of the &amp; element of sample b Fig. 69 shows the side profile of the Ge element of sample B. Figure 7 shows a schematic view based on the purpose of making the figures 66 to 69 easier to see. It can be confirmed from the figure: in sample B, Si The interface between the wafer 22〇2 and the crystal is steep. In contrast, the interface in the sample A is ambiguous, showing the diffusion of Ge into the Si wafer 22〇2. The Si wafer 22〇 2. 〇2 film 2204' and Ge crystal 22〇6 are respectively equivalent to &amp; wafer (4), resist 321546 84 201019376 barrier layer 2104, Ge crystal 2106. For sample A and sample B, define Si wafer 2202 and Ge The measurement area in the interface of crystallization 2206, and the element intensity integral of Si and Ge Fig. 71 shows an SEM image of the measurement area of the sample A. The measurement area of the elemental intensity integral value is shown in Fig. 71 (SEM image) where the Ge crystal 2206 exists on the Si wafer 2202. The interface between the Si wafer 2202 and the Ge crystal 2206 (the interface observed in the SEM image) is further penetrated from the side of the Si wafer 2202 to a position of 1 to 5 nm. Figure 72 shows the first? ! The elemental intensity integral values of y and Ge of the measurement area shown in the figure. Figure 73 shows an SEM image of the measurement area of the sample β. Fig. 74 shows the element intensity integral values of Si and Ge with respect to the measurement area shown in Fig. 73. It can be seen from the figure that in the case of the sample ,, the signal of Ge is not detected, and only the signal of Si is detected. In the case of sample A, a larger signal of Ge is detected. From this, it is understood that in the case of the sample A, Ge diffuses into the Si wafer 2202.找出 Find out the Si intensity in the crystal 2202 and the Si intensity in the scratch film 2204 when the region where the Si wafer 2202 is in contact with the SiCh film 2204 is used to trace the 'juju direction intensity rib of the element. The sum is 5, and this position is defined as the interface between the Si wafer 2202 and the Ge crystal, and the elemental intensity of each element of Ge and Si in the range of 5 to 1 nm from the interface to the 22G2 side of the Si wafer is measured. ratio. The integrated value in the depth direction of each of the elements is calculated from the intensity ratio of each element, and the product (Ge/Si) is calculated. As a result, the ratio of the sample A was 3 33 , and in the case of the sample B, it was 321546 85 201019376 1. 10. Thus, the average concentration of Ge in the range of 5 to 10 nm from the interface of the Si wafer 2202 and the Ge crystal 2206 to the side of the Si wafer 2202 is calculated, which is 77% in the sample A, and in the sample B. It is 52%. Observation of the difference between the sample A and the sample B by a transmission electron microscope revealed that the sample A did not have a difference in the surface of the Ge crystal 2206. On the other hand, in the sample B, it was found that there was a difference in the density reaching the crystal surface at a density of lxl09cnf2. From the above results, it is understood that the implementation of the cyclic annealing treatment has the effect of reducing the difference between the Ge crystals 2206. (Example 19) GaAs On the Ge crystal 2206 subjected to the cyclic annealing treatment as in the sample A of Example 18, the GaAs crystal 2208 was grown by the MOCVD method, and the GaAs layer and the GaAs layer were laminated on the GaAs crystal 2208. Sample C was prepared by a multilayer structure film composed of an InGaP layer. Further, a sample D was prepared by forming a GaAs crystal 2208 and a multilayer structure film as described above except that the Ge crystallization 2206 was not post-annealed. For the sample C and the sample D, an EDX measurement as in Example 18 was carried out, and Ge and Si in the range of 5 to 1 Onm from the interface of the Si wafer 2202 and the Ge crystal to the side of the Si wafer 2202 were measured. The elemental intensity ratio of each element. Further, the integrated value in the depth direction is calculated, and then the ratio (Ge/Si) of the integrated values of both Ge and S i is calculated. The ratio was 2.28 in sample C and 0.60 in sample D. Thus, the average concentration of Ge in the range of 5 to 10 nm from the interface between the Si wafer 2202 and the Ge crystal to the Si wafer 2202 side was calculated, and was 70% in the sample C and 38% in the sample D. For the sample C and the sample D, observation was carried out by a transmission electron microscope and 86 321546 201019376 ', and it was found that the sample C did not have a difference in the multilayer structure film composed of the GaAs layer and the InGaP layer. On the other hand, in the sample D, a difference in the arrival of the multilayer structure film composed of the GaAs layer and the InGaP layer was observed. From the above results, it can be seen that when the average concentration of Ge in the range of 5 to 1 Onm from the interface between the Si wafer 2202 and the Ge crystal to the Si wafer 2202 is 60% or more, it is possible to form a Ge crystal. High quality compound semiconductor layer. More preferably, the average concentration of Ge is 70% or more. (Embodiment 20) In Embodiment 20, the experimental data of the inventors according to the present invention is used to change the growth rate of the film for a device caused by changing the width of the barrier layer. Here, the film for a device refers to a film which is processed as a part of a semiconductor device after being processed by a film for a device. When a plurality of layers of the compound semiconductor thin film are sequentially laminated on the tantalum crystal, and the compound semiconductor thin film formed by lamination is processed to form a semiconductor device, the compound semiconductor thin film formed by lamination is a film for a device. Further, the buffer layer formed between the compound semiconductor thin film formed by the layer deposition and the germanium crystal is also a film for a device, and the seed layer of the crystal-growth core as a buffer layer or a compound semiconductor film is also a film for a device. The growth rate of the film for the device affects the properties of the film for a device such as flatness and crystallinity. The characteristics of the film for a device greatly affect the characteristics of the semiconductor device formed on the film for the device. Therefore, it is necessary to appropriately control the growth rate of the film for a device to satisfy the required characteristics of the film for a device derived from the specifications of the semiconductor device. The experimental data shown below shows that the growth rate of the film for the device varies depending on the width of the barrier layer 87 321546 201019376 and the like. Using the experimental data, the shape of the barrier layer can be designed, and the growth rate of the film for the device can be appropriately increased from the required specifications of the film for the device. Fig. 75 is a view showing the planar pattern of the wafer 3000 for a semiconductor device fabricated in the twenty-first embodiment. The semiconductor device wafer 3 has a barrier layer 3002, a device film 3004, and a sacrificial growth portion 3〇〇6 on the base wafer. The barrier layer 3002, the device film 3004, and the sacrificial growth portion 3〇〇6 are formed so that the barrier layer 3002 surrounds the device film 30〇4, and the sacrificial growth portion 3〇〇6 surrounds the barrier layer 3002. The barrier layer 3002 is formed to have a substantially square outer shape, and a substantially square opening portion is formed at a central portion of the square. One side a of the opening is made 30/zm or 50/zm. The distance b from the outer periphery to the inner periphery of the barrier layer 3〇〇2, that is, the width b of the barrier layer 3〇〇2 is changed within the range of 5# melon to private m. Cerium oxide (Si 〇〇 is used as the barrier layer 3002. The cerium oxide does not epitaxially grow on the surface under the epitaxial growth condition of M CVD. The barrier layer 3002 is used by dry thermal oxidation. A germanium dioxide film is formed on a base wafer, and the germanium dioxide film is patterned by photolithography. On the base wafer other than the barrier layer 3002, the &lt;RTIgt; The semiconductor crystal is selectively epitaxially grown. The compound semiconductor crystal which is epitaxially grown in the opening surrounded by the barrier layer 3002 is the device film 3004, and the compound half crystal of the barrier layer 3〇〇2 is surrounded on the outer side of the barrier layer 3002. Then, the growth portion 3006 is sacrificed. QaAs crystallized, inQap crystal, or P-doped GaAs crystal (p-GaAs crystal) is grown as a compound 321546 88 201019376 • Semiconductor crystal. Using trimethyl gallium (Ga(CH3)3) As a Ga raw material, a hydrogen hydride (AsH3) was used as an As raw material. Trimethyl indium (In(CH3)3) was used as an In raw material, and phosphine (PH3) was used as a P raw material. The doping of carbon (c) is based on The amount of the deodorant dichlorophyll (CBrCls) added is controlled as a dopant (d〇pant). The reaction temperature at the time of epitaxial growth is 61 ° C. Fig. 76 shows that the device is used as a device. The film 3004 and the graph of the relationship between the growth rate of the film 3〇〇4 for the device GaAs crystal growth of the thin film 3004 and the sacrificial growth portion 3006 and the width of the barrier layer 3002. Fig. 77 shows the film for the device. 3004 and a graph showing the relationship between the growth rate of the device film 3004 and the area ratio at the time of GaAs epitaxial growth of the sacrificial growth portion 3006. Fig. 78 shows the growth of InGaP as the device film 3004 and the sacrificial growth portion 3006. A graph showing the relationship between the growth rate of the film 3〇〇4 and the width of the barrier layer 3002 in the case of the device. Fig. 79 shows a film for a device when the InGaP as the device film 3004 and the sacrificial growth portion 103006 is epitaxially grown. A graph showing the relationship between the growth rate of 3004 and the area ratio. Fig. 80 shows the growth rate of the film 3004 for the device and the barrier layer 3002 when the p-GaAs is grown as the device film 3004 and the sacrificial growth portion 3006. width Fig. 81 is a graph showing the relationship between the growth rate and the area ratio of the film 3004 for the device when the p-GaAs crystallites for the device film 3004 and the sacrificial growth portion 3006 are grown. In each of the graphs of Fig. 81, the vertical axis represents the growth rate ratio of the compound semiconductor crystal. The growth rate ratio is assumed to be on the entire plane at a growth rate of 1 on the entire plane of the barrier layer 3002 without the barrier layer 3002. The ratio of the growth rate to the growth rate. The area ratio is the ratio of the area of the region for forming the device film 3004 to the total area of the area where the film for forming the device 3004 is formed and the area of the region where the barrier layer 3 0 0 2 is formed. In each figure, the plotted points marked with black squares or black diamonds represent the actual measurement points. The solid line indicates the experimental line. The experimental line is a quadratic function of a variable, which is obtained by finding the coefficients of each polynomial by the least square method. For comparison, the growth rate ratio of the film stack 3004 for the device without sacrificing the growth portion 3006 is indicated by a broken line. L1 is a case where the opening area of the barrier layer 3002 is 50 // m□, and L2 is a case where the opening area of the barrier layer 3002 is 30 /z m. The case where the growth portion 3006 is not sacrificed means that the barrier layer 3002 also covers the region corresponding to the sacrificial growth portion 3006. As shown in the respective figures of Figs. 76 to 81, the larger the width of the barrier layer 3002, the larger the growth rate, and the smaller the area ratio, the higher the growth rate. Moreover, the experimental line is quite consistent with the measurement point. From this, it can be seen that the design of the barrier layer 3002 can be performed. ◎ It is expected that the desired growth rate can be achieved by using the quadratic function of the experimental line. Further, the results of such an experiment can be considered to be explained by the growth mechanism of the crystals as described below. Also, the crystal raw materials (Ga and As atoms) in the film formation are thought to be supplied by molecules flying from space or molecules moving on the surface. The inventors of the present invention considered that in the reaction environment of MOCVD such as selective growth of stray crystals, the supply of the crystal raw material by the molecules on the surface migration is the main source of supply. In this case, the raw material molecules (precursors) that have flown to the barrier layer 3002 are transferred to the surface of the barrier layer 3002 in addition to the surface 90 321546 201019376, and are supplied to the device film 3004 or the sacrificial growth portion 3006. . When the width of the barrier layer 3002 is large, the absolute number of the raw material molecules supplied by the surface migration is increased, and the growth rate of the device film 3004 is increased. Further, when the area ratio of the device film 3004 to the total area is small, the amount of the raw material molecules supplied from the barrier layer 3002 to the device film 3〇〇4 is relatively large. Therefore, the growth rate of the film for film 3004 becomes large.

❹ 以如上所述之成長機制作為基礎’就可如以下般瞭解 犧牲成長部3006的功能。亦即，假使沒有犧牲成長部3〇〇6 的話，就會有過多的原料分子供給至裝置用薄膜3〇〇4，導 致裝置用薄膜3004的表面紊礼及結晶性降低。換言之，因 為有犧牲成長部3006存在，所以有犧牲成長部3〇〇6適度 地接收飛來到阻礙層3002之原料分子，而將供給至裝置用 薄膜3004的原料分子的量控制在適當的量。犧牲成長部 3006可謂具有讓原料分子犧牲成長而消耗掉，以抑制過多 的原料分子供給至裝置用薄膜3〇〇4之功能。 、第82及83圖係顯示觀察使基底晶圓的傾斜角為厂時 之半導體裝置用晶圓3GGG的表面所見之電子顯微鏡影 像。第82圖係觀察蠢晶成長後的狀態所見者，第83圖係 觀察退火處理後的狀態所見者。第84及85圖係顯示觀察 :基底晶圓的傾斜角為6。時之半導體裝置用晶圓3〇〇〇的 =所見之電子顯微鏡影像。第84圖係觀察蠢晶成長後的 ^態所見者’第85圖係觀察退火處理後的狀態所見者。此 處所謂的傾斜角，係指作為基底晶圓之㈣表面相對於結 321546 91 201019376 晶學上的面方位，即（1 〇〇)面傾斜的角度。 · 如第82及84圖所示，傾斜角為2。時之結晶表面相較 · 於傾斜角為6°時之結晶表面，表面的紊亂較小。因此傾斜 角2°比傾斜角6°為佳。如第83及85圖所示，退火處理後 的結晶表面則不論在什麼傾斜角都很良好。由此可知：只 要傾斜角在2°至6°的範圍内皆可讓結晶良好地成長。 (實施例21) 第86圖係顯示本發明的發明人等製造的異質接面雙 極性電晶體（HBT)3100之平面圖。HBT 3100具有將20個 ❹ HBT元件3150並聯連接而成的構造。第86圖中只顯示基 底晶圓的一部份，只顯示一個HBT 3100的部份。同一個基 底晶圓上雖也形成有測試圖案（test pauern)等半導體元 件，但此處省略其說明。 . 20個HBT元件3150之各個元件的集極係以集極配線 3124予以並聯連接，各個元件的射極係以射極配線幻26 予以並聯連接’各個元件的基極係以基極配線3128予以並 聯連接、。而且，2G個基極係分為四組，且將各組的五個* 〇 極予以並聯連接。集極配線3124連接至集極焊塾（c〇Uect or pad)3130，射極配線3126連接至射極焊墊Μ%，基極 配線3128連接至基極焊塾3134。集極配線犯*、集極焊 塾3130射極配線3126及射極烊塾形成於同一個第 一配線層，基極配線3128及基極焊墊3134形成於在第-配線層的上層之第二配線層。 第87圖係顯不第86圖中以虛線圍起的部份之顯微鏡 321546 92 201019376 影像。第88圖係放大顯示第87 元件315G的部份之平_ ^ 線園起的三個腿 π Η切之千面圖。集極配線31 電極3116，射極配结丄 系連接至木極 耵棧配線312 6係經由射極引出 接至射極_ 3112，基極 讀3122而連 3120而遠接… 係蛵由基極引出配線 配線3122及其1 3114。集極配線如、射極引出 -線3122及基極引出配線312q的下 絕緣膜3118，HBT元件⑽及犧 成杨⑴⑽ Ο 3124、射則Λ配線3122 。卩和集極配線 由場猫缝胺川。 5丨出配線3120之間係藉 麥、邑緣膜3118而絕緣。場絕緣膜311 礙層，聰元件3150形成於阻礙層3== 域。第89圖係觀窣抓了 i斤包圍的區 鏡影像。觀察腿讀315G的區域所見之雷射顯微 第9〇至94圖係顯示HBT元件315〇的 之平面圖。準備作為基底晶圓之石夕晶圓’在=基底晶圓之 上以乾式熱氧化法軸二氧切膜。錢&quot;' 示，使用光刻法使二氧化侧案化，而形成阻L: “如弟91圖所示，使用選擇性磊晶法，在阻礙層讀 所包圍的區域形成裝置用薄膜咖，在包圍阻礙層謂 之周圍的區域形成犧牲成長部3110。裝置用薄膜·，係 在作為基底晶圓之矽晶圓上，依序層積Ge種子層、緩衝 f、次集極（sub-collector)層、集極層、基極層、射極層、 次射極層而形成。在裝置用薄膜3108的積層中，在射極層 成長後、次射極層成長前，暫時使砷化氫（arsine)的流量 為〇，在氫氣環境下’以670°C、3分鐘的條件進行退火處 321546 93 201019376 理 如第92圖所示，在裝置用薄祺 ㈣’再以射極電極3112作為遮革而在裝置用薄=極 形成射極台面（emitter mesa)。在形成知搞a ' 08 裝置用薄膜3刚姓刻到讓基極層露出的深度口。接==將 成集極電極㈣的區域形錢極台面。在形成集心2 階段將裝置用薄膜細飯刻到讓:欠集掩層露。面的 «置用薄膜誦的周邊料料刻—離度台= (1solation mesa) 〇 ° 面 © 如第93圖所示，全面形成二氧化矽膜而形 再在場絕緣膜咖開設連接到基極層 形成基極電極3114。再在場絕_ 3m開設連;^ 極層之連接孔織形成集極電極_。射極電極 = 極電極3114及集極電極3116係以錄（Ni)及金（Au)之居二 膜形成。射極電極3112、基極電極3114及集極電極^ 係以剝離（liftoff)法形成。如此而形成ΗΒΤ元件315〇。❹ Based on the growth mechanism described above, you can understand the function of the sacrifice growth unit 3006 as follows. In other words, if the growth unit 3〇〇6 is not sacrificed, too many raw material molecules are supplied to the film 3〇〇4 for the device, and the surface of the film 3004 for the device is deteriorated and the crystallinity is lowered. In other words, since the sacrificial growth portion 3006 exists, the sacrificial growth portion 3〇〇6 appropriately receives the raw material molecules flying to the barrier layer 3002, and controls the amount of the raw material molecules supplied to the device film 3004 to an appropriate amount. . The sacrificial growth unit 3006 has a function of allowing the raw material molecules to be sacrificed and grown, and suppressing the supply of excessive raw material molecules to the device film 3〇〇4. Figs. 82 and 83 show an electron microscope image seen on the surface of the wafer 3GGG for a semiconductor device when the tilt angle of the base wafer is made. Fig. 82 shows the state after observing the growth of the stray crystal, and Fig. 83 shows the state observed after the annealing treatment. Figures 84 and 85 show the observation that the base wafer has a tilt angle of 6. At the time of the semiconductor device wafer 3 = = the electron microscope image seen. Fig. 84 is a view of the state of the observed state after the growth of the stray crystal. Fig. 85 shows the state observed after the annealing treatment. The so-called tilt angle here refers to the crystal orientation of the (4) surface of the base wafer relative to the junction 321546 91 201019376, that is, the angle at which the (1 〇〇) plane is inclined. · As shown in Figures 82 and 84, the tilt angle is 2. When the surface of the crystal is compared with the surface of the crystal at a tilt angle of 6°, the surface disorder is small. Therefore, the inclination angle of 2° is better than the inclination angle of 6°. As shown in Figs. 83 and 85, the crystal surface after the annealing treatment is excellent regardless of the inclination angle. From this, it can be seen that the crystal can be grown well as long as the inclination angle is in the range of 2° to 6°. (Embodiment 21) Fig. 86 is a plan view showing a heterojunction bipolar transistor (HBT) 3100 manufactured by the inventors of the present invention. The HBT 3100 has a structure in which 20 ❹ HBT elements 3150 are connected in parallel. In Fig. 86, only a portion of the base wafer is shown, showing only one portion of the HBT 3100. Although a semiconductor element such as a test pattern is formed on the same base wafer, the description thereof is omitted here. The collectors of the respective elements of the 20 HBT elements 3150 are connected in parallel by the collector wiring 3124, and the emitters of the respective elements are connected in parallel by the emitter wiring illusion 26, and the base of each element is connected by the base wiring 3128. Connected in parallel. Moreover, the 2G base systems are divided into four groups, and the five * 〇 poles of each group are connected in parallel. The collector wiring 3124 is connected to a collector pad 3130, the emitter wiring 3126 is connected to the emitter pad Μ%, and the base wiring 3128 is connected to the base pad 3134. The collector wiring harness*, the collector pad 3130 emitter wiring 3126, and the emitter electrode are formed on the same first wiring layer, and the base wiring 3128 and the base pad 3134 are formed on the upper layer of the first wiring layer. Two wiring layers. Figure 87 shows the microscope 321546 92 201019376 image of the portion enclosed by the dotted line in Figure 86. Fig. 88 is an enlarged view showing the three legs of the portion of the 87th element 315G, which are 平 Η Η 。 。 。. Collector wiring 31 electrode 3116, emitter-coupled lanthanum is connected to the wood-pole stack wiring 312 6 is connected to the emitter _ 3112 via the emitter, and the base is read 3122 and connected to the 3120 and the remote is connected... The wiring wiring 3122 and its 1 3114 are taken out. The collector wiring includes, for example, the lower insulating film 3118 of the emitter lead-out wire 3122 and the base lead-out wiring 312q, the HBT element (10), and the sacrificial Yang (1) (10) Ο 3124 and the emitter Λ wiring 3122.卩 and collector wiring. 5 The wiring 3120 is insulated by the wheat and enamel film 3118. The field insulating film 311 is a barrier layer, and the smart element 3150 is formed in the barrier layer 3 == domain. Figure 89 shows the image of the area surrounded by the ijin. Laser microscopy seen in the area where the leg reading 315G is observed. Figures 9 to 94 show a plan view of the HBT element 315. It is prepared to use a dry thermal oxidation method for the dioxo prior film as a base wafer. The money &quot;' shows that the photo-oxidation method is used to form the second side of the oxide, and the resistance L is formed: "As shown in Fig. 91, using the selective epitaxial method, the film for the device is formed in the region surrounded by the barrier layer reading. The sacrificial growth portion 3110 is formed in a region surrounding the barrier layer. The film for the device is laminated on the germanium wafer as the base wafer, and the Ge seed layer, the buffer f, and the second collector are sequentially stacked (sub- The collector layer, the collector layer, the base layer, the emitter layer, and the second emitter layer are formed. In the laminate of the device film 3108, arsenic is temporarily made after the growth of the emitter layer and before the growth of the secondary emitter layer. The flow rate of hydrogen (arsine) is 〇, and it is annealed at 670 ° C for 3 minutes in a hydrogen atmosphere. 321546 93 201019376 As shown in Fig. 92, the device uses a thin crucible (4) and then an emitter electrode 3112. As a shadowing device, an emitter mesa is formed by a thin electrode at the device. In the formation of a film for the 'a' 08 device, the film is just pasted to the depth of the base layer. The connection == will become a collector. The area of the electrode (4) is shaped like a micro-top. In the stage of forming the center 2, the device is engraved with a thin film of rice to let: The cover layer is exposed. The surface of the film is etched - the degree of separation is = (1solation mesa) 〇 ° face © as shown in Figure 93, the overall formation of the ruthenium dioxide film and then the field insulation film The coffee is connected to the base layer to form the base electrode 3114. The connection is opened at _3m; the connection hole of the pole layer is woven to form the collector electrode _. The emitter electrode = the electrode 3114 and the collector electrode 3116 are recorded The two films of (Ni) and gold (Au) are formed. The emitter electrode 3112, the base electrode 3114, and the collector electrode are formed by a liftoff method. Thus, the germanium element 315 is formed.

Q 如第94圖所示，形成連接至射極電極3112之射極 出配線3122、連接至射極引出配線3122之射極配線31扣、 連接至基極電極3114之基極引出配線312〇、連接至集極 電極3116之集極配線3124。射極引出配線3122、射;^配 線3126、基極引出配線312〇及集極配線3124係以鋁形成γ 然後全面形成覆蓋射極引出配線3122、射極配線3126、基 極引出配線3120及集極配線3124之聚醯亞胺膜來作為層 間絕緣膜。在層間絕緣膜之上，形成透過連接孔而連接^ 321546 94 201019376 圖所 基極引出配線3120之基極配線3128，而形成如第88 示之 HBT 3100。 第95至99圖係顯示對於製造出來的HBT 3100的各種 特性進行量測所得到的數據之曲線圖。第95圖顯示使基極 射極間的電壓變化時之集極電流及基極電流。四角形的描 、·曰點表不集極H三肖形的描繪點表示基極電流。第 圖顯示使基極-射極間的電㈣化時之電流放大率。電流放 大率從基極-射極間電壓為約115 v附近開始增加，在基 β極-射極間電壓到達h47 v時到達最大電流放大率1〇6。 第97圖顯不相對於集極電壓之集極電流。第9了圖中顯示 四個系列之使基極電壓變化時之數據。第97圖顯示出集極 電流在廣範_#極電__穩定流動之情形。第⑽圖 顯示用來求出電流放大率為.i的截止頻率（cut〇ff frequency)之實驗數據。在基極_射極間電壓為5v之情 況付到截止頻率15 GHz之值。第99圖顯示用來求出電流 ❹放大率為1的最大振盪頻率之實驗數據。在基極_射極間電 壓為1.45 V之情況得到最大振盪頻率9 GHz之值。 第100圖係在已形成裝置用薄膜3108之階段對於以二 次離子質量分析法進行深度濃度輪廓的量測所得到的數 據。圖中’ As原子濃度、c原子濃度、InGaAs中之Si原 子濃度、及GaAs中之Si原子濃度值分別對應於深度而顯 示。範圍3202為作為次射極層及射極層之GaAs及InGap。 範圍3204為作為基極層之p_GaAs。範圍3206為作為集極 層之n-GaAs。範圍3208為作為次集極層之n+(jaAs及作為 95 321546 201019376 蝕刻阻擋層之InGaP。範圍3210為作為緩衝層之GaAs及 -Q, as shown in Fig. 94, an emitter lead wiring 3122 connected to the emitter electrode 3112, an emitter wiring 31 connected to the emitter lead wiring 3122, and a base lead wiring 312 connected to the base electrode 3114 are formed, Connected to the collector wiring 3124 of the collector electrode 3116. The emitter lead wiring 3122, the radiation wiring 3126, the base lead wiring 312, and the collector wiring 3124 are formed of γ by aluminum, and then the entire surface of the emitter lead wiring 3122, the emitter wiring 3126, the base lead wiring 3120, and the set are formed. The polyimide film of the pole wiring 3124 serves as an interlayer insulating film. On the interlayer insulating film, a base wiring 3128 which is connected to the base lead wiring 3120 of the figure 321546 94 201019376 is formed through the connection hole to form the HBT 3100 as shown in FIG. Figures 95 to 99 show graphs of data obtained by measuring various characteristics of the manufactured HBT 3100. Fig. 95 shows the collector current and the base current when the voltage between the base and the emitter is changed. The description of the quadrangle, the point of the 曰 point, and the point of the collector of the three H-Shaw represents the base current. The figure shows the current amplification when the base-emitter is electrically (four). The current amplification rate starts from a base-emitter voltage of about 115 volts, and reaches a maximum current amplification factor of 1 〇6 when the voltage between the base β pole and the emitter reaches h47 v. Figure 97 shows the collector current relative to the collector voltage. Figure 9 shows the data for the four series of changes in the base voltage. Fig. 97 shows the case where the collector current flows stably in the wide range _# pole power__. Figure (10) shows the experimental data used to find the cutoff frequency of the current amplification factor of .i. The value of the cutoff frequency of 15 GHz is applied to the case where the voltage between the base and the emitter is 5 volts. Figure 99 shows the experimental data used to find the maximum oscillation frequency of the current ❹ amplification factor of 1. The maximum oscillation frequency of 9 GHz is obtained with a base-emitter voltage of 1.45 V. Fig. 100 is a graph showing the measurement of the depth concentration profile by the secondary ion mass spectrometry at the stage of forming the film 3108 for the device. In the figure, 'As atom concentration, c atom concentration, Si atom concentration in InGaAs, and Si atom concentration value in GaAs are respectively shown corresponding to depth. The range 3202 is GaAs and InGap which are the secondary emitter layer and the emitter layer. The range 3204 is p_GaAs as a base layer. The range 3206 is n-GaAs which is a collector layer. The range 3208 is n+ (jaAs and InGaP as an etch barrier of 95 321546 201019376 as the secondary collector layer. The range 3210 is GaAs as a buffer layer and -

AlGaAs。範圍3212為作為種子層之Ge。 · 第101圖顯示與HBT 3100同時形成之HBT的斷面之 TEM影像。圖中顯示：在矽322〇上依序形成Ge層3222、 緩衝層3224、次集極層3226、集極層3228、基極層3230、 次射極層及射極層3232。以及，與次集極層3226接觸而 形成集極電極3234 ’與基極層3230接觸而形成基極電極 3236 ’與射極層3232接觸而形成射極電極3238之情形。 第102圖係為了比較而顯示之TEM影像，顯示在沒有 ❹ 阻礙層之整個晶圓形成裝置用薄膜而作成之HBT。在圖中 標示為3240之區域觀察到很多的結晶缺陷，且缺陷到達 HBT的活性區域，亦即到達射極-基極-集極區域。另一方 面’·第101圖所示之HBT中，結晶缺陷卻極少。此外，在 第101圖所示之HBT可得到值為123之最大電流放大率， 在第102圖所示之HBT則只不過30之最大電流放大率。 以上的說明中之電子裝置，可為例如MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)。但電 子裝置並不限於MOSFET，除了 M0SFE1T之外，亦可為例如 HEMT(High Electron Mobility Transistor)、假晶 HEMT (pseudomorphic-HEMT)。此外，電子裝置100可為例如 MESFETCMetal-Semiconductor Field Effect Transistor ;金屬半導體場效電晶體）等。 以上，雖然利用實施形態而進行了本發明的說明’惟 本發明之技術上的範圍並不受上述實施形態中記載的範圍 96 321546 201019376 • 所限定。可在上述實施形態 .本技術賴的業者而言均為自^變更歧良’對於 記載可清楚看出，增加了各二而變易:;從申請專伽 在本發明的技術範圍之内。變更或改良之形態也包含 另外，應注意的是··申請專 中顯示的裝置、系統、程式、及方=說明書、及圖式 驟、及階段等的各處理的執 卜之動作、程序、步 「先 執仃眞序，除非特別載明「之前」、 否pt: 的處理的輪出用在之後的處理」， 否貝j均可以任意的順序實規 說明查、月㈣士 外，關於申請專利範圍、 ㈣式中的動作流程，即使為了方便而❹ ΐ」。、其次」等進行說明，但並不表示—定要依此順序實 記載=上=書::有;:序層積各元素的層積方向 ❹ 向。限定為f子裝置100等之使用時朝上的方 形成、成於〇〇上」’係表示在層積方向 而形成之产所明職於◦◦上」，不僅限於與對象相接 【圖也包含隔著別的層而形成之情況。 【圖式簡單說明】 第1圖概略地顯示半導體裝置10 _面之一例。 第2圖概略地顯示半導體裝置2〇的斷面之一例。 第3圖概略地顯示半導體裝置3〇的斷面之一例。 第4圖概略地顯示半導體裝置4〇的斷面之一例。 第5圖顯示一實施形態之電子裝置100的平面例。 321546 97 201019376 第6圖顯示第5圖中之A-A線斷面。 第7圖顯示第5圖中之B-B線斷面。 第8圖顯示電子裝置1〇〇的製造過程的斷面例。 第9圖顯示電子裝置1 〇 〇的製造過程的斷面例。 第10圖顯示電子裝置1〇〇的製造過程的斷面例。 第11圖顯示電子裝置1〇〇的製造過程的斷面例。 第12圖顯示電子裝置1〇〇的製造過程的斷面例。 第13圖顯示電子裝置1〇〇的其他製造過程的斷面例。 第14圖顯示電子裝置1〇〇的其他製造過程的斷面例。 第15圖顯示電子裝置200的平面例。 第16圖顯示電子裝置300的平面例。 第17圖顯示電子裝置400的斷面例。 第18圖顯示電子裝置500的斷面例。 第19圖顯示電子裝置600的斷面例。 第20圖顯示電子裝置7〇〇的斷面例。 第21圖顯示半導體晶圓8〇1的平面例。 第22圖擴大顯示區域803。 第23圖顯示半導體晶圓801的斷面例，其中同時顯示 成於卩且礙層804所被覆之被覆區域的開口 806之HBT。 第24圖顯示本實施形態之半導體晶圓“Μ的平面例。 _ ，第25圖顯示半導體晶圓1101的斷面例，其中同時顯 不形成於島狀的Ge結晶層1120之HBT。 第26圖顯示半導體晶圓1101的製造過程的斷面例。 第27圖顯示半導體晶圓1101的製造過程的斷面例。 321546 98 201019376 ' 第28圖顯示半導體晶圓1101的製造過程的斷面例。 ' 第29圖顯示半導體晶圓1101的製造過程的斷面例。 第30圖顯示半導體晶圓1101的製造過程的斷面例。 第31圖顯示半導體晶圓1201的斷面例。 第32圖顯示半導體晶圓1201的製造過程的斷面例。 第33圖顯示半導體晶圓1201的製造過程的斷面例。 第34圖顯示半導體晶圓1301的斷面例。 第35圖顯示半導體晶圓1301的製造過程的斷面例。 ❹ 第36圖顯示作成的半導體晶圓的斷面之示意圖。 第37圖顯示未進行退火處理之Ge結晶層2106的斷面 形狀。 第38圖顯示以700°C進行過退火處理之Ge結晶層 2106的斷面形狀。 第39圖顯示以800°C進行過退火處理之Ge結晶層 2106的斷面形狀。 ©第40圖顯示以850°C進行過退火處理之Ge結晶層 2106的斷面形狀。 第41圖顯示以900°C進行過退火處理之Ge結晶層 2106的斷面形狀。 第42圖顯示實施例9中之化合物半導體2108的膜厚 的平均值。 第43圖顯示實施例9中之化合物半導體2108的膜厚 的變動係數。 第44圖顯示實施例10中之化合物半導體2108的膜厚 99 321546 201019376 的平均值。 第45圖顯示實施例10中之化合物半導體21〇8的電子 顯微鏡影像。 第46圖顯示實施例1〇中之化合物半導體21〇8的電子 顯微鏡影像。 第47圖顯示實施例10中之化合物半導體21〇8的電子 顯微鏡影像。 第48圖顯示實施例1〇中之化合物半導體2108的電子 顯微鏡影像·。 第49圖顯示實施例10中之化合物半導體21〇8的電子 顯微鏡影像。 第50圖顯示實施例11中之化合物半導體2108的電子 顯微鏡影像。 第51圖顯示實施例11中之化合物半導體2108的電子 顯微鏡影像。 第52圖顯示實施例11中之化合物半導體2108的電子 顯微鏡影像。 第53圖顯示實施例11中之化合物半導體2108的電子 顯微鏡影像。 第54圖顯示實施例11中之化合物半導體2108的電子 顯微鏡影像。 第55圖顯示實施例12中之化合物半導體2108的電子 顯微鏡影像。 第56圖顯示實施例12中之化合物半導體21〇8的電子 321546 100 叫峋376 .、繞影像。 第57 繞影7係圖顯示實施例12中之化合物半導體纖的電子 第 58 fa 影像。_顯示實施例13中之半導體晶圓的電子顯微鏡 第59廟 第6〇澈顯不實施例14中之HBT元件的雷射顯微鏡像。 ® » 61 ^示實施例15中之電子元件的雷射顯微鏡像。 之關係。顯示HBT元件的電氣特性、與開口區域的面積 第62屬 第顯示結晶的斷面的掃描式電子顯微鏡影像。 顯禾的慕^顯示基於使第62圖的影像更容易看之目的而 圖。 苐64阑一 第65 _顯示結晶的斷面的掃描式電子顯微鏡影像。 1員示的摹7顯示基於使第64圖的影像更容易看之目的而 ® h舄圖。 ^ 66 jg, _ _ 第67顯示關於試料A之Si元素的側面輪廓。 第S鞫顯示關於試料AiGe元素的侧面輪廓。 …8圖顧示關於試料B之Si元素的側面輪廓。 弟69圖顯示關於試料B之Ge元素的侧面輪廓。 第70圖顯示基於使第66至69圖更容易看之目的而顯 示的示意圖。 第71圖顯示一 SEM影像，其中顯示關於試料A之量測 區域。 第72圖顯不關於第71圖中所示的量測區域之Si及 101 321546 201019376AlGaAs. The range 3212 is Ge as a seed layer. • Figure 101 shows a TEM image of the section of the HBT formed simultaneously with the HBT 3100. The figure shows that a Ge layer 3222, a buffer layer 3224, a sub-collector layer 3226, a collector layer 3228, a base layer 3230, a sub-emitter layer and an emitter layer 3232 are sequentially formed on the 矽322. Further, a contact is made with the sub-collector layer 3226 to form a collector electrode 3234' which is in contact with the base layer 3230 to form a base electrode 3236' which is in contact with the emitter layer 3232 to form an emitter electrode 3238. Fig. 102 is a view showing a TEM image displayed for comparison, and shows an HBT which is formed on the entire wafer forming apparatus film without the barrier layer. A large number of crystal defects are observed in the region indicated as 3240 in the figure, and the defects reach the active region of the HBT, that is, reach the emitter-base-collector region. On the other side, the HBT shown in Fig. 101 has very few crystal defects. In addition, the HBT shown in Fig. 101 can obtain a maximum current amplification value of 123, and the HBT shown in Fig. 102 is only a maximum current amplification ratio of 30. The electronic device in the above description may be, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). However, the electronic device is not limited to the MOSFET, and may be, for example, a HEMT (High Electron Mobility Transistor) or a pseudomorphic HEMT (pseudomorphic-HEMT) in addition to the MOSFE1T. Further, the electronic device 100 may be, for example, a MESFETCMetal-Semiconductor Field Effect Transistor; a metal semiconductor field effect transistor). As described above, the description of the present invention has been made by the embodiment. However, the technical scope of the present invention is not limited to the range of 96 321546 201019376. In the above-mentioned embodiments, it is obvious that the manufacturer of the present technology is arbitrarily changed. It is clear from the description that it is easy to increase the number of two: It is within the technical scope of the present invention from the application. The form of the change or the improvement is also included. It should be noted that the operation, program, and procedures of the processes, systems, programs, and instructions for the application, the instructions, the drawings, and the stages are Step "Before the order, unless the "previous" or "no" processing is used for the subsequent processing", no. The scope of the patent application and the action flow in (4) are even for convenience. And secondly, etc., but it does not mean that it must be recorded in this order = upper = book:: yes;: the lamination direction of each element of the sequential layer product. It is limited to the case where the f-sub-device 100 or the like is used, and the upper side is formed, and the upper side is formed on the 〇〇"", which means that the product is formed in the stacking direction, and is not limited to the object. It also includes the case where it is formed across other layers. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 schematically shows an example of a semiconductor device 10 _ plane. Fig. 2 schematically shows an example of a cross section of the semiconductor device 2A. Fig. 3 schematically shows an example of a cross section of the semiconductor device 3A. Fig. 4 is a view schematically showing an example of a cross section of the semiconductor device 4A. Fig. 5 shows a planar example of the electronic device 100 of the embodiment. 321546 97 201019376 Figure 6 shows the section A-A in Figure 5. Fig. 7 shows a section B-B in Fig. 5. Fig. 8 is a view showing a cross-sectional view of the manufacturing process of the electronic device 1A. Fig. 9 is a view showing an example of a manufacturing process of the electronic device 1 〇 。. Fig. 10 is a view showing a cross-sectional view of the manufacturing process of the electronic device 1A. Fig. 11 is a view showing an example of a cross section of the manufacturing process of the electronic device 1A. Fig. 12 is a view showing an example of a cross section of the manufacturing process of the electronic device 1A. Fig. 13 is a view showing a cross-sectional view of another manufacturing process of the electronic device 1A. Fig. 14 shows a cross-sectional view of another manufacturing process of the electronic device 1A. Fig. 15 shows a plane example of the electronic device 200. FIG. 16 shows a planar example of the electronic device 300. Fig. 17 shows an example of a cross section of the electronic device 400. Fig. 18 shows an example of a cross section of the electronic device 500. Fig. 19 shows an example of a cross section of the electronic device 600. Fig. 20 shows an example of a cross section of the electronic device 7A. Fig. 21 shows an example of the plane of the semiconductor wafer 8〇1. Figure 22 enlarges the display area 803. Fig. 23 shows an example of a cross section of the semiconductor wafer 801 in which the HBT of the opening 806 of the covered region covered by the barrier layer 804 is simultaneously displayed. Fig. 24 is a view showing a plane example of the semiconductor wafer of the present embodiment. _, Fig. 25 shows a cross-sectional example of the semiconductor wafer 1101 in which the HBT of the island-shaped Ge crystal layer 1120 is simultaneously formed. The figure shows a cross-sectional example of the manufacturing process of the semiconductor wafer 1101. Fig. 27 shows a cross-sectional example of the manufacturing process of the semiconductor wafer 1101. 321546 98 201019376 ' Figure 28 shows a cross-sectional example of the manufacturing process of the semiconductor wafer 1101. Fig. 29 shows a cross-sectional example of the manufacturing process of the semiconductor wafer 1101. Fig. 30 shows a cross-sectional example of the manufacturing process of the semiconductor wafer 1101. Fig. 31 shows a cross-sectional example of the semiconductor wafer 1201. Fig. 32 shows an example of the cross section of the semiconductor wafer 1201. A cross-sectional view of a manufacturing process of the semiconductor wafer 1201. Fig. 33 shows a cross-sectional view of a manufacturing process of the semiconductor wafer 1201. Fig. 34 shows a cross-sectional view of the semiconductor wafer 1301. Fig. 35 shows a semiconductor wafer 1301. A cross-sectional view of the manufacturing process. Fig. 36 is a schematic view showing a cross section of a fabricated semiconductor wafer. Fig. 37 shows a cross-sectional shape of a Ge crystal layer 2106 which has not been annealed. Fig. 38 shows a structure at 700 °C. Over-annealing The cross-sectional shape of the Ge crystal layer 2106. Fig. 39 shows the cross-sectional shape of the Ge crystal layer 2106 which has been annealed at 800 ° C. © Fig. 40 shows the Ge crystal layer 2106 which has been annealed at 850 ° C Fig. 41 shows the cross-sectional shape of the Ge crystal layer 2106 which has been annealed at 900 ° C. Fig. 42 shows the average value of the film thickness of the compound semiconductor 2108 in Example 9. Fig. 43 shows The coefficient of variation of the film thickness of the compound semiconductor 2108 in Example 9. The figure 44 shows the average value of the film thickness of the compound semiconductor 2108 in Example 10 of 99321546 201019376. Fig. 45 shows the compound semiconductor of Example 10 Electron microscope image of 8. Fig. 46 shows an electron microscope image of the compound semiconductor 21〇8 in Example 1. Fig. 47 shows an electron microscope image of the compound semiconductor 21〇8 in Example 10. Fig. 48 shows an implementation An electron microscope image of the compound semiconductor 2108 in Example 1 is shown. Fig. 49 shows an electron microscope image of the compound semiconductor 21〇8 in Example 10. Fig. 50 shows the example 11 Electron microscope image of compound semiconductor 2108. Fig. 51 shows an electron microscope image of compound semiconductor 2108 in Example 11. Fig. 52 shows an electron microscope image of compound semiconductor 2108 in Example 11. Fig. 53 shows Example 11 Electron microscope image of compound semiconductor 2108. Fig. 54 shows an electron microscope image of compound semiconductor 2108 of Example 11. Fig. 55 shows an electron microscope image of the compound semiconductor 2108 in Example 12. Fig. 56 shows an electron 321546 100 of the compound semiconductor 21〇8 in Example 12, which is called an image. The 57th ray 7 diagram shows the electronic 58th fa image of the compound semiconductor fiber in Example 12. - Electron microscope showing the semiconductor wafer in Example 13 The 59th Temple The laser microscope image of the HBT element in Example 14 was not shown. ® » 61 The laser microscope image of the electronic component of Example 15 is shown. Relationship. The electrical characteristics of the HBT element and the area of the opening region are shown. 62. Scanning electron microscope image showing the cross section of the crystal. The display of the display of the display is based on the purpose of making the image of Fig. 62 easier to see.苐64阑一第65 _ shows a scanning electron microscope image of the crystal cross section. The 摹7 display shown by the 1st member is based on the purpose of making the image of Fig. 64 easier to see. ^ 66 jg, _ _ 67 shows the side profile of the Si element for sample A. The first side shows the side profile of the sample AiGe element. Fig. 8 shows the side profile of the Si element of sample B. Figure 69 shows the side profile of the Ge element of sample B. Figure 70 shows a schematic diagram based on the purpose of making Figures 66 to 69 easier to see. Figure 71 shows an SEM image showing the measurement area for sample A. Figure 72 shows the Si of the measurement area shown in Figure 71 and 101 321546 201019376

Ge的元素強度積分值。 第73圖顯示一 SEM影像，其中顯示關於試料B之量測 區域。 第74圖顯示關於第73圖中所示的量測區域之Si及 Ge的元素強度積分值。 第75圖顯示在實施例2中作成的半導體裝置用晶圓 3000的平面圖案。 第76圖係顯示裝置用薄膜3004的成長速度與阻礙層 3002的寬度的關係之曲線圖。 第77圖係顯示裝置用薄膜3004的成長速度與面積比 的關係之曲線圖。 第78圖係顯示裝置用薄膜3004的成長速度與阻礙層 3002的寬度的關係之曲線圖。 · 第79圖係顯示裝置用薄膜3004的成長速度與面積比 的關係之曲線圖。 第80圖係顯示裝置用薄膜3004的成長速度與阻礙層 3002的寬度的關係之曲線圖。 θ 第81圖係顯示裝置用薄膜3004的成長速度與面積比 的關係之曲線圖。 第82圖係顯示觀察使基底晶圓的傾斜角為2。時之半 導體裝置用晶圓3000的表面所見之電子顯微鏡影像。 第83圖係顯示觀察使基底晶圓的傾斜角為2。時之半 導體裝置用晶圓3000的表面所見之電子顯微鏡影像。 第84圖係顯示觀察使基底晶圓的傾斜角為6。時之半 321546 102 201019376 &quot; 導體裝置用晶圓3000的表面所見之電子顯微鏡影像。 • 第85圖係顯示觀察使基底晶圓的傾斜角為6°時之半 導體裝置用晶圓3000的表面所見之電子顯微鏡影像。 第86圖係顯示異質接面雙極性電晶體（HBT)3100之平 面圖。 第87圖係顯示第20圖中以虛線圍起的部份之顯微鏡 影像。 第88圖係擴大顯示第21圖中以虛線圍起的三個HBT 〇 元件3150的部份之平面圖。 第89圖係顯示觀察HBT元件3150的區域所見之雷射 顯微鏡影像。 第90圖係顯示HBT 3100的製造工序的順序之平面圖。 第91圖係顯示HBT 3100的製造工·序的順序之平面圖。 第92圖係顯示HBT 3100的製造工序的順序之平面圖。 第93圖係顯示HBT 3100的製造工序的順序之平面圖。 第94圖係顯示HBT 3100的製造工序的順序之平面圖。 第95圖係顯示對於製造出來的HBT 3100的各種特性 進行量測所得到的數據之曲線圖。 第96圖係顯示對於製造出來的HBT 3100的各種特性 進行量測所得到的數據之曲線圖。 第97圖係顯示對於製造出來的HBT 3100的各種特性 進行量測所得到的數據之曲線圖。 第98圖係顯示對於製造出來的HBT 3100的各種特性 進行量測所得到的數據之曲線圖。 103 321546 201019376 第99圖係顯示對於製造出來的Ηβτ 31〇〇的各 進行量測所得到的數據之曲線圖。 锊性 進行深度輪廓的量 第100圖係以二次離子質量分析法 測所得到的數據。 同時形成的HBT斷面之 第101圖係顯示與HBT 3100 TEM影像。 膜之HBT。 第102圖顯示在沒有阻礙層的整個晶圓形成裝置用》 【元件符號說明】 10 半導體晶圓 12 基底晶圓 14 Si結晶層 18 化合物半導體 20 半導體晶圓 26 種子結晶 28 化合物半導體 34 Si結晶層 38 化合物半導體 41 面 44 Si結晶層 46 種子結晶 100 電子裝置 104 阻礙層 106 Ge結晶層 11 主面 13 絕緣層 16 種子結晶 19 表面 25 阻礙層 27 開口 30 半導體晶圓 36 種子結晶 40 半導體晶圓 43 上表面 45 阻礙層 48 化合物半導體 102 SO I晶圓 105 開口The elemental intensity integral value of Ge. Figure 73 shows an SEM image showing the measurement area for sample B. Fig. 74 shows the element intensity integral values of Si and Ge regarding the measurement area shown in Fig. 73. Fig. 75 shows a planar pattern of the wafer 3000 for a semiconductor device fabricated in the second embodiment. Fig. 76 is a graph showing the relationship between the growth rate of the film 3004 for the device and the width of the barrier layer 3002. Fig. 77 is a graph showing the relationship between the growth rate of the film 3004 for a device and the area ratio. Fig. 78 is a graph showing the relationship between the growth rate of the film 3004 for the device and the width of the barrier layer 3002. Fig. 79 is a graph showing the relationship between the growth rate of the film 3004 for the device and the area ratio. Fig. 80 is a graph showing the relationship between the growth rate of the film 3004 for the device and the width of the barrier layer 3002. θ Fig. 81 is a graph showing the relationship between the growth rate of the film 3004 for the device and the area ratio. Figure 82 shows the observation that the tilt angle of the base wafer is 2. The electron microscope image seen on the surface of the wafer 3000 for the conductor device. Fig. 83 shows the observation that the tilt angle of the base wafer is 2. The electron microscope image seen on the surface of the wafer 3000 for the conductor device. Fig. 84 shows the observation that the tilt angle of the base wafer is 6. Half of the time 321546 102 201019376 &quot; Electron microscope image seen on the surface of wafer 3000 for conductor devices. • Fig. 85 shows an electron microscope image seen on the surface of the semiconductor device wafer 3000 when the inclination angle of the base wafer is 6°. Figure 86 is a plan view showing a heterojunction bipolar transistor (HBT) 3100. Fig. 87 is a view showing a microscope image of a portion enclosed by a broken line in Fig. 20. Fig. 88 is a plan view showing an enlarged view of a portion of three HBT 元件 elements 3150 enclosed by a broken line in Fig. 21. Fig. 89 shows a laser microscope image seen in the area where the HBT element 3150 is observed. Fig. 90 is a plan view showing the sequence of the manufacturing process of the HBT 3100. Fig. 91 is a plan view showing the sequence of the manufacturing order of the HBT 3100. Fig. 92 is a plan view showing the sequence of the manufacturing process of the HBT 3100. Fig. 93 is a plan view showing the sequence of the manufacturing process of the HBT 3100. Fig. 94 is a plan view showing the sequence of the manufacturing process of the HBT 3100. Fig. 95 is a graph showing data obtained by measuring various characteristics of the manufactured HBT 3100. Fig. 96 is a graph showing data obtained by measuring various characteristics of the manufactured HBT 3100. Fig. 97 is a graph showing data obtained by measuring various characteristics of the manufactured HBT 3100. Fig. 98 is a graph showing data obtained by measuring various characteristics of the manufactured HBT 3100. 103 321546 201019376 Fig. 99 is a graph showing the data obtained by measuring each of the manufactured Ηβτ 31〇〇.锊 The amount of depth profile is taken. Figure 100 shows the data obtained by secondary ion mass spectrometry. The 101st image of the HBT section formed at the same time shows the TEM image with the HBT 3100. HBT of the membrane. Figure 102 shows the entire wafer forming apparatus without a barrier layer. [Explanation of Symbols] 10 Semiconductor Wafer 12 Substrate Wafer 14 Si Crystal Layer 18 Compound Semiconductor 20 Semiconductor Wafer 26 Seed Crystal 28 Compound Semiconductor 34 Si Crystal Layer 38 Compound semiconductor 41 face 44 Si crystal layer 46 seed crystal 100 electronic device 104 barrier layer 106 Ge crystal layer 11 main surface 13 insulating layer 16 seed crystal 19 surface 25 barrier layer 27 opening 30 semiconductor wafer 36 seed crystal 40 semiconductor wafer 43 Upper surface 45 barrier layer 48 compound semiconductor 102 SO I wafer 105 opening

321546 104 201019376 108 種子化合物半導體結晶 &quot; 110 第一化合物半導體結晶 112 第二化合物半導體結晶 114 閘極絕緣膜 116 閘極電極 118 源極/没極電極 120 缺陷捕捉部 130 缺陷捕捉部 162 Si晶圓 164 絕緣層 166 Si結晶層 172 主面 200 電子裝置 ❿ 300 電子裝置 400 電子裝置 402 緩衝層 500 電子裝置 502 源極/汲極電極 600 電子裝置 602 源極/汲極電極 700 電子裝置 702 下部閘極絕緣膜 704 下部閘極電極 801 半導體晶圓 802 SOI晶圓 803 區域 804 阻礙層 G 806 開口 808 集極電極 810 射極電極 812 基極電極 820 Ge.結晶層 822 緩衝層 824 化合物半導體功能層 862 Si晶圓 864 絕緣層 866 Si結晶層 872 主面 880 MISFET 882 阱 888 閘極電極 1101 半導體晶圓 1102 SOI晶圓 1108 集極電極 1110 射極電極 105 321546 201019376 1112 基極電極 1120 Ge結晶層 1122 InGaP 層 1123 InGaP 層 1124 化合物半導體功能層 1125 附隨層 1130 Ge膜 1162 Si晶圓 1164 絕緣層 1166 Si結晶層 1172 主面 1201 半導體晶圓 1202 種子結晶層 1204 GaAs 層 1301 半導體晶圓 2102 Si晶圓 2104 阻礙層 2106 Ge結晶層 2108 化合物半導體 2202 S i晶圓 2204 Si〇2 膜 2206 Ge結晶 2208 GaAs結晶 3000 半導體裝置用晶圓 3002 阻礙層 3004 裝置用薄膜 3006 犧牲成長部 3100 HBT 3102 阻礙層 3108 裝置用薄膜 3110 犧牲成長部 3112 射極電極 3114 基極電極 3116 集極電極 3118 場絕緣膜 3120 配線 3122 配線 3124 集極配線 3126 射極配線 3128 基極配線 3130 集極焊墊 3132 射極焊墊 3134 基極焊墊 3150 HBT元件 3202 範圍 3204 範圍 3206 範圍 3208 /rfr ret 摩巳圍321546 104 201019376 108 Seed Compound Semiconductor Crystallization &quot; 110 First Compound Semiconductor Crystal 112 Second Compound Semiconductor Crystal 114 Gate Insulation Film 116 Gate Electrode 118 Source/Pole Electrode 120 Defect Capture Port 130 Defect Capture Port 162 Si Wafer 164 Insulation 166 Si Crystal Layer 172 Main Surface 200 Electronics ❿ 300 Electronics 400 Electronics 402 Buffer Layer 500 Electronics 502 Source / Gate Electrode 600 Electronics 602 Source / Gate Electrode 700 Electronics 702 Lower Gate Insulating film 704 lower gate electrode 801 semiconductor wafer 802 SOI wafer 803 region 804 barrier layer G 806 opening 808 collector electrode 810 emitter electrode 812 base electrode 820 Ge. crystal layer 822 buffer layer 824 compound semiconductor functional layer 862 Si Wafer 864 insulating layer 866 Si crystal layer 872 main surface 880 MISFET 882 well 888 gate electrode 1101 semiconductor wafer 1102 SOI wafer 1108 collector electrode 1110 emitter electrode 105 321546 201019376 1112 base electrode 1120 Ge crystal layer 1122 InGaP layer 1123 InGaP layer 1124 combination Semiconductor functional layer 1125 accompanying layer 1130 Ge film 1162 Si wafer 1164 insulating layer 1166 Si crystal layer 1172 main surface 1201 semiconductor wafer 1202 seed crystal layer 1204 GaAs layer 1301 semiconductor wafer 2102 Si wafer 2104 barrier layer 2106 Ge crystal layer 2108 Compound semiconductor 2202 S i wafer 2204 Si〇2 film 2206 Ge crystal 2208 GaAs crystal 3000 Semiconductor device wafer 3002 Barrier layer 3004 Device film 3006 Sacrificial growth portion 3100 HBT 3102 Barrier layer 3108 Device film 3110 Sacrificial growth portion 3112 Emitter electrode 3114 Base electrode 3116 Collector electrode 3118 Field insulating film 3120 Wiring 3122 Wiring 3124 Collector wiring 3126 Emitter wiring 3128 Base wiring 3130 Collective pad 3132 Electrode pad 3134 Base pad 3150 HBT component 3202 Range 3204 Range 3206 Range 3208 /rfr ret Capricorn

106 321546 201019376 3210 範圍 3212 範圍 3220 矽 3224 緩衝層 3226 次集極層 3230 基極層 3232 射極層 3234 集極電極 3236 基極電極 3238 射極電極 107 321546106 321546 201019376 3210 Range 3212 Range 3220 矽 3224 Buffer Layer 3226 Secondary Collector Layer 3230 Base Layer 3232 Emitter Layer 3234 Collector Electrode 3236 Base Electrode 3238 Emitter Electrode 107 321546

Claims (1)

201019376 七、申請專利範圍： I —種半導體晶圓，以基底晶圓、絕緣層、Si結晶層這 樣的順序具有該基底晶圓、絕緣層及S i結晶層，且具 備有： 設於前述Si結晶層上並經過退火處理之種子矣士 晶；以及 與則述種子結晶晶格匹配或準晶格匹配之化合物 半導體。 σ 2·如申請專利範圍第1項之半導體晶圓，其中， 還具備有阻礙前述化合物半導體的結晶成長之阻 礙層， 前述阻礙層具有貫通至前述Si結晶層之開口， 前述種子結晶係設於前述開口的内部。 3.如申請專利範圍第2項之半導體晶圓，其中， 前述阻礙層係形成於前述Si結晶層上。 4·如申請專利範圍第2項之半導體晶圓，θ其中， 前述化合物半導體之包含於前述開口内的部份且 有不到/2之深寬比。 ” 5.如申請專利範圍第2項之半導體晶圓，其中， 前述化合物半導體具有： 在則述種子結晶上，結晶成長到比前述阻礙層 面凸出之種子化合物半導體結晶；以及 、表 以前述種子化合物半導體結晶為核而沿 礙層橫向成長之横向成長化合財導體結一钱 321546 108 201019376 6·如申請專利範圍第5項之半導體晶圓，其中， 前述橫向成長化合物半導體結晶具有： 以前述種子化合物半導體結晶為核而沿著前述阻 礙層橫向成長之第一化合物半導體結晶；以及 以前述第一化合物半導體結晶為核而沿著前述阻 礙層朝向與前述第一化合物半導體結晶不同的方向橫 向成長之第二化合物半導體結晶。 ⑩7·如申請專利範圍第1項之半導體晶圓，其中， 、别述Sl結晶層、前述種子結晶、及前述化合物半 導體係大致平行地形成於前述基底晶圓。 8. 如申請專利範圍第7項之半導體晶圓，其中， 還具備有覆蓋住前述Si結晶層的上表面，阻礙前 述化合物半導體的結晶成長之阻礙層。 . 9. 如申請專利範圍第2項之半導體晶圓，其中， 藉由使4述Si結晶層之設有前述種子結晶之區域 © 以外的區域熱氧化而形成前述阻礙層。 10·如申請專利範圍第1項之半導體晶圓，其中， 複數個前述種子結晶等間隔設置於前述Si結晶層 上。 u.如申請專利範圍第丨項之半導體晶圓，其中， 月’J述種子結晶為不會因為在前述退火處理中產生 的熱應力而發生缺陷之大小。 2.如申请專利範圍第1項之半導體晶11，其中， 還具備有捕捉前述種子結晶的内部產生的缺陷之 109 321546 201019376 缺陷捕捉部， 前述種子結晶所包含的任意的點到前述缺陷捕捉 部的最大輯，比在前述退火處理中前述缺陷 距離小。 13·如申請專利範圍第12項之半導體晶圓，其中 前述缺陷捕捉部，係為前述種子結晶的界面或表 面，且為並不與前述基底晶圓大致平行的方向之面。 14.如申請專利範圍第丨項之半導體晶圓，其中， 前述種子結晶，係結晶成長成的SixGeix(〇$x&lt;i) 結晶或在500t以下之溫度結晶成長成的GaAs。 b·如申請專利範圍第丨項之半導體晶圓，其中， 則述種子結晶之與前述化合物半導體的界面，接受 以氣體之磷化合物進行之表面處理。 又 M·如申請專利範圍第丨項之半導體晶圓，其中， 洳述化合物半導體為IΗ 族化合物半導體或 1卜VI族化合物半導體。 17·如申請專利範圍第16項之半導體晶圓，其中， ，則述化合物半導體為III-V族化合物半導體，且作 為ΠΙ無TL素者包含A1、Ga、In中之至少一者，作為 V族7L素者包含况、|&gt;、As、Sb中之至少一者。 8·如申凊專利範圍第1項之半導體晶圓，其中， 前述化合物半導體包含由含磷之ΙΠ_ν 半導體所構成之緩衝層， 化°物 月’J述緩衝層係與前述種子結晶晶格匹配或準晶格 321546 110 201019376 匹配。 19·如申請專利範㈣丨項之半導體晶圓，其中， 前述種子結晶的表面的差排密度在lxl〇6/cm2以 下。 20.如申請專利範圍第！項之半導體晶圓，其中， 還具備有設於前述Si結晶層之未為前述種子結晶 所覆蓋的部份之Si半導體裝置。 ❹21·如申請專利範圍第1項之半導體晶圓，其中， 4述基底晶圓為單結晶Μ， 該半導體晶圓還具備有設於前述基底晶圓之未為 别述種子結晶所覆蓋的部份之Si半導體裝置。 22.如申請專利範圍第1項之半導體晶圓，其中， 刖述Si結晶層之形成前述種子結晶的面，係具有 f對於從（100)面、⑴〇)面、（1⑴面、與⑽）面在結 晶學上等效的面、與（11〇)面在結晶學上等效的面、及 ❹與（111)面在結晶學上等效的面之中選出的任—個結晶 面傾斜一個角度之傾斜角。 23·如申請專利範圍第22項之半導體晶圓，其中 前述傾斜角在2。以上6。以下。 24. 如申請專利範圍第1項之半導體晶圓，其中 前述種子結晶的底面積在1mm2以下。 25. 如申請專利範圍第24項之半導體晶圓，其中 如述底面積在16 0 0 /z m2以下。 26. 如申請專利範圍第託項之半導體晶圓，其中 201019376 别述底面積在900 # m2以下。 27. 如申請專利範圍第1項之半導體晶圓，其中 前述種子結晶的底面的最大寬度在8〇//m以下。 28. 如申請專利範圍第27項之半導體晶圓，其中 刖述種子結晶的底面的最大寬度在# m以下。 29. 如申請專利範圍第i項之半導體晶圓，其中 則述基底晶圓具有：擁有相對於（1〇〇)面或與（1〇〇) 面在結晶學上等效的面傾斜一個角度的傾斜角之主面， 前述種子結晶的底面為長方形， 則述長方形的一邊係與前述基底晶圓的〈〇1〇&gt;方 向、&lt;0-10&gt;方向、&lt;001&gt;方向、及&lt;〇〇1&gt;方向之任一者 實質地平行。 30. 如申請專利範圍第29項之半導體晶圓，其中 前述傾斜角在2。以上6。以下。 31. 如申凊專利範圍第丨項之半導體晶圓，其中 前述基底晶圓具有：擁有相對於（111)面或與（111) 面在^晶學上等效的面傾斜—個角度的傾斜角之主面， 刖述種子結晶的底面為六角形， 前述六角形的一邊係與前述基底晶圓的&lt;H0&gt;方 向、110&gt;方向、&lt;(M1&gt;方向、&lt;01-1&gt;方向、〈㈣〉 方向、及&lt;-101&gt;方向之任一者實質地平行。 扣.如申請專利範圍第，31項之半導體晶圓，其中 前述傾斜角在2。以上6。以下。 、 33·如申請專利範圍第2項之半導體晶圓，其中 321546 112 201019376 前述阻礙層的外形的最大寬度在4250 /zm以下。 34. 如申請專利範圍第33項之半導體晶圓，其中 前述阻礙層的外形的最大寬度在400 /z m以下。 35. —種電子裝置，具備有： 基體； 設於前述基體上之絕緣層； 設於前述絕緣層上之Si結晶層； 設於前述Si結晶層上並經過退火處理之種子結 晶， 與前述種子結晶晶格匹配或準晶格匹配之化合物 半導體；以及 使用前述化合物半導體而形成之半導體裝置。 36. 如申請專利範圍第35項之電子裝置，其中 還具備有阻礙前述化合物半導體的結晶成長之阻 礙層， 前述阻礙層具有貫通至前述Si結晶層之開口， 前述種子結晶係設於前述開口的内部， 前述化合物半導體具有：在前述種子結晶上結晶成 長到比前述阻礙層的表面凸出之種子化合物半導體結 晶；以及以前述種子化合物半導體結晶為核而沿著前述 阻礙層橫向成長之橫向成長化合物半導體結晶。 37. —種半導體晶圓之製造方法，包含有： 準備以基底晶圓、絕緣層、Si結晶層這樣的順序 具有該基底晶圓、絕緣層及Si結晶層之SOI晶圓的階 113 321546 201019376 段； * 使種子結晶在前述Si結晶層上成長的階段； · 對前述種子結晶進行退火處理的階段；以及 使與前述種子結晶晶格匹配或準晶格匹配之化合 物半導體結晶成長的階段。 38. 如申請專利範圍第37項之半導體晶圓之製造方法，其 中， 使前述種子結晶成長的階段包含： 在前述Si結晶層上設置阻礙前述化合物半導體的 ® 結晶成長之阻礙層的階段； 在前述阻礙層形成貫通至前述Si結晶層之開口的 階段；以及 使前述種子結晶在前述開口的内部成長的階段。 39. 如申請專利範圍第37項之半導體晶圓之製造方法，其 中，還包含有： 在使前述化合物半導體結晶成長的階段之前進 Ο 行，藉由使前述Si結晶層之設有前述種子結晶之區域 以外的區域熱氧化，而設置阻礙前述化合物半導體的結 晶成長之阻礙層的階段。 40. 如申請專利範圍第37項之半導體晶圓之製造方法，其 中， 前述進行退火處理的階段，係以可使前述種子結晶 中所含的缺陷移動到前述種子結晶的外緣之溫度及時 間進行。 114 321546 201019376 — 41.如申請專利範圍第37項之半導體晶圓之製造方法，其 中，還包含有： 使前述進行退火處理的階段重複進行複數次的階 段。 42.如申請專利範圍第37項之半導體晶圓之製造方法，其 中， 使前述種子結晶成長的階段，係使複數個前述種子 結晶等間隔成長。 © 43.如申請專利範圍第37項之半導體晶圓之製造方法，其 中， 使前述種子結晶成長的階段，係使前述種子結晶成 長到不會因為前述退火處理所產生的熱應力而使得前 述種子結晶發生缺陷之大小。 44.如申請專利範圍第38項之半導體晶圓之製造方法，其 中-， _ 前述進行退火處理的階段，使前述種子結晶的表面 的差排密度在lxlOVcm2以下。 115 321546201019376 VII. Patent application scope: I. A semiconductor wafer having the base wafer, the insulating layer, and the Si crystal layer in the order of the base wafer, the insulating layer, and the Si crystal layer, and having: a seeded sapphire crystal which is annealed on the crystal layer; and a compound semiconductor which is lattice-matched or quasi-lattice-matched to the seed crystal. The semiconductor wafer according to the first aspect of the invention, further comprising a barrier layer that inhibits crystal growth of the compound semiconductor, wherein the barrier layer has an opening penetrating through the Si crystal layer, and the seed crystal is provided in The inside of the aforementioned opening. 3. The semiconductor wafer according to claim 2, wherein the barrier layer is formed on the Si crystal layer. 4. The semiconductor wafer of claim 2, wherein the compound semiconductor is included in the opening and has an aspect ratio of less than /2. 5. The semiconductor wafer according to claim 2, wherein the compound semiconductor has: a seed compound semiconductor crystal which grows on the seed crystal to be larger than the barrier layer; and The compound semiconductor crystal is a nucleus and the lateral growth of the barrier layer is laterally grown. The semiconductor wafer is 321 546. The semiconductor wafer of claim 5, wherein the lateral growth compound semiconductor crystal has: a first compound semiconductor crystal in which a compound semiconductor crystal is a core and laterally grown along the barrier layer; and a lateral growth of the first compound semiconductor crystal as a core and a direction different from the first compound semiconductor crystal along the barrier layer The semiconductor wafer according to the first aspect of the invention, wherein the S1 crystal layer, the seed crystal, and the compound semiconductor are formed substantially in parallel with the base wafer. For example, the scope of patent application is 7 The semiconductor wafer further includes a barrier layer covering the upper surface of the Si crystal layer and hindering crystal growth of the compound semiconductor. 9. The semiconductor wafer according to claim 2, wherein The semiconductor wafer of the first aspect of the present invention is obtained by thermally oxidizing a region other than the region of the Si crystal layer in which the seed crystal is formed. The semiconductor wafer of the first aspect of the invention, wherein the plurality of seed crystals are equally spaced. The semiconductor wafer of the above-mentioned Si crystal layer, wherein the semiconductor wafer is crystallized so that the size of the defect does not occur due to thermal stress generated in the annealing treatment. The semiconductor crystal 11 according to the first aspect of the invention, further comprising: 109321546 201019376 defect capturing portion for capturing a defect occurring inside the seed crystal, wherein an arbitrary point included in the seed crystal reaches a maximum of the defect capturing portion In addition, the aforementioned defect distance is smaller than in the foregoing annealing process. 13· The semiconductor wafer of claim 12, The defect trapping portion is an interface or a surface of the seed crystal, and is a surface that is not substantially parallel to the base wafer. 14. The semiconductor wafer according to claim </ RTI> wherein the seed is Crystallization is a crystallization of SixGeix (〇$x&lt;i) crystal grown or crystallized at a temperature of 500t or less. b. A semiconductor wafer according to the scope of the patent application, wherein the seed crystal is The interface of the compound semiconductor is subjected to a surface treatment by a phosphorus compound of a gas. M. The semiconductor wafer according to the scope of the patent application, wherein the compound semiconductor is a group I compound semiconductor or a group VI compound semiconductor. . 17. The semiconductor wafer of claim 16, wherein the compound semiconductor is a III-V compound semiconductor, and the TL-free element includes at least one of A1, Ga, and In, as V The family 7L element includes at least one of the condition, |&gt;, As, and Sb. 8. The semiconductor wafer according to claim 1, wherein the compound semiconductor comprises a buffer layer composed of a phosphorus-containing germanium _ν semiconductor, and the buffer layer is matched with the seed crystal lattice. Or pseudo-lattice 321546 110 201019376 matches. 19. The semiconductor wafer according to claim 4, wherein the surface of the seed crystal has a difference in density of lxl 〇 6 / cm 2 or less. 20. If you apply for a patent scope! The semiconductor wafer of the present invention further includes a Si semiconductor device provided in the Si crystal layer which is not covered by the seed crystal. The semiconductor wafer of claim 1, wherein the base wafer is a single crystal germanium, and the semiconductor wafer further includes a portion of the base wafer that is not covered by seed crystals Si semiconductor device. 22. The semiconductor wafer according to claim 1, wherein the surface of the Si crystal layer forming the seed crystal has f for a (100) plane, (1) 〇 plane, (1 (1) plane, and (10) a crystallographically equivalent surface, a crystallographically equivalent surface of the (11 Å) plane, and any crystallographic plane selected from the crystallographically equivalent planes of the (111) plane Tilt the angle of inclination of an angle. 23. The semiconductor wafer of claim 22, wherein the aforementioned tilt angle is two. Above 6. the following. 24. The semiconductor wafer of claim 1, wherein the seed crystal has a bottom area of less than 1 mm2. 25. The semiconductor wafer of claim 24, wherein the bottom area is below 1600/z m2. 26. For example, the semiconductor wafers in the scope of the patent application, in which 201019376, the bottom area is below 900 # m2. 27. The semiconductor wafer of claim 1, wherein the bottom surface of the seed crystal has a maximum width of 8 Å/m or less. 28. The semiconductor wafer of claim 27, wherein the maximum width of the bottom surface of the seed crystal is below #m. 29. The semiconductor wafer of claim i, wherein the substrate wafer has an angle that is inclined at a crystallographically equivalent plane with respect to (1 〇〇) plane or (1 〇〇) plane The main surface of the inclined angle, the bottom surface of the seed crystal is a rectangle, and the side of the rectangle is the <〇1〇> direction, the &lt;0-10&gt; direction, the &lt;001&gt; direction, and the base wafer. Any of the &lt;〇〇1&gt; directions is substantially parallel. 30. The semiconductor wafer of claim 29, wherein the aforementioned tilt angle is 2. Above 6. the following. 31. The semiconductor wafer of claim </ RTI> wherein the base wafer has a tilt that is crystallographically equivalent to the (111) plane or the (111) plane. The main surface of the corner is a hexagonal shape on the bottom surface of the seed crystal, and the side of the hexagonal shape is the &lt;H0&gt; direction, 110&gt; direction, &lt;(M1&gt; direction, &lt;01-1&gt; The direction, the <(4)> direction, and the &lt;-101&gt; direction are substantially parallel. The semiconductor wafer according to claim 31, wherein the tilt angle is 2 or more and 6. or less. 33. The semiconductor wafer of claim 2, wherein 321546 112 201019376 has a maximum width of the outer shape of the barrier layer of 4250 /zm or less. 34. The semiconductor wafer of claim 33, wherein the barrier layer The maximum width of the shape is less than 400 /zm. 35. An electronic device comprising: a substrate; an insulating layer disposed on the substrate; a Si crystal layer disposed on the insulating layer; disposed on the Si crystal layer Annealed a seed crystal, a compound semiconductor lattice-matched or quasi-lattice-matched with the seed crystal; and a semiconductor device formed using the compound semiconductor. 36. The electronic device of claim 35, further comprising a barrier layer for crystal growth of a compound semiconductor, wherein the barrier layer has an opening penetrating into the Si crystal layer, and the seed crystal is provided inside the opening, and the compound semiconductor has crystal growth on the seed crystal to be larger than the barrier layer a seed compound semiconductor crystal having a surface protruding; and a laterally growing compound semiconductor crystal which grows laterally along the barrier layer by using the seed compound semiconductor crystal as a core. 37. A method for manufacturing a semiconductor wafer, comprising: preparing The order of the base wafer, the insulating layer, and the Si crystal layer has the step 113 321546 201019376 of the SOI wafer of the base wafer, the insulating layer, and the Si crystal layer; * the stage of crystallizing the seed on the Si crystal layer; · Performing the aforementioned seed crystallization a stage of annealing treatment; and a stage of crystal growth of a compound semiconductor which is lattice-matched or quasi-lattice-matched with the seed crystal. 38. The method of manufacturing a semiconductor wafer according to claim 37, wherein the seed crystal is crystallized The stage of growth includes: a step of providing a barrier layer for inhibiting the crystal growth of the compound semiconductor on the Si crystal layer; a step of forming the barrier layer to penetrate the opening of the Si crystal layer; and crystallizing the seed in the opening The stage of internal growth. 39. The method of manufacturing a semiconductor wafer according to claim 37, further comprising: performing a step of crystallization of said Si crystal layer before said crystal growth of said compound semiconductor The region other than the region is thermally oxidized, and a step of blocking the barrier layer of crystal growth of the compound semiconductor is provided. 40. The method of manufacturing a semiconductor wafer according to claim 37, wherein the annealing step is performed at a temperature and time at which an edge contained in the seed crystal is moved to an outer edge of the seed crystal. get on. The method of manufacturing a semiconductor wafer according to claim 37, further comprising: repeating the step of performing the annealing treatment a plurality of times. The method of producing a semiconductor wafer according to the 37th aspect of the invention, wherein the seed crystal is grown at a stage in which a plurality of the seed crystals are grown at equal intervals. The method for producing a semiconductor wafer according to claim 37, wherein the seed crystal is grown in a stage in which the seed crystal is grown to not cause the aforementioned seed due to thermal stress generated by the annealing treatment. The size of defects in crystallization. 44. The method for producing a semiconductor wafer according to claim 38, wherein the step of performing the annealing treatment is such that the surface of the seed crystal has a difference in density of lxl OVcm2 or less. 115 321546
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