JPH0425135A - Semiconductor substrate - Google Patents
Semiconductor substrateInfo
- Publication number
- JPH0425135A JPH0425135A JP12972390A JP12972390A JPH0425135A JP H0425135 A JPH0425135 A JP H0425135A JP 12972390 A JP12972390 A JP 12972390A JP 12972390 A JP12972390 A JP 12972390A JP H0425135 A JPH0425135 A JP H0425135A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- single crystal
- semiconductor
- thickness
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 239000000758 substrate Substances 0.000 title claims abstract description 47
- 239000013078 crystal Substances 0.000 claims abstract description 52
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 150000001875 compounds Chemical class 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 26
- 238000000034 method Methods 0.000 abstract description 8
- 230000006866 deterioration Effects 0.000 abstract description 6
- 239000010931 gold Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000012495 reaction gas Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 241000282320 Panthera leo Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 201000010099 disease Diseases 0.000 description 1
- 208000037265 diseases, disorders, signs and symptoms Diseases 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体基板、特に半導体素子を形成するヘテロエピタキ
シャル成長による単結晶半導体層を上面に有する半導体
基板の構造に関し、
ヘテロ接合部の格子定数や熱膨張係数の不整合により、
素子が形成される単結晶半導体層に転位やストレスが発
生するのを抑制するヘテロエピタキシ基板の構造を提供
し、ヘテロエピタキシャル成長による単結晶半導体層に
形成される半導体素子の性能劣化を防止することを目的
とし、支持基板上に絶縁層を介して積層されている厚さ
１５００Å以下の単結晶シリコン層上に、該単結晶シリ
コン層とヘテロ接合を形成する単結晶半導体層が形成さ
れた構成を有する。[Detailed Description of the Invention] [Summary] Regarding the structure of a semiconductor substrate, particularly a semiconductor substrate having a single crystal semiconductor layer formed by heteroepitaxial growth on the upper surface to form a semiconductor element, there is a mismatch in the lattice constant and coefficient of thermal expansion of a heterojunction. According to
It is an object of the present invention to provide a heteroepitaxial substrate structure that suppresses the generation of dislocations and stress in a single crystal semiconductor layer in which an element is formed, and to prevent performance deterioration of a semiconductor element formed in a single crystal semiconductor layer due to heteroepitaxial growth. It has a structure in which a single crystal semiconductor layer forming a heterojunction with the single crystal silicon layer is formed on a single crystal silicon layer with a thickness of 1500 Å or less that is laminated on a support substrate via an insulating layer. .
本発明は半導体基板、特に素子を形成するヘテロエピタ
キシャル成長による半導体層を上面に有する半導体基板
の構造に関する。The present invention relates to a semiconductor substrate, and more particularly to the structure of a semiconductor substrate having a heteroepitaxially grown semiconductor layer on its upper surface forming a device.
近年、化合物半導体装置等においては、基板の大口径化
を図って製造原価を低減することを主たる目的として、
シリコン（Ｓｉ）基板上にヘテロエピタキシャル成長に
より形成した単結晶化合物半導体層を用いて半導体装置
を形成する技術が提供されているが、上記単結晶化合物
半導体層の結晶品質が充分でなく、半導体装置の性能劣
化を生ずるので、」１記ヘテロエピタキシャル成長によ
る単結晶半導体層の結晶品質の改善が望まれている。In recent years, in compound semiconductor devices, etc., the main purpose is to reduce manufacturing costs by increasing the diameter of the substrate.
A technique has been provided for forming a semiconductor device using a single crystal compound semiconductor layer formed by heteroepitaxial growth on a silicon (Si) substrate, but the crystal quality of the single crystal compound semiconductor layer is insufficient, and the semiconductor device Therefore, it is desired to improve the crystal quality of the single crystal semiconductor layer by heteroepitaxial growth described in 1.
〔従来の技術に余囮バ゛＠決しようとＩる牌、急〕従来
の、例えばＳｉ基板上にヘテロエピタキシャル成長した
単結晶化合物半導体層を用いた半導体装置においては、
ヘテロ接合界面でのＳｉ基板と単結晶化合物半導体層と
の間の格子定数及び熱膨張係数の不整合により、この接
合界面からＳｉ基板に対して極端に薄い単結晶化合物半
導体層内に、高密度の転位が発生ずると共に大きな残留
スＩ・レスも形成され、その結果、この単結晶化合物半
導体層に形成される半導体素子に、接合リーク等による
性能劣化を多発していた。[I'm trying to make a decision due to the influence of conventional technology.] In conventional semiconductor devices using, for example, a single-crystal compound semiconductor layer grown heteroepitaxially on a Si substrate,
Due to the mismatch in lattice constant and thermal expansion coefficient between the Si substrate and the single crystal compound semiconductor layer at the heterojunction interface, high density Along with the occurrence of dislocations, large residual I/stresses were also formed, resulting in frequent performance deterioration due to junction leakage and the like in semiconductor elements formed in this single crystal compound semiconductor layer.
そのため従来は、上記単結晶化合物半導体層の内部に中
間層としてアニール層や歪み超格子層を設け、これらの
層にヘテロ接合面からの転位やス１−レスを吸収して、
素子が形成される単結晶化合物半導体層の表面部の結晶
性を高める方法が試みられているが、転位やス１ヘレス
の除去が充分でなく、素子性能の劣化を充分に防止する
ことはできなかった。Therefore, conventionally, an annealing layer or a strained superlattice layer is provided as an intermediate layer inside the single crystal compound semiconductor layer, and these layers absorb dislocations and stress from the heterojunction surface.
Attempts have been made to improve the crystallinity of the surface of the single-crystal compound semiconductor layer on which the device is formed, but the removal of dislocations and strands is not sufficient, and deterioration of device performance cannot be sufficiently prevented. There wasn't.
そこで本発明は、ヘテロ接合部の格子定数や熱膨張係数
の不整合により、素子が形成される単結晶半導体層に転
位やストレスが発生するのを抑制するヘテロエピタキシ
基板の構造を提供し、ヘテロエピタキシャル成長による
単結晶半導体層に形成される半導体素子の性能低下を防
止することを目的とする。Therefore, the present invention provides a structure of a heteroepitaxy substrate that suppresses the occurrence of dislocations and stress in a single crystal semiconductor layer in which an element is formed due to mismatching of lattice constants and thermal expansion coefficients of a heterojunction. The purpose is to prevent deterioration in the performance of a semiconductor element formed in a single crystal semiconductor layer by epitaxial growth.
〔課題を解決するだめの手段］
上記課題は、支持基板上に絶縁層を介して積層されてい
る厚さ１５００Å以下の単結晶シリコン層上に、該単結
晶シリコン層とヘテロ接合を形成する単結晶半導体層が
形成された本発明による半導体基板によって解決される
。[Means to Solve the Problem] The above problem is achieved by forming a single crystal silicon layer, which forms a heterojunction with the single crystal silicon layer, on a single crystal silicon layer with a thickness of 1500 Å or less, which is laminated on a supporting substrate via an insulating layer. The problem is solved by a semiconductor substrate according to the invention on which a crystalline semiconductor layer is formed.
即ち、本発明においては半導体素子の形成されるヘテロ
エピタキシャル成長による単結晶半導体層の支持基板に
５ＯＴ（Ｓｉｌｉｃｏｎ Ｏｎ Ｔｎｓｕｌａｔｏｒ）
基板を用い、絶縁膜上に積層されている５ｊＮ（ＳＯＩ
Ｎ）上にヘテロエピタキシャル成長により素子が形成さ
れる単結晶半導体層を形成する。そして、第３図に示す
８０１層の膜厚と、その上にヘテロエピタキシャル成長
される通常の２〜３μｍ程度の厚さの単結晶半導体（Ｇ
ａＡｓ）層内に発生する転位の密度との関係から、８０
１層の厚さを５０〜１５００人程度に充分薄＜シ、単結
晶半導体層をそれに比べて充分に厚く形成することによ
り、ヘテロ接合部に生ずる結晶格子及び熱膨張係数の不
整合による応力を８０１層におけるＳｉ結晶の格子の変
形によって吸収し、上記応力が素子を形成する単結晶半
導体層に及ぼされる大きさを減少させて、この単結晶半
導体層内に発生する転位密度を少なくとも１０’／ｃｍ
２以下に減少させると同時に、これに伴ってストレスの
大きさをも減少せしめる。That is, in the present invention, a 5OT (Silicon On Tnsulator) is used as a support substrate for a single crystal semiconductor layer formed by heteroepitaxial growth on which a semiconductor element is formed.
Using a substrate, 5jN (SOI) is laminated on an insulating film.
N) A single crystal semiconductor layer on which elements will be formed is formed by heteroepitaxial growth. The film thickness of the 801 layer shown in Fig. 3 and the normal single crystal semiconductor (G
aAs) From the relationship with the density of dislocations occurring within the layer, 80
By making the single crystal semiconductor layer sufficiently thin (about 50 to 1,500 layers) and making the single crystal semiconductor layer sufficiently thick in comparison, stress caused by mismatching of the crystal lattice and thermal expansion coefficient that occurs at the heterojunction can be reduced. The stress is absorbed by the deformation of the Si crystal lattice in the 801 layer, reducing the magnitude of the stress exerted on the single crystal semiconductor layer forming the device, and reducing the dislocation density generated in the single crystal semiconductor layer to at least 10'/ cm
2 or less, and at the same time, the magnitude of stress is also reduced accordingly.
なお、第３図において、＾はＳｉ基板上にヘテロエピタ
キシャル成長させた厚さ３μｍのＧａＡｓ層の転位密度
を示し、Ｂは３０１層の厚さとその上にヘテロエピタキ
シャル成長された厚さ３μｍの単結晶ＧａＡｓ層内に発
生ずる転位の密度との関係のカーブである。In Fig. 3, ^ indicates the dislocation density of a 3 μm thick GaAs layer grown heteroepitaxially on a Si substrate, and B indicates the dislocation density of a 3 μm thick single crystal GaAs layer heteroepitaxially grown on the 301 layer. This is a curve showing the relationship between the density of dislocations generated within the layer.
以下本発明を、図示実施例により具体的に説明する。 The present invention will be specifically explained below with reference to illustrated embodiments.
第１図は本発明に係る半導体基板の一実施例の模式断面
図、第２図（ａ）乃至（Ｃ）は本発明に係る半導体基板
の形成方法の一実施例を示す工程断面図、第３図は５０
１層の膜厚と、ヘテロエピタキシャル成長ＧａＡｓ層の
転位密度との関係図、第４図は本発明に係る半導体基板
を用いて形成した半導体素子の一例の模式断面図である
。FIG. 1 is a schematic cross-sectional view of an embodiment of a semiconductor substrate according to the present invention, and FIGS. Figure 3 is 50
FIG. 4 is a diagram showing the relationship between the thickness of one layer and the dislocation density of a heteroepitaxially grown GaAs layer. FIG. 4 is a schematic cross-sectional view of an example of a semiconductor element formed using a semiconductor substrate according to the present invention.
全図を通じ同一対象物は同一符合で示す。Identical objects are indicated by the same reference numerals throughout the figures.
ＧａＡｓ半導体装置を形成する際に用いられる本発明に
係る半導体基板は、例えば、Ｓｔ支持基板１上に厚さ４
５００人程度０二酸化シリコン（ＳｉＯ□）絶縁層２を
介して積層された５０〜１５００人の範囲内の例えば１
０００人の厚さを有する単結晶Ｓｉ層（ＳＯＩ層）３上
に、厚さ１００人程鹿の非晶質ＧａＡｓ層４を介してヘ
テロエピタキシャル成長による厚さ２〜３μｍの単結晶
ＧａＡｓ層５が形成された構造を有する。The semiconductor substrate according to the present invention used when forming a GaAs semiconductor device is, for example, formed on a St support substrate 1 with a thickness of 4
For example, 1 in the range of 50 to 1,500 laminated with a silicon dioxide (SiO□) insulating layer 2
On a single crystal Si layer (SOI layer) 3 having a thickness of about 1,000 mm, a single crystal GaAs layer 5 with a thickness of 2 to 3 μm is formed by heteroepitaxial growth via an amorphous GaAs layer 4 of about 100 mm thick. Has a formed structure.
このような本発明に係るＧａＡｓ基板は、例えば以下に
説明する方法で形成される。Such a GaAs substrate according to the present invention is formed, for example, by the method described below.
第２図（ａ）参照
即ち、（１００）面を有し、（０１１）方向２°オフの
Ｓｉ単結晶基板１０１に酸素イオン（０゛）をドーズ量
２．０Ｘ１０１０ｃｍ−”、加速エネルギー１５０Ｋｅ
Ｖでイオン注入し、窒素中において１３００°Ｃで６時
間程度アニールし、弗酸等により表面の自然酸化膜を除
去しＳＯＩ基板１１を形成する。なおここで、前記Ｓｉ
単結晶基板１０１には、表面部に３０１層３となる厚さ
１０００人程度人程結晶Ｓｉ層１０１八を残してその下
部に厚さ４５００人程度０二ｉＯ□絶縁層２が形成され
る。Refer to FIG. 2(a). In other words, oxygen ions (0゛) are applied to a Si single crystal substrate 101 having a (100) plane and 2° off from the (011) direction at a dose of 2.0 x 1010 cm-" and an acceleration energy of 150 Ke.
Ions are implanted with V, annealed in nitrogen at 1300° C. for about 6 hours, and the natural oxide film on the surface is removed with hydrofluoric acid or the like to form the SOI substrate 11. Note that here, the Si
On the single-crystal substrate 101, a crystalline Si layer 1018 having a thickness of about 1,000 layers and forming a 301 layer 3 is left on the surface, and an insulating layer 2 of about 4,500 layers is formed below the crystalline Si layer 1018.
なおこのＳｉＯ□絶縁層２の下部に残留するＳｉ基板１
０１Ｂは支持基板１として機能する。Note that the Si substrate 1 remaining under this SiO□ insulating layer 2
01B functions as a support substrate 1.
第２図（ｂ）参照
次いで、このＳＯＩ基板１１をＭＯＣＶＤ （有機金属
気相成長）装置内に搬入し、例えば、
水素（Ｈ２） ： １２ ＳＬＭ とアルシン（八５
Ｈ３） ： ３０ ＳＣＣＭの混合ガスの７０〜８０Ｔ
ｏｒｒの減圧雰囲気中で、１０００°Ｃに約１０分間保
持して、単結晶Ｓｉ層１０１Ａ上の自然酸化膜を除去し
た後、
例えば、トリメチルガリウム（ＴＭＧ） ： ７０
ＳＣＣＭと八ｓ１１． ： ２００ ＳＣＣＭの混合ガ
スの７０Ｔｏｒｒ程度の減圧雰囲気中で４５０’Ｃ程度
に加熱し、単結晶Ｓｉ層１０１Ａ上に厚さ１００人程鹿
の非晶質ＧａＡｓ層４を形成し、次いで成長温度を通常
のＧａＡｓの成長温度である７００°Ｃに昇温し、成長
ガスの混合比を、ＴＭＧ：１４ＳＣＣＭ 、ＡＳｌ＋３
： １００３ＣＣＭとしてＧａＡｓのヘテロエピタキ
シャル成長を行い、前記非晶質ＧａＡｓ層４上に厚さ１
μｍ程度の第１の単結晶ＧａＡｓ層５Ａを形成し、次い
で同雰囲気中で、８００°Ｃと２００ ”Ｃとの間の昇
降温を５回程度繰り返す熱サイクルアニールを行い、上
記第１の単結晶ＧａＡｓ層島の表面部にアニル層５ａｎ
を形成する。Refer to FIG. 2(b) Next, this SOI substrate 11 is carried into an MOCVD (metal organic chemical vapor deposition) apparatus, and hydrogen (H2): 12 SLM and arsine (85
H3): 70-80T of mixed gas of 30 SCCM
After removing the natural oxide film on the single crystal Si layer 101A by holding it at 1000°C for about 10 minutes in a reduced pressure atmosphere of
SCCM and 8s11. : Heating to about 450'C in a reduced pressure atmosphere of about 70 Torr with a mixed gas of 200 SCCM to form an amorphous GaAs layer 4 about 100 mm thick on the single crystal Si layer 101A, and then lowering the growth temperature. The temperature was raised to 700°C, which is the normal growth temperature for GaAs, and the mixing ratio of the growth gas was changed to TMG: 14SCCM, ASl+3.
: GaAs is heteroepitaxially grown as 1003 CCM, and a thickness of 1 is formed on the amorphous GaAs layer 4.
A first single-crystal GaAs layer 5A with a thickness of approximately μm is formed, and then thermal cycle annealing is performed in the same atmosphere, increasing and decreasing the temperature between 800°C and 200''C approximately 5 times. An anil layer 5an is formed on the surface of the crystalline GaAs layer island.
form.
ここで、前記非晶質ＧａＡｓ層４は単結晶化され単結晶
ＧａＡｓ層論と一体化する。Here, the amorphous GaAs layer 4 is made into a single crystal and integrated with the single crystal GaAs layer.
第２図（Ｃ）参照
次いで」１記エピタキシャル成長と同一条件で、第１の
単結晶ＧａＡｓ層５Ａ」二に厚さ１μｍ程度の第２の単
結晶ＧａＡｓ層５Ｂをエピタキシャル成長させる。Referring to FIG. 2(C), a second single crystal GaAs layer 5B with a thickness of about 1 μm is epitaxially grown under the same conditions as in the epitaxial growth described in 1.
以」−のような方法により形成した単結晶ＧａＡｓ層５
表面部の転位密度は、第３図に示すｓｏｒ層の厚さと転
位密度の関係図から、Ｓｉ単結晶基板上に、直に、上記
実施例と同様の方法で形成した単結晶ＧａＡｓ層の転位
密度（八）の値に比べ、＜Ｃ＞ の点で示されるように
１／２程度に改善されていることがわかる。Single-crystal GaAs layer 5 formed by the method described below.
The dislocation density in the surface area can be determined from the relation diagram between the thickness of the SOR layer and the dislocation density shown in FIG. 3. It can be seen that compared to the value of density (8), it is improved to about 1/2 as shown by the point <C>.
第４図は、例えば」１記の方法で形成した３０１層３上
に単結晶ＧａＡｓ層５がヘテロエピタキシャル成長され
ているＧａＡｓ５ＯＩ基板２１を用いて形成したＭＥＳ
ＦＩＥＴを示した模式断面図で、６はリセス、７はア
ルミニウム（Ａ１）ゲート、８は金ゲルマニウム合金（
ＡｕＧｅ）層上に金（Ａｕ＞層が積層されてなるＡｕ／
ＡｕＧｅソース電極、９はＡｕ／ＡｕＧｅ ドレイン
電極、その他の符号は第１図と同一対称物を示す。FIG. 4 shows an MES formed using, for example, a GaAs5OI substrate 21 on which a single crystal GaAs layer 5 is heteroepitaxially grown on a 301 layer 3 formed by the method described in 1.
In the schematic cross-sectional view showing the FIET, 6 is a recess, 7 is an aluminum (A1) gate, and 8 is a gold-germanium alloy (
Au/AuGe) layer with gold (Au> layer laminated on top)
An AuGe source electrode, 9 an Au/AuGe drain electrode, and other symbols indicate the same symmetry as in FIG.
なお、本発明の構造は、素子が形成される半導体層に、
」１記ＧａＡｓ以外の■−Ｖ族化合物半導体を用いる際
にも適用される。例えば、ガリウム燐（ＧａＰ）を用い
る場合、ｓｏｒ層」−に単結晶ＧａＰ層形成する条件は
、例えば
反応ガス ｔイ２ １２ＳＬＭＰＨ３
３００ＳＣＣＭ
ＴＭＣ１４ＳＣＣＭ
圧力 ７ＱＴｏｒｒ成長温
度 ９００ °Ｃである。Note that the structure of the present invention includes a semiconductor layer in which an element is formed,
1.It is also applied when using a -V group compound semiconductor other than GaAs. For example, when using gallium phosphorus (GaP), the conditions for forming a single-crystal GaP layer on the sor layer are, for example, the reaction gas ti2 12SLMPH3
300SCCM TMC14SCCM Pressure: 7QTorr Growth temperature: 900°C.
また、本発明の構造は、素子が形成される半導体層にゲ
ルマニウム（Ｇｅ）を用いる際にも適用される。単結晶
Ｇｅ層を気相成長で形成する場合の条件は、例えば
反応ガス Ｈｚ ８ ＳＬ？ｌ
ＧｅＨ４１ｏ ＳＣＣＭ
圧力 １０Ｔｏｒｒ成長温
度 ６００ °Ｃである。Further, the structure of the present invention is also applied when germanium (Ge) is used in a semiconductor layer in which an element is formed. The conditions for forming a single crystal Ge layer by vapor phase growth are, for example, a reaction gas of Hz 8 SL? l
GeH41o SCCM pressure: 10 Torr growth temperature: 600°C.
更にまた、本発明の構造は、素子が形成される半導体層
にＧｅとＳｉの混晶を用いる際にも適用される。その場
合の気相成長条件は、例えば反応ガス Ｈｚ
８ ＳＬＭＧｅＨ４１０ＳＣＣＭ
Ｓ ！ Ｈ２Ｃ１２９ＳＣＣＭ
０Ｔｏｒｒ
６０ °Ｃ
圧力
成長温度
である。Furthermore, the structure of the present invention is also applied when a mixed crystal of Ge and Si is used in a semiconductor layer in which an element is formed. In that case, the vapor phase growth conditions are, for example, the reaction gas Hz
8 SLMGeH410SCCM S! H2C129SCCM 0 Torr 60 °C Pressure growth temperature.
以上説明したように本発明によれば、単結晶Ｓｉ上にヘ
テロエピタキシャル成長せしめたＧａＡｓ等の単結晶半
導体層内に発生する転位の密度を、従来に比べて１７２
程度に減少することができ、またそれと同時にストレス
も減少できるので、ヘテロエピタキシャル成長による半
導体層を用いて形成されるＧａＡｓ ＭＥＳＦＥＴ等の
半導体素子の、リーク電流による性能劣化を防止する効
果が生ずる。As explained above, according to the present invention, the density of dislocations generated in a single crystal semiconductor layer such as GaAs grown heteroepitaxially on single crystal Si can be reduced by 172% compared to the conventional method.
At the same time, the stress can be reduced to a certain degree, and at the same time, the stress can be reduced, which has the effect of preventing performance deterioration due to leakage current of semiconductor elements such as GaAs MESFETs formed using semiconductor layers formed by heteroepitaxial growth.
第１図は本発明に係る半導体基板の一実施例の模式断面
図、
第２図（ａ）乃至（Ｃ）は本発明に係る半導体基板の形
成方法の一実施例の工程断面図、
第３図は３０１層の厚さと、ヘテロエビクキシャル成長
ＧａＡｓ層の転位密度との関係図、第４図は本発明に係
る半導体基板を用いて形成した半導体素子の模式断面図
である。
図において、
１はＳｉ支持基板、
１は
２−！ｌ！−３ｉＯ２絶縁膜、
３は単結晶Ｓｉ層（ＳＯＴ層）、
４は非晶質ＧａＡｓ層、
５ば単結晶ＧａＡｓ層、
６はリセス、
７はΔ１ゲート、
８は八ｕ／ＡｕＧｅ ソース電極、
９はＡｕ／八ｕへｅ ドレイン電極
１１はＳＯ■基板、
２１はＧａＡｓ Ｓｏｌ基板、
１０１は単結晶Ｓｉ基板
を示す。
（２−改９）Ｖ赤患獅ω＆９■’り一FIG. 1 is a schematic cross-sectional view of an embodiment of a semiconductor substrate according to the present invention; FIGS. 2(a) to (C) are process cross-sectional views of an embodiment of a method for forming a semiconductor substrate according to the present invention; The figure is a relationship diagram between the thickness of the 301 layer and the dislocation density of the heteroepitaxially grown GaAs layer, and FIG. 4 is a schematic cross-sectional view of a semiconductor element formed using the semiconductor substrate according to the present invention. In the figure, 1 is a Si support substrate, 1 is 2-! l! -3iO2 insulating film, 3 is a single crystal Si layer (SOT layer), 4 is an amorphous GaAs layer, 5 is a single crystal GaAs layer, 6 is a recess, 7 is a Δ1 gate, 8 is an 8u/AuGe source electrode, 9 The drain electrode 11 is an SO2 substrate, 21 is a GaAs Sol substrate, and 101 is a single crystal Si substrate. (2-revised 9) V red disease lion ω & 9 ■' Riichi
Claims (5)
１５００Å以下の単結晶シリコン層上に、該単結晶シリ
コン層とヘテロ接合を形成する単結晶半導体層が形成さ
れていることを特徴とする半導体基板。(1) A single crystal semiconductor layer that forms a heterojunction with the single crystal silicon layer is formed on a single crystal silicon layer with a thickness of 1500 Å or less that is laminated on the support substrate with an insulating layer interposed therebetween. Characteristic semiconductor substrate.
とを特徴とする請求項（１）記載の半導体基板。(2) The semiconductor substrate according to claim (1), wherein the supporting substrate is made of a single crystal silicon substrate.
に形成した酸素のイオン注入によって形成された酸化シ
リコン層からなり、該単結晶シリコン層が該酸化シリコ
ン層の上部に残留する該単結晶シリコン層よりなること
を特徴とする請求項（２）記載の半導体基板。(3) The insulating layer is made of a silicon oxide layer formed by ion implantation of oxygen formed inside the single crystal silicon support substrate, and the single crystal silicon layer remains on the silicon oxide layer. 3. The semiconductor substrate according to claim 2, wherein the semiconductor substrate is made of a silicon layer.
れた再結晶シリコン層よりなることを特徴とする請求項
（１）及び（２）記載の半導体基板。(4) The semiconductor substrate according to claims (1) and (2), wherein the single crystal silicon layer is a recrystallized silicon layer stacked on the insulating layer.
混晶、又はゲルマニウム、又はシリコンとゲルマニウム
の混晶よりなることを特徴とする請求項（１）、（２）
、（３）及び（４）記載の半導体基板。(5) Claims (1) and (2) characterized in that the single crystal semiconductor layer is made of a III-V compound semiconductor mixed crystal, germanium, or a mixed crystal of silicon and germanium.
, (3) and (4).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12972390A JPH0425135A (en) | 1990-05-18 | 1990-05-18 | Semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12972390A JPH0425135A (en) | 1990-05-18 | 1990-05-18 | Semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0425135A true JPH0425135A (en) | 1992-01-28 |
Family
ID=15016607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12972390A Pending JPH0425135A (en) | 1990-05-18 | 1990-05-18 | Semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0425135A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7501318B2 (en) | 2003-05-30 | 2009-03-10 | International Business Machines Corporation | Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal |
| JP2010226079A (en) * | 2008-10-02 | 2010-10-07 | Sumitomo Chemical Co Ltd | Semiconductor substrate, electronic device, and method of manufacturing the semiconductor substrate |
-
1990
- 1990-05-18 JP JP12972390A patent/JPH0425135A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7501318B2 (en) | 2003-05-30 | 2009-03-10 | International Business Machines Corporation | Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal |
| JP2010226079A (en) * | 2008-10-02 | 2010-10-07 | Sumitomo Chemical Co Ltd | Semiconductor substrate, electronic device, and method of manufacturing the semiconductor substrate |
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