TW201015645A - Package substrate and fabrication method thereof - Google Patents

Package substrate and fabrication method thereof Download PDF

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Publication number
TW201015645A
TW201015645A TW097137666A TW97137666A TW201015645A TW 201015645 A TW201015645 A TW 201015645A TW 097137666 A TW097137666 A TW 097137666A TW 97137666 A TW97137666 A TW 97137666A TW 201015645 A TW201015645 A TW 201015645A
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TW
Taiwan
Prior art keywords
layer
openings
wafer
contact pads
solder
Prior art date
Application number
TW097137666A
Other languages
Chinese (zh)
Inventor
Hung-Sheng Hu
Wen-Sung Chang
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW097137666A priority Critical patent/TW201015645A/en
Publication of TW201015645A publication Critical patent/TW201015645A/en

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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a package substrate and a fabrication method thereof, comprising a substrate having a plurality of chip contacting pads formed on at least one surface thereof, a solder mask layer formed on the surface having via openings each corresponding to the contacting pads for allowing each pad to be exposed from the openings; a conductive layer formed on the contacting pads, the wall of the openings and peripheral ends of the openings; an electroplating tin material layer formed on the conductive layer, the tin material layer being formed on the contacting pads, the wall of the openings and peripheral ends of the openings to form a recessed portion, wherein the tin material layer formed on the contacting pads is not higher than the solder mask layer, thereby forming a recessed electroplating tin material layer having a larger size than the chip to facilitate positioning of the chip and the substrate and increase positioning precision.

Description

201015645 70、货明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體結構及其製法，尤指一種 封裝基板之表面結構及其製法。 【先前技術】 隨著電子產t的發達，現今的電子產&已趨向輕薄短 小與功能多樣化的方向發展，且半導體封裝技術亦隨之開 發出不同的封裝型態，傳統半導體裝置主要係在一封裝基 ❹板（Package Substrate)或導線架（Lead Frame)上先裝置 一例如積體電路之半導體晶片，再將該半導體晶片以㈣ 方式電性連接在該封裝基板或導線架上，接著以膠體進 封裝。 然而自從IB Μ公司在19 6 〇年早期引入覆晶封裝（F丨} p Chip Package)技術以來，相較於打線（Wire B〇nd)技術， 覆晶技術之特徵在於採用一封裝基板來安置半導體晶 片，並於該封裝基板表面植置多數個成陣列排列之焊錫凸 ©塊（Solder bumps)與半導體晶片間電性連接，再於該封裝 基板與半導體晶片之間填入底膠，以加強機械性之連接； 由於該封裝基板與半導冑晶片^間之電性連接並非透 過一般金線，且覆晶技術除可提高封裝結構佈線密度，使 相同單位面積上可以容納更多輸入/輸出連接端（1/0 connection)以達高度集積化（Integrati〇n)之效亦可降 低封裝結構整體尺寸，以達到微型化⑻心咖加⑽ 的封裝需求’更因不需使用導電路徑較細長之金線，而能 1.10939 5 201015645 nf m r且彳几’以提高電性功能。 凊芩閱第1A至1G圖，係為中華民國專利第I23962〇 號之封裝基板之製法示意圖；如第u圖所示，首先提供 一基板本體1〇，於該基板本體1〇具有植球面l〇a，於該 植球面10a具有複數植球塾101，於該植球面i〇a上具有 防焊層11 ’且該防焊層11中具有複數開孔，以對應 外露各該植球墊1G1;如第1β圖所示，於該些植球塾 1〇1、開孔UG之孔壁及防焊層U上以無電鑛或濺鑛方式 ❹形成有第-金屬層12;如第lc圖所示，於該第一金屬層 12上形成有阻層13，並形成有開口區13〇，以外露出該 ^孔U0周圍以外之第—金屬層12;如第㈣所示， 移除該開口區13〇中之第—金屬層12;如第1£圖所示， f除該阻層13;如第1F圖所示，以電鍍方式在該第一金 :層丄2上形成有第二金屬層14;如第1G圖所示，於該 第一金屬層14上形成有焊料社201015645 70. Description of the goods: [Technical field to which the invention pertains] The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a surface structure of a package substrate and a method of fabricating the same. [Prior Art] With the development of electronic products, today's electronic products & has become the trend of thin and light and diversified functions, and semiconductor packaging technology has also developed different packaging types, the main semiconductor devices Mounting a semiconductor wafer such as an integrated circuit on a package substrate or a lead frame, and then electrically connecting the semiconductor wafer to the package substrate or lead frame in a (4) manner, and then Encapsulated in a gel. However, since IB Corporation introduced the flip chip package (F丨} p Chip Package) technology in the early 19th century, the flip chip technology is characterized by a package substrate for placement compared to Wire B〇nd technology. a semiconductor wafer, and a plurality of solder bumps arranged in an array are electrically connected to the semiconductor wafer on the surface of the package substrate, and a primer is filled between the package substrate and the semiconductor wafer to strengthen Mechanical connection; Since the electrical connection between the package substrate and the semi-conductive wafer is not through the ordinary gold wire, and the flip chip technology can increase the wiring density of the package structure, so that more input/output can be accommodated in the same unit area. The connection end (1/0 connection) can also reduce the overall size of the package structure to achieve the miniaturization (8) packaging requirements of the top-of-the-line (10). The gold line, and can be 1.10939 5 201015645 nf mr and a few 'to improve the electrical function. 1A to 1G, which is a schematic diagram of a method for manufacturing a package substrate of the Republic of China Patent No. I23962; as shown in FIG. 5, a substrate body 1 is first provided, and a substrate 1 is provided on the substrate body 1 〇a, the ball-forming surface 10a has a plurality of ball-handling cymbals 101, and has a solder resist layer 11' on the ball-facing surface i〇a, and the solder resist layer 11 has a plurality of openings therein to correspondingly expose the ball-gluding pads 1G1 As shown in FIG. 1β, the first metal layer 12 is formed on the hole wall of the ball 塾1, the hole wall of the opening UG, and the solder resist layer U by electroless or splashing; as shown in FIG. As shown, a resist layer 13 is formed on the first metal layer 12, and an opening region 13 is formed to expose the first metal layer 12 except for the periphery of the hole U0; as shown in the fourth item, the opening is removed. a first metal layer 12 in the region 13; as shown in FIG. 1 , f is removed from the resist layer 13; as shown in FIG. 1F, a second layer is formed on the first gold layer 2 by electroplating a metal layer 14; as shown in FIG. 1G, a soldering society is formed on the first metal layer 14.

Ml羽 以供接置印刷電路板。 ❹今某板本體10 ^ D封職板之製法巾，係則虫刻方式於 ❹録板本體10上之植球塾m、開孔110之 Π0之周圍上形成該第一金屬層12，再以/孔 *二金屬層14’然後再於該第二金屬層14:二=: 焊料球15;准，該基板本體1〇須於形成該焊 係先形成該第一金屬層丨2 , 刖 層，導致製程複雜提高；又今層14等兩層金屬 第一金屬们且該 精度較差，較不適用於細線寬比之難控制、 110939 6 201015645 層主要#以钻μ+ 成有兩層金屬層，且該金屬 .二形ί，造成整體製程較複雜、較難控 【發明内容】· 声 '已成為目刖亟欲解決之課題。 ，供-知技術之缺失’本發明之-目的係在於提 •層，俾以簡化整體製程。 兩層金屣 ❹ :二一== 板易於對位且提高封裝難對晶片與基 招，：2述目的及其他目的’本發明揭露-種封裝基 墊於：矣.基板本體’其至少-表面具有複數晶片接觸 有防焊層，且該防焊層具㈣應各該晶片 接觸墊之複數開孔，以露出各該晶片接觸塾；導電層，係 設於各該晶片接觸墊、開孔之孔壁及孔端周圍上；以及電 ❹鍍鮮錫材料層，係設於該導電層上，且位於各該晶片接觸 墊、開孔之孔壁及孔端周圍上以形成凹部，而位於各該晶 片接觸塾上之電鍍銲錫材料層並未高於該防焊層表面。 依上述之封裝基板，該電鍍銲錫材料層係為錫（Sn)、 鉛（PW、銀Ug)、銅（Cu)、鋅（Zn)、鉍（Bi)、鎳（Ni)、鈀 (Pd)及金（Au)所組成之群組之其中一者。 本發明復提供一種封裝基板之製法，係包括：提供一 基板本體，其至少-表面具有複數晶片接觸墊；於該基板 110939 7 201015645 个籠以㈣成防焊層，且該防輝層具有對應各該 •觸塾之複數開孔，以使各該晶片接觸墊外露於各該 中；於該晶片接觸塾、開孔之孔壁及防烊層上形成恭 層；於該導電層上形成有阻層，並形成有開口區，: 出各該開孔及其周圍上之導電層；於該開口區中之導： 層上電鍍形成有電鍍銲錫材料層，使該電鍍銲錫材料層： 於各該晶片接觸塾、開孔之孔壁及孔端周圍上，以形成凹 部，而位於各該晶片接觸墊上之電鍍銲錫材料層並未高於 ❹該防焊層表面；以及移除該阻層及其所覆蓋之導電層？ 依上述之封裝基板之製法，該電鍍銲錫材料層係日為錫 (Sn)^〇KPb)^(Ag)^(Cu)^i(Zn)^(Bi)^(Ni). 把（Pd)及金（Au)所組成之群組之其中一者。 本發明之封裝基板及其製法，主要係於基板本體上之 晶片接觸墊、防焊層之開孔及其孔端周圍上電錢形成範圍 大於該晶片接觸墊且具有凹部之銲錫材料層，使該具有凹 部之電鍵銲踢材料層與半導體晶片之凸塊電性連接時，可 ❹，供定位以防止該半導體晶片的偏移。又，因範圍較大之 電鍍銲錫材料層具有凹部’當接置半導體晶片之凸塊時， 可使晶片凸塊產生自動對位的功能’以提高製程中對位的 準確丨生，且本發明僅於晶片接觸整上形成單層之銲錫材料 層，因此免除習知技術中必須使用兩層金屬層導致製程複 雜度增加之缺失。另外，本發明係應用於晶片接觸墊上以 供接置晶片，習知技術則應用於植球墊上以供接置印刷電 路板，且本發明主要係使用電鍍方式以形成銲錫材料層， 110939 8 201015645 相敉於習知技術中使用蝕刻的製作方式，俾能提高製程精 度，以因應細線寬比之封裝基板，並使晶片與基板易於^ 位且k而封裝體對位精度。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 4參閱第2A至2G圖，係提供本發明之封裝基板及其 ❹製法。 八 如第2A圖所示，提供一基板本體2〇，其至少一表面 具有複數晶片接觸墊2(n，於該基板本體2〇之表面形成 防焊層2卜且該防焊層21具有對應各該晶片接觸墊2〇1 之複數開孔210,以使各該晶片接觸塾2〇1外露於各該開 ❹ 第B圖所示，於各該晶片接觸墊gw、開孔 之孔壁及防焊層21上形成有導電層22。 如第2C圖所示， 並形成有開口區230， 之導電層22。 於該導電層22上形成有阻層23, 以外露出各該開孔21 〇及其周圍上 ίΓ圖所示，於該開口區230中之導電層22上電 位：該24,且該電鍍銲錫材料層24係 孔浐墊20、開孔210之孔壁及開孔210之 而。圍上，以形成凹部240，其中，位於各哕日κ桩觸 電鍍鲜錫材料層24表面並未高於該防焊層21 110939 9 201015645 衣®，錄電鍍銲錫材料層24係為錫（Sn)、鉛（pb)、^ (Ag)、銅（Cu)、鋅（zn)、鉍（jBi)、鎳（Ni)、鈀（pd)及金（A幻 所組成之群組之其中一者。 如第2E圖所示，移除該阻層23及其所覆蓋之導電層 22 〇 如第2F圖所示，提供一半導體晶月託，係結合至“ 電鍍銲錫材料層24上，該半導體晶片25具有作用面 25a，於該作用面25a上具有複數電極墊251，且該些電 ❹極墊251上具有凸塊26，以電性連接至該電鍍銲錫材^ 層24上，而將該半導體晶片25設於該基板本體μ上： 其中，該凸塊26係為錫（Sn)、鉛（pb)、銀（Ag)、銅（Cu)、 鋅（Zn)、鉍（Bi)、鎳（Ni)、鈀（pd)及金（Au)所組成之群“且 之其中一者。 如第2G圖所示，進行迴焊製程，使該電鍍銲錫材料 層24成為焊料球24, ’並電性連接至該半導體晶片託之 電極塾251;接著，於該半導體晶片25之作用面❿與 Ο该防焊層21之間形成有底膠27’藉以提高接合強度。由 於該電料錫材制24 <範圍大於各該晶片接觸塾 2〇1，因此即使該凸塊26與該電鍍銲錫材料層24之間產 生偏移，仍然能完成電性連接。 本發明復揭露一種封裳基板，係包括：基板本體2〇, >、至少一表面具有複數晶片接觸墊2〇1，於該基板本體加 =面設有防焊層…且該防焊層21具有對應各該晶片 接觸墊201之複數開孔210，以使各該晶片接觸塾201外 110939 10 201015645 路π分鉍開孔210中；導電層22,係設於各該晶片接觸 墊201、開孔210之孔壁及開孔21〇之孔端周圍上；以及 .電鍍銲錫材料層24，係設於該導電層22上，且該電鍍銲 錫材料層24係位於各該晶片接觸墊2〇 1、開孔21 〇之孔 壁及開孔210之孔端周圍上以形成凹部24〇，而位於各該 晶片接觸塾201上之電鍍銲錫材料層24並未高於該防焊 層21表面。 依上述之封裝基板，該電鍍銲錫材料層24係為錫 ❹（sioucpb)'銀（Ag)’（Cu)、辞（Ζη)、錢（Β〇、錄⑻）、 鈀（Pd)及金（AU)所組成之群組之其中一者。 本發明之封裝基板及其製法，主要藉由在該基板本體 ί之晶片接觸墊、防焊層之開孔及其孔端周圍上電鑛形成 軌圍大於該晶片接觸塾且具有凹部之鲜锡材料層，當該具 有凹部之電鑛銲錫材料層與半導體晶片結合時，能用以定 Ζ半導體曰曰片的凸塊。又’範圍較大之該電鍍銲錫材料 〇產部’可於接置半導體晶片之凸塊時，使晶片凸塊 發二 的功能’以提高製程中對位的準確性;且本 發明僅於各該晶片接觸熱 較於^ h 彡觸墊上形成早層之電鍍銲錫材料，相 加製i:、i二因本發明無需使用兩層金屬層，可避免增 電=二錫1祖义。另外，本發明係使用電鍍方式以形成該 本：r ;層’相較於習知技術中之使用蝕刻的方式， 以因應細線寬比之封裝基板，並 位精度。曰”基板本體易於對位且提高封裝的整體對 110939 11 201015645 工地實施例仙以例示性說明本發明之原理及盆功 - 而/用於限制本發明。任何熟習此項技藝之人士均可 .在不連背本發明之精神及範訂，對上述實施例進行修 =因此本發明之權利保護範圍，應如後述之中請專利範 圍所列。 【圖式簡單説明】 第1A至1G圖係為習知之封裝基板及其製法之剖視示 • 意圖；以及 〇 第2A至2G圖係為本發明之封裝基板及其製法之剖視 示意圖。 【主要元件符號說明】 10, 20 基板本體 10a 植球面 101 植球墊 11, 21 防焊層 110,210 開孔 12 第一金屬層 13, 23 阻層 130, 230 開口區 14 第二金屬層 15, 24， 焊料球 201 晶片接觸墊 22 導電層 24 電鍍銲錫材料層 110939 12 凹部 25 半導體晶片 25a 作用面 251 電極墊 26 凸塊 27 底膠 201015645Ml feather for the connection of printed circuit boards.制 某 某 板 板 板 板 10 10 10 10 10 10 10 10 10 10 10 10 10 10 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某 某And the second metal layer 14' and then the second metal layer 14: two =: solder ball 15; quasi, the substrate body 1 does not need to form the first metal layer 丨2, 刖Layer, which leads to complicated process improvement; two layers of metal first metal such as 14 layers and this precision is poor, it is not suitable for difficult control of thin line width ratio, 110939 6 201015645 layer main # drilled μ+ into two layers of metal The layer, and the metal. The shape of the metal is more complicated and difficult to control [invention content] · Sound 'has become a subject to be solved. The absence of a supply-to-know technology is the object of the present invention to improve the overall process. Two layers of gold enamel: two one == board is easy to align and improve the packaging is difficult for the wafer and the basic tricks: 2 Description of the purpose and other purposes 'The present invention discloses a kind of package base pad: 矣. substrate body 'at least - The surface has a plurality of wafers in contact with the solder resist layer, and the solder resist layer (4) is to have a plurality of openings of the wafer contact pads to expose the respective wafer contacts; the conductive layer is disposed on each of the wafer contact pads and the openings And surrounding the hole wall and the hole end; and the electroplating tin plating material layer is disposed on the conductive layer, and is located around each of the wafer contact pad, the opening hole wall and the hole end to form a concave portion, and is located at The layer of plated solder material on each of the wafer contacts is not higher than the surface of the solder mask. According to the above package substrate, the plating solder material layer is tin (Sn), lead (PW, silver Ug), copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd). One of the groups of gold (Au). The invention provides a method for manufacturing a package substrate, comprising: providing a substrate body having at least a surface having a plurality of wafer contact pads; wherein the substrate 110939 7 201015645 is caged with (4) a solder resist layer, and the anti-glaze layer has a corresponding Each of the plurality of contacts is opened to expose the wafer contact pads to each of the pads; a silicon layer is formed on the wafer contact opening, the opening wall and the anti-corrugation layer; and the conductive layer is formed on the conductive layer a resist layer formed with an open area, wherein: a conductive layer on each of the openings and the periphery thereof; and a guide layer in the open area: a layer of an electroplated solder material is formed on the layer to make the electroplated solder material layer: The wafer contacts the sidewall of the opening, the opening of the opening, and the periphery of the opening to form a recess, and the layer of the plated solder material on each of the wafer contact pads is not higher than the surface of the solder resist; and the resist is removed and The conductive layer covered by it? According to the above method for manufacturing a package substrate, the layer of the plated solder material is tin (Sn)^KPb)^(Ag)^(Cu)^i(Zn)^(Bi)^(Ni). (Pd) One of the groups of gold (Au). The package substrate of the present invention and the method for fabricating the same are mainly for the wafer contact pad on the substrate body, the opening of the solder resist layer and the solder material around the hole end to form a solder material layer having a recess larger than the wafer contact pad and having a recess. When the conductive bonding material layer having the recess is electrically connected to the bump of the semiconductor wafer, it can be positioned to prevent the semiconductor wafer from being displaced. Moreover, since the plated solder material layer having a larger range has a recessed portion 'when the bump of the semiconductor wafer is attached, the wafer bump can be automatically positioned to improve the alignment, so that the accurate alignment of the alignment in the process is improved, and the present invention A single layer of solder material layer is formed only on the wafer contact, thus eliminating the need to use two metal layers in the prior art to cause a lack of process complexity. In addition, the present invention is applied to a wafer contact pad for attaching a wafer, and the prior art is applied to a ball pad for receiving a printed circuit board, and the present invention mainly uses an electroplating method to form a solder material layer, 110939 8 201015645 In contrast to the conventional etching method used in the prior art, the process precision can be improved to accommodate the package substrate in accordance with the thin line width ratio, and the wafer and the substrate can be easily positioned and k can be aligned with the package. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand the other advantages and functions of the present invention from the disclosure. 4 Referring to Figures 2A to 2G, a package substrate of the present invention and a tanning method thereof are provided. As shown in FIG. 2A, a substrate body 2 is provided, at least one surface of which has a plurality of wafer contact pads 2 (n, a solder resist layer 2 is formed on the surface of the substrate body 2, and the solder resist layer 21 has a corresponding Each of the wafers contacts a plurality of openings 210 of the pad 2〇1 such that each of the wafer contacts 塾2〇1 is exposed to each of the openings B, and the wafer contact pads gw, the opening walls of the openings, and A conductive layer 22 is formed on the solder resist layer 21. As shown in Fig. 2C, an open region 230 is formed, and a conductive layer 22 is formed. A resist layer 23 is formed on the conductive layer 22, and each of the openings 21 is exposed. And the surrounding portion of the conductive layer 22 in the open region 230 has a potential: the 24, and the layer of the plated solder material 24 is the hole pad 20, the hole wall of the opening 210, and the opening 210 Surrounding, to form a recess 240, wherein the surface of the κp-plated electroplated fresh tin material layer 24 is not higher than the solder resist layer 21 110939 9 201015645, and the electroplated solder material layer 24 is tin ( Sn), lead (pb), ^ (Ag), copper (Cu), zinc (zn), ytterbium (jBi), nickel (Ni), palladium (pd), and gold As shown in FIG. 2E, the resist layer 23 and the conductive layer 22 covered thereon are removed, as shown in FIG. 2F, and a semiconductor crystal holder is provided, which is bonded to the “plated solder material layer 24”. The semiconductor wafer 25 has an active surface 25a having a plurality of electrode pads 251 on the active surface 25a, and the electrical pads 251 have bumps 26 electrically connected to the plating solder layer 24. The semiconductor wafer 25 is disposed on the substrate body μ: wherein the bumps 26 are tin (Sn), lead (pb), silver (Ag), copper (Cu), zinc (Zn), and bismuth (Bi). And one of the group consisting of nickel (Ni), palladium (pd), and gold (Au). As shown in Fig. 2G, a reflow process is performed to make the plated solder material layer 24 a solder ball 24 And electrically connected to the electrode 251 of the semiconductor wafer holder; then, a primer 27' is formed between the active surface of the semiconductor wafer 25 and the solder resist layer 21 to improve the bonding strength. The tin material 24 < is larger than each of the wafer contacts 塾2〇1, so even if the bump 26 and the plated solder material layer 24 are produced The substrate is further offset, and the electrical connection can still be completed. The present invention discloses a substrate for sealing, comprising: a substrate body 2, > at least one surface having a plurality of wafer contact pads 2〇1, and the substrate body is added to the surface a solder mask layer is provided, and the solder resist layer 21 has a plurality of openings 210 corresponding to the respective wafer contact pads 201, such that the wafers are in contact with the outer surface 110130 10 201015645 π minute opening 210; the conductive layer 22 Provided on the wafer contact pad 201, the hole wall of the opening 210, and the hole end of the opening 21〇; and the plating solder material layer 24 is disposed on the conductive layer 22, and the plating solder material The layer 24 is located around each of the wafer contact pads 2, 1 and 20, and around the hole end of the opening 210 to form a recess 24, and the layer of the plated solder material 24 on each of the wafer contacts 201. It is not higher than the surface of the solder resist layer 21. According to the above package substrate, the plating solder material layer 24 is tin cp si si si si si si si si 银 银 银 银 银 银 银 si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si One of the groups consisting of AU). The package substrate of the present invention and the method for manufacturing the same are mainly characterized in that the wafer contact pad, the opening of the solder resist layer and the hole end of the substrate body are electrically formed to form a tin with a track circumference larger than the contact of the wafer and having a concave portion. The material layer, when the conductive ore solder material layer having the recess is combined with the semiconductor wafer, can be used to define the bump of the semiconductor wafer. Moreover, the larger range of the electroplated solder material manufacturing department can "make the function of the wafer bumps when the bumps of the semiconductor wafer are attached" to improve the accuracy of the alignment in the process; and the present invention is only applicable to each The wafer is in contact with the hot-plated solder material formed on the touch pad, and is added to the i:, i. Since the present invention does not require the use of two metal layers, the power-increasing = tin-tin is avoided. Further, the present invention uses an electroplating method to form the present: r; layer' is compared with the etching method in the prior art, in order to meet the fine line width ratio of the package substrate, and the bit precision.基板"The substrate body is easy to align and improve the overall integrity of the package. 110939 11 201015645 The construction site is illustrative of the principles and potting of the present invention - and / is used to limit the invention. Anyone skilled in the art can. The above embodiments are modified without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patents described below. [Simple Description of the Drawings] Figures 1A to 1G FIG. 2A to 2G are schematic cross-sectional views showing a package substrate of the present invention and a method of manufacturing the same. [Main component symbol description] 10, 20 substrate body 10a Spherical 101 ball pad 11, 21 solder mask 110, 210 opening 12 first metal layer 13, 23 resist layer 130, 230 open region 14 second metal layer 15, 24, solder ball 201 wafer contact pad 22 conductive layer 24 electroplated solder Material layer 110939 12 recess 25 semiconductor wafer 25a active surface 251 electrode pad 26 bump 27 primer 201015645

13 11093913 110939

Claims (1)

201015645^ ^ _ τ、τ請專利範圍： 1. 一種封裝基板，係包括： • 基板本體，其至少一表面具有複數晶片接觸墊， 於該表面設有防焊層，且該防焊層具有對應各該晶片 接觸墊之複數開孔，以露出各該晶片接觸墊； 導電層，係設於各該晶片接觸墊、開孔之孔壁及 孔端周圍上；以及 電鍍銲錫材料層，係設於該導電層上，且位於各 ❹ 該晶片接觸墊、開孔之孔壁及孔端周圍上以形成凹 部，而位於各該晶片接觸墊上之電鍍銲錫材料層並未 高於該防焊層表面。 2·如申請專利範圍帛！項之封裝基板，纟中，該電錢銲 錫材料層係為錫（Sn)、鉛（Pb)、銀Qg) '銅（Cu；)、鋅 (Zn)、鉍（Bi)、鎳（Ni)、鈀（Pd)及金（Au)所組成之群 組之其中一者。 3. 一種封裝基板之製法，係包括： 0 I供-基板本體，其至少—表面具有複數晶片接 觸墊； 於該基板本體之表面形成防焊層，且該防焊層具 有對應各該晶片接觸墊之複數開孔，以使各該晶片接 觸墊外露於各該開孔中； 於各該晶片接觸墊、開孔之孔壁及防焊層上形成 有導電層； 於該導電層上形成有阻層，並形成有開口區，以 110939 14 201015645 , 邓路出各該開孔及其周圍上之導電層； 於ί亥開口區中之莫當爲 - 電層上電鍍形成有電鍍銲錫 . ㈣層’使_鎮銲錫材料層位於各該晶片 開孔之孔壁及孔端周圍上，以形成凹部，而位於各該 晶片接觸塾上之電鑛銲錫材料層並未高於該防焊層 表面；以及 移除該阻層及其所覆蓋之導電層。 4.如申δ月專利範圍第3項之封裝基板之製法，其中，該 ❹電鑛錦锡材料層係為錫（Sn)、鉛（Pb)、銀（Ag)、銅 (Cu)、鋅（zn)、鉍（Bi)、鎳（Ni)、鈀（pd)及金（Au)所 組成之群組之其中一者。201015645^^ _ τ, τ Please patent scope: 1. A package substrate comprising: • a substrate body having at least one surface having a plurality of wafer contact pads, a solder resist layer disposed on the surface, and the solder resist layer having a corresponding Each of the wafer contacts a plurality of openings of the pad to expose each of the wafer contact pads; a conductive layer is disposed around each of the wafer contact pads, the opening and the hole end of the opening; and the layer of the plated solder material is The conductive layer is disposed on each of the wafer contact pads, the hole walls and the hole ends to form a recess, and the layer of the plated solder material on each of the wafer contact pads is not higher than the surface of the solder resist layer. 2. If you apply for a patent range! The package substrate of the item, in the middle, the layer of the electric solder material is tin (Sn), lead (Pb), silver Qg) 'copper (Cu;), zinc (Zn), bismuth (Bi), nickel (Ni) One of a group consisting of palladium (Pd) and gold (Au). A method for manufacturing a package substrate, comprising: a substrate having at least a surface having a plurality of wafer contact pads; forming a solder resist layer on a surface of the substrate body, wherein the solder resist layer has a contact corresponding to each of the wafers a plurality of openings of the pad, such that each of the wafer contact pads is exposed in each of the openings; a conductive layer is formed on each of the wafer contact pads, the opening holes and the solder resist layer; and the conductive layer is formed on the conductive layer The resist layer is formed with an open area to 110939 14 201015645, Deng Lu exits the conductive layer on each of the openings and the periphery thereof; in the opening area of the 亥hai, the electric layer is plated with electroplated solder. (4) The layer 'make the solder material layer around the hole wall and the hole end of each of the wafer openings to form a recess, and the layer of the electric ore solder material on each of the wafer contact pads is not higher than the surface of the solder resist layer And removing the resist layer and the conductive layer it covers. 4. The method for manufacturing a package substrate according to item 3 of the patent scope of the invention, wherein the layer of the tin ore material is tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc. One of a group consisting of (zn), bismuth (Bi), nickel (Ni), palladium (pd), and gold (Au). 110939 15110939 15
TW097137666A 2008-10-01 2008-10-01 Package substrate and fabrication method thereof TW201015645A (en)

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