TW201011773A - Semiconductor memory device and driving method thereof - Google Patents

Semiconductor memory device and driving method thereof Download PDF

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TW201011773A
TW201011773A TW098102087A TW98102087A TW201011773A TW 201011773 A TW201011773 A TW 201011773A TW 098102087 A TW098102087 A TW 098102087A TW 98102087 A TW98102087 A TW 98102087A TW 201011773 A TW201011773 A TW 201011773A
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drive
control signal
input
pull
main
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TW098102087A
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TWI417896B (en
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Ki-Ho Kim
Kang-Seol Lee
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

A semiconductor memory device includes a data input driver and a data output driver for receiving an external power supply voltage, and for inputting and outputting data, respectively; and a voltage detector for detecting the external power supply voltage to generate a detection signal, wherein a drive current of each of the data input driver and the data output driver is controlled by the detection signal.

Description

201011773 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體設計技術，且更特定言之，係 關於一種具備分別用於輸入及輸出資料之資料輸二驅動器 及資料輸出驅動器的半導體記憶體裝置，及其驅動方法。 本發明主張2008年9月10日所申請之韓國專利申锖案第 10·薦，細號之優先權，該案之全部内容以引用的方 式併入。 【先前技術】 大體而言，半導體記憶體裝置（包括雙資料速 RAM(DDR SDRAM))根㈣央4理單⑽pu)所要求之命 令儲存或輸出資料。若自CPU提供寫入命令，則來自外部 之資料經儲存於對應於C P U所要求之位址的記憶體單元 中’且若自CPU提供讀取命令’則對應於cpu所要求之位 址的記憶體單元中所健存的資料經輸出至外部。亦即，在 寫入操作中’輸入資料經由資料輸入/輸出襯塾而應用至 資料輸人㈣H且接㈣人至記憶體單元，且在讀取操作 中，待自半導體記憶體裝置輸出之資料首先提供至資料輸 出驅動器且接著經由輸入/輸出概塾輸出至外部。 圖1為說明典型資料輸入驅動器11〇及資料輸出驅動器 130之電路圖。 參看圖1，：备刺_ h θ 貫料輸入驅動器no比較經由輸入/輸出襯墊 ，所提供之輸入資料信號DIN與外部參考信號VREF且緩 衝較、π果以輪出内部資料信號。此處，外部參 13751l.doc 201011773 考信號VREF為自外部提供之電壓且具有施加至半導體記 憶體裝置之外部電源電壓VDD的1/2電壓位準。且，啟動 信號EN用以啟動資料輸入驅動器11〇之輸入操作且在半導 體記憶體裝置之寫入操作期間啟動。 資料輸出驅動器130回應於待自半導體記憶體裝置輸出 之資料k號DAT—PU及DAT—PD而驅動輸出端子（輸出端子 表示輸出資料信號DOUT所輸出至之節點），且經由輸入/ 輸出襯墊150將輸出資料信號DOUT輸出至外部。資料輸出 驅動器130包括上拉預驅動單元丨32、下拉預驅動單元i34 及主驅動單元136。 回應於上拉資料信號DAT一PU，上拉預驅動單元13 2產生 上拉驅動控制信號CTR一PU，且回應於下拉資料信號 DAT_PD，下拉預驅動單元134產生下拉驅動控制信號 CTR一PD »此處，舉例而言，上拉資料信號DAT一up及下拉 資料信號DAT_PD指示與自延遲鎖定迴路（未圖示）所產生 之時脈信號同步的資料信號。 回應於上拉驅動控制信號CTR_PU及下拉驅動控制信號 CTR一PD ’主驅動單元136上拉或下拉驅動輸出端子。亦 即，輸出資料信號DOUT回應於上拉驅動控制信號CTR_PU 而變為邏輯’高1且回應於下拉驅動控制信號CTR_PD而變為 邏輯'低％ 圖2A、圖2B及圖2C為用於解釋圖1中所展示之資料輸入 驅動器110之輸入操作的波形圖，其中視外部電源電壓 VDD之電壓位準而定，資料輸入驅動器ι10具有如所展示 137511.doc 201011773 之三個波形。 圖2A展示外部電源電壓Vdd具有初始設計中所考慮之電 壓位準（下文稱為目標電壓位準）的狀況。在此狀況下，為 解釋方便起見，圖1中所展示之外部參考電壓VREF、輸入 資料信號DIN及内部資料信號DAT_INN將分別被稱為 VREF—Μ、DIN_MADAT_INN一Μ。 參看圖1及圖2Α，資料輸入驅動器110比較輸入資料信號 DIN_M與外部參考信號VREF_M以輸出内部資料信號 ® DAT—INN_M。此處，輸入資料信號DIN以相對於外部參考 電壓VREF之50:50之作用時間比率（duty ratio)經輸入。因 此’内部資料信號DAT_INN_M亦以50:50之作用時間比率 經輸出。 圖2B展示外部電源電壓VDD低於目標電壓位準之狀況。 在此狀況下，為解釋方便起見，圖1中之外部參考電壓 VREF、輸入資料信號DIN及内部資料信號DAT—INN將分 • 別被稱為 VREF L、DIN L及 DAT INN L。 — — — — 參看圖1及圖2B，資料輸入驅動器110比較輸入資料信號 DIN一L與外部參考信號VREF—L以產生内部資料信號 • DAT_INN_L。此時，輸入資料信號DIN—L以相對於外部參 考電壓VREFJL所預設之最大電壓位準與最小電壓位準之 間的電壓位準經輸入。因此，其具有50:50之作用時間比 率，如圖2A之狀況中。 然而，因為外部電源電壓VDD之電壓位準低於目標電壓 位準以減小資料輸入驅動器110之驅動電流，所以圖2B中 137511.doc 201011773 之内部資料信號DAT_INN_L不維持50:50之作用時間比 率。 圖2C表示外部電源電壓Vdd高於目標電壓位準之狀況。 在此狀況下’為解釋方便起見，圖1中之外部參考電壓 VREF、輸入資料信號DIN及内部資料信號dat_INN將分 別被稱為 VREF_H、DIN Η及 DAT INN Η。 參看圖1及圖2C，資料輸入驅動器110藉由外部電源電壓 VDD之較高電壓位準而具有增加之驅動電流。因此，内部 資料信號DAT一ΙΝΝ_Η不維持50:50之作用時間比率，如圖 2Β之狀況中。 亦即’在圖2Β及圖2C之狀況中，視外部電源電壓vdd 之電壓位準而定’内部資料信號之作用時間比率變為非恆 定。此非怪定作用時間比率導致内部資料信號之可靠性降 低。 圖3展示用於解釋圖丨中所展示之資料輸出驅動器13〇之 輸出操作的波形。 如圖1中所描述，資料輸出驅動器丨3〇由上拉預驅動單元 132及下拉預驅動單元134，以及主驅動單元136構成。上 拉預驅動單元132及下拉預驅動單元134判定主驅動單元 3 6變為接通或斷開之時間點且亦基於所判定之時間點來 判定待自主驅動單元136輸出之輸出資料信號D〇UT的轉換 速率（slew rate)。 接下來，主驅動單元136中所提供之PM〇s電晶體由上拉 預驅動單元132中所提供之NM〇s電晶體接通且主驅動單元 137511 .doc 201011773 136中所提供之NMOS電晶體由下拉預驅動單元134中所提 供之PMOS電晶體接通。由於此，上拉預驅動單元丨32中之 NMOS電晶體及下拉預驅動單元134中之PM〇s電晶體應以 適當大小來設計’尤其藉由考慮轉換速率。 圖3之（A)、（B)及（〇中所展示者為上拉資料信號 DAT_PU、下拉資料信號DAT—pD、圖3之外部電源電壓 VDD具有目標電壓位準之（A)狀況中的輸出資料信號 DOUT—M、圖3之外部電源電壓VDD低於目標電壓位準之 (B)狀況中的輸出資料信號d〇ut_l，及圖3之外部電源電 壓VDD高於目標電壓位準之（c)狀況中的輸出資料信號 DOUT_H。201011773 VI. Description of the Invention: Technical Field of the Invention The present invention relates to a semiconductor design technique, and more particularly to a semiconductor having a data input driver and a data output driver for inputting and outputting data, respectively. Memory device, and its driving method. The present invention claims the priority of the Korean Patent Application filed on September 10, 2008, the priority of the serial number, the entire contents of which are incorporated by reference. [Prior Art] Generally, a semiconductor memory device (including a double data rate RAM (DDR SDRAM)) root (4) central 4 (10) pu) is required to store or output data. If a write command is provided from the CPU, the external data is stored in the memory unit corresponding to the address required by the CPU 'and if the read command is supplied from the CPU', the memory corresponding to the address required by the CPU is stored. The data stored in the body unit is output to the outside. That is, in the write operation, the input data is applied to the data input (4)H and the (4) person to the memory unit via the data input/output pad, and the data to be output from the semiconductor memory device in the read operation. It is first provided to the data output driver and then output to the outside via the input/output overview. 1 is a circuit diagram showing a typical data input driver 11 and data output driver 130. Referring to Figure 1, the spur _ h θ traverse input driver no compares the input data signal DIN and the external reference signal VREF via the input/output pad, and the π is used to rotate the internal data signal. Here, the external reference 13751.doc 201011773 test signal VREF is a voltage supplied from the outside and has a 1/2 voltage level applied to the external power supply voltage VDD of the semiconductor memory device. Moreover, the enable signal EN is used to initiate an input operation of the data input driver 11 and is activated during a write operation of the semiconductor memory device. The data output driver 130 drives the output terminal in response to the data k number DAT_PU and DAT_PD to be output from the semiconductor memory device (the output terminal indicates the node to which the output data signal DOUT is output), and via the input/output pad 150 outputs the output data signal DOUT to the outside. The data output driver 130 includes a pull-up pre-drive unit 丨32, a pull-down pre-drive unit i34, and a main drive unit 136. In response to the pull-up data signal DAT-PU, the pull-up pre-drive unit 13 2 generates a pull-up drive control signal CTR-PU, and in response to the pull-down data signal DAT_PD, the pull-down pre-drive unit 134 generates a pull-down drive control signal CTR-PD » For example, the pull-up data signal DAT-up and pull-down data signal DAT_PD indicate a data signal synchronized with a clock signal generated from a delay locked loop (not shown). The main drive unit 136 pulls up or pulls down the drive output terminal in response to the pull-up drive control signal CTR_PU and the pull-down drive control signal CTR_PD'. That is, the output data signal DOUT becomes a logic 'high 1 in response to the pull-up drive control signal CTR_PU and becomes a logic 'low % in response to the pull-down drive control signal CTR_PD. FIG. 2A, FIG. 2B, and FIG. The data shown in Figure 1 is input to a waveform diagram of the input operation of the driver 110, wherein the data input driver ι 10 has three waveforms as shown by 137511.doc 201011773, depending on the voltage level of the external power supply voltage VDD. Fig. 2A shows a state in which the external power supply voltage Vdd has a voltage level considered in the initial design (hereinafter referred to as a target voltage level). In this case, for convenience of explanation, the external reference voltage VREF, the input data signal DIN, and the internal data signal DAT_INN shown in Fig. 1 will be referred to as VREF-Μ, DIN_MADAT_INN, respectively. Referring to Figures 1 and 2, the data input driver 110 compares the input data signal DIN_M with the external reference signal VREF_M to output an internal data signal ® DAT_INN_M. Here, the input data signal DIN is input with a duty ratio of 50:50 with respect to the external reference voltage VREF. Therefore, the internal data signal DAT_INN_M is also output at a time ratio of 50:50. Figure 2B shows the condition in which the external supply voltage VDD is below the target voltage level. In this case, for the convenience of explanation, the external reference voltage VREF, the input data signal DIN and the internal data signal DAT_INN in Fig. 1 will be referred to as VREF L, DIN L and DAT INN L, respectively. — — — — Referring to FIGS. 1 and 2B, the data input driver 110 compares the input data signal DIN_L with the external reference signal VREF-L to generate an internal data signal • DAT_INN_L. At this time, the input data signal DIN_L is input at a voltage level between the maximum voltage level and the minimum voltage level preset with respect to the external reference voltage VREFJL. Therefore, it has an action time ratio of 50:50, as in the case of Fig. 2A. However, since the voltage level of the external power supply voltage VDD is lower than the target voltage level to reduce the driving current of the data input driver 110, the internal data signal DAT_INN_L of 137511.doc 201011773 in FIG. 2B does not maintain the 50:50 action time ratio. . Fig. 2C shows a state in which the external power supply voltage Vdd is higher than the target voltage level. In this case, for the convenience of explanation, the external reference voltage VREF, the input data signal DIN and the internal data signal dat_INN in Fig. 1 will be referred to as VREF_H, DIN Η and DAT INN 分, respectively. Referring to Figures 1 and 2C, data input driver 110 has an increased drive current by a higher voltage level of external supply voltage VDD. Therefore, the internal data signal DAT_ΙΝΝ_Η does not maintain a 50:50 action time ratio, as shown in Figure 2Β. That is, in the case of Figs. 2A and 2C, the ratio of the action time of the internal data signal becomes non-constant depending on the voltage level of the external power supply voltage vdd. This non-stranged time ratio results in a decrease in the reliability of the internal data signal. Fig. 3 shows waveforms for explaining the output operation of the data output driver 13A shown in Fig. As described in FIG. 1, the data output driver 丨3〇 is composed of a pull-up pre-drive unit 132 and a pull-down pre-drive unit 134, and a main drive unit 136. The pull-up pre-drive unit 132 and the pull-down pre-drive unit 134 determine the time point at which the main drive unit 36 becomes on or off and also determine the output data signal D to be output by the autonomous drive unit 136 based on the determined time point. The slew rate of the UT. Next, the PM〇s transistor provided in the main driving unit 136 is turned on by the NM〇s transistor provided in the pull-up pre-driving unit 132 and the NMOS transistor provided in the main driving unit 137511 .doc 201011773 136 The PMOS transistor provided in the pull-down pre-drive unit 134 is turned on. Because of this, the NMOS transistors in the pull-up pre-driver unit 及32 and the PM〇s transistors in the pull-down pre-drive unit 134 should be designed in an appropriate size, especially by considering the slew rate. In (A), (B) and (A), the pull-up data signal DAT_PU, the pull-down data signal DAT-pD, and the external power supply voltage VDD of FIG. 3 have a target voltage level (A). The output data signal DOUT-M, the external power supply voltage VDD of FIG. 3 is lower than the target voltage level (B), the output data signal d〇ut_l, and the external power supply voltage VDD of FIG. 3 is higher than the target voltage level ( c) Output data signal DOUT_H in the condition.

如自圖式可見，在圖3之（B)狀況中，外部電源電壓VDD 具有較低電壓位準，使得上拉預驅動單元132及下拉預驅 動單7L 134使主驅動單元136之接通/斷開時間點較慢❶因 此，輸出資料信號DOUT—L之轉換速率變為較小。亦即， 輸出資料信號D0UT—L之斜率變為小於圖3之（A)中之 DOUT_M的斜率。 相反地，在圖3之（〇狀況中，外部電源電壓VDD具有較 同電壓位準’使得主驅動單元丨36之接通/斷開時間點變為 較快。因A，輸出資料信號D〇UT—H之轉換速率變為較 大。亦即，輸出資料信號D〇UT_H之斜率變為大於圈"3之 (A)中之〇〇1；丁_^4的斜率。 亦即’在圖3之(B)及(c)狀況中，輸出資料信號之轉換 速率視外部電源電壓VDD之電壓位準而變化。大體而言，、 137511.doc 201011773 因為輸出資料信號之轉換速率與資料可靠性及功率消耗有 關所以較佳以應基於資料可靠性及功率消耗而恰當地維 持轉換速率之方式來設計。然而，圖3之（B)及（C)中所說明 的狀況不維持轉換速率。 • 圖4A及圖4B為用於依據圖1中之主驅動單元130之外部 . 電源VDD解釋電流特性的視圖。亦即，圖4A表示在下拉操 作’月間由主驅動單元13〇所消耗之電流的特性且圖4b表示 φ 在上拉操作期間由主驅動單元130所消耗之電流的特性。 圖A及圖4B中之母一者中，兩條特性線①分別指示所消 電流之下限及上限，其係根據規範而界定。特性線② 表示外部電源電壓VDD高於目標電壓位準之狀況，且特性 線③表示外部電源電壓VDD具有目標電壓位準之狀況。特 性線④表示外部電源電壓VDD低於目標電壓位準之狀況。 如自圖4A及圖4B可見’戶斤消耗之電流不隨外部電源之 電壓位準變化而滿足規範。 • 如上文所描述，視外部電源電壓VDD之電壓位準而定， 典型資料輸入驅動器11〇及資料輸出驅動器13〇具有不同操 作特性。此不可確保資料輸入驅動器110與CPU之間及資 . #輸出驅動器13喷CPU之間的資料交換操作之足夠可靠 - 性〇 此外，因為所消耗之電流存在於規範中所界定之範圍 外，所以產品之大量生產可減少且相容性可降低。亦即， 若所製造之產品不滿足規範，則其作為不良品而處理，由 此降低大量生產之效率。舉例而言，假設存在使用i 乂之 137511.doc 201011773 外部電源電壓VDD及使用1.5 V之外部電源電壓vdd的環 境。在此狀況下，若其中一者不滿足規範，則相容性可降 低0 【發明内容】 本發明之一實施例係針對提供一種能夠視外部電源電壓 之電壓位準而控制輸入及輸出電路之驅動電流的半導體·^己 憶體裝置。 本發明之另一實施例係針對提供一種能夠確保輸入至輸 入及輸出電路或自輸入及輸出電路輸出之資料可無關於外 部電源電壓而可靠地具有相同操作特性之半導體記憶體裝 置。 根據本發明之一態樣，提供一種半導體記憶體裝置，其 包括：一資料輸入驅動器及一資料輸出驅動器，其用於接 收外部電源電壓’且分別用於輸入及輸出資料；及一電壓 偵測器，其用於偵測外部電源電壓以產生一偵測信號，其 中資料輸入驅動器及資料輸出驅動器中之每一者的驅動電 流由該偵測信號控制。 根據本發明之一態樣，提供一種用於半導體記憶體裝置 中之讀取驅動電路，該讀取驅動電路包括：一預驅動單 元，其用於產生對應於内部資料之驅動控制信號；一主驅 動單元，其用於回應於驅動控制信號而將對應於内部資料 之輸出資料提供至其輸出端子；及—電㈣測器，其用於 積測外部電源電塵以產生一偵測信號以控制預驅動單元及 主驅動單元中之每一者的驅動電流。 1375ll.doc 201011773 根據本發明之一態樣，提供一種一半導體記憶體裝置之 驅動方法，其包括：偵測外部電源電壓之電壓位準；若外 部電源電壓基於偵測結果高於目標電壓位準，則藉由小於 對應於外部電源電壓之驅動電流的驅動電流執行資料之輸 入/輸出操作；及若外部電源電壓基於偵測結果低於目標 電壓位準，則藉由大於對應於外部電源電壓之驅動電流的 驅動電流執行資料之輸入/輸出操作。 本發明偵測外部電源電壓之電壓位準且基於該所偵測之 電壓位準控制半導體記憶體裝置中之輸入及輸出電路的驅 動電流，使得輸入及輸出電路可始終具有相同操作特性。 【實施方式】 下文中’將參看附隨圖式詳細地描述本發明之較佳實施 .例’使得熟習此項技術者可容易地實踐本發明。 圖5為說明用於解釋根據本發明之實施例的半導體記憶 體裝置之部分組態的方塊圖。 參看圖5 ’半導體記憶體裝置包括電壓偵測器5丨〇、資料 輸入驅動器530、資料輸出驅動器55〇及輸入/輸出襯墊 570 〇 電壓偵測器5 10用以偵測外部電源電壓vdD之電壓位準 以回應於外部電源電壓VDD及外部參考電壓VREF而產生 第一偵測信號DET—HVDD及第二偵測信號DET_LVDD ^外 部參考電壓VREF為自外部提供之電壓且具有（例如）施加至 半導體記憶體裝置之外部電源電壓VDD的1 /2位準。 資料輸入驅動器530自輸入/輸出襯墊570接收輸入資料 137511.doc •10- 201011773 k號DIN以產生内部資料信號DΑΤ—ΙΝΝ，且資料輸出驅動 器550獲得待輸出之資料信號DAT_PU及DAT_PD以產生用 於輸出至輸入/輸出襯墊570的輸出資料信號D〇UT。 此處’資料輸入驅動器530及資料輸出驅動器550接收外 部電源電壓VDD ’且資料輸入驅動器530之驅動電流及資 料輸出驅動器550之驅動電流可回應於稍後描述之第一摘 測信號DET—HVDD及第二偵測信號DETJLVDD而受到控 制。 圖6為說明圖5中所展示之電壓偵測器5 1 〇的詳細電路 圖。 參看圖6 ’電壓偵測器510包括分別用於產生第一價測信 號DET—HVDD及第二偵測信號DETJLVDD之第一债測信號 產生器610及第二偵測信號產生器630。 第一偵測信號產生器610用於偵測外部電源電壓VDD之 電壓位準以產生第一偵測信號DET_HVDD，且具備分壓器 612、電壓比較器614及偵測信號輸出部分61 6。 分壓器612用於劃分外部電源電壓VDD以產生具有預定 電壓位準之第一參考電壓HVREF，且具備耦接於外部電源 電壓VDD端子與接地電壓VSS端子之間的第一電阻器…及 第一二極體D1。第一參考電壓HVREF之預定電壓位準可 基於所設計之第一電阻器R1及第一二極體D1之大小而改 變，如稍後將描述。 電壓比較器614比較第一參考電壓HVREF與外部參考電 壓VREF以輸出比較結果。若第一參考電壓HVREf高於外 137511.doc • 11 - 201011773 部參考電壓VREF，則電壓比較器614輸出比較結果為邏輯 '高，，且若第一參考電壓HVREF低於外部參考電壓vref， 則其輸出比較結果為邏輯'低'。 偵測信號輸出部分616輸出電壓比較器614之比較結果作 為第一偵測信號DET—HVDD。偵測信號輸出部分616中所 提供之轉移閘起作用以使自第二偵測信號產生器63〇所產As can be seen from the figure, in the condition of (B) of FIG. 3, the external power supply voltage VDD has a lower voltage level, so that the pull-up pre-drive unit 132 and the pull-down pre-driver unit 7L 134 turn on the main drive unit 136/ The disconnection time point is slower, so the slew rate of the output data signal DOUT_L becomes smaller. That is, the slope of the output data signal DOUT-L becomes smaller than the slope of DOUT_M in (A) of Fig. 3. Conversely, in Fig. 3 (the external power supply voltage VDD has a relatively high voltage level), the on/off time point of the main drive unit 丨36 becomes faster. Because A, the output data signal D〇 The conversion rate of UT_H becomes larger. That is, the slope of the output data signal D〇UT_H becomes greater than the slope of 圈1; 丁_^4 in (A) of the circle "3. In the conditions of (B) and (c) of Figure 3, the slew rate of the output data signal varies depending on the voltage level of the external power supply voltage VDD. In general, 137511.doc 201011773 because the output data signal conversion rate and data reliability The relationship between the performance and the power consumption is preferably designed in such a manner that the conversion rate should be properly maintained based on data reliability and power consumption. However, the conditions described in (B) and (C) of FIG. 3 do not maintain the conversion rate. 4A and 4B are views for explaining the current characteristics according to the external power supply VDD of the main driving unit 130 in Fig. 1. That is, Fig. 4A shows the current consumed by the main driving unit 13〇 during the pull-down operation 'month. Characteristic and Figure 4b shows φ during pull-up operation The characteristics of the current consumed by the main drive unit 130. In the mother of Figures A and 4B, the two characteristic lines 1 respectively indicate the lower limit and the upper limit of the current to be erased, which are defined according to the specification. The external power supply voltage VDD is higher than the target voltage level, and the characteristic line 3 indicates the condition that the external power supply voltage VDD has the target voltage level. The characteristic line 4 indicates the condition that the external power supply voltage VDD is lower than the target voltage level. 4A and 4B can be seen that the current consumed by the household does not meet the specification of the voltage level of the external power supply. • As described above, depending on the voltage level of the external power supply voltage VDD, the typical data input driver 11 and data The output driver 13 has different operational characteristics. This does not ensure that the data exchange operation between the data input driver 110 and the CPU and the output driver 13 is sufficiently reliable - in addition, because the current consumed is present in Out of the scope defined in the specification, the mass production of the product can be reduced and the compatibility can be reduced. That is, if the manufactured product does not meet the regulations Then, it is handled as a defective product, thereby reducing the efficiency of mass production. For example, it is assumed that there is an environment in which the external power supply voltage VDD of 137511.doc 201011773 and the external power supply voltage vdd of 1.5 V are used. If the one does not satisfy the specification, the compatibility can be reduced by 0. [Invention] An embodiment of the present invention is directed to providing a driving current capable of controlling input and output circuits according to a voltage level of an external power supply voltage. A semiconductor device is provided. Another embodiment of the present invention is directed to providing a material capable of ensuring that input to an input and output circuit or output from an input and output circuit can reliably have the same operational characteristics regardless of an external power supply voltage. Semiconductor memory device. According to an aspect of the present invention, a semiconductor memory device includes: a data input driver and a data output driver for receiving an external power supply voltage 'and for inputting and outputting data, respectively; and a voltage detection The device is configured to detect an external power supply voltage to generate a detection signal, wherein a driving current of each of the data input driver and the data output driver is controlled by the detection signal. According to an aspect of the present invention, a read drive circuit for use in a semiconductor memory device is provided. The read drive circuit includes: a pre-drive unit for generating a drive control signal corresponding to internal data; a driving unit for supplying output data corresponding to the internal data to the output terminal thereof in response to the driving control signal; and an electric (four) measuring device for integrating the external power supply dust to generate a detection signal for controlling The drive current of each of the pre-drive unit and the main drive unit. 137511.doc 201011773 According to an aspect of the present invention, a method for driving a semiconductor memory device includes: detecting a voltage level of an external power supply voltage; and if the external power supply voltage is higher than a target voltage level based on the detection result And performing an input/output operation of the data by a driving current smaller than a driving current corresponding to the external power supply voltage; and if the external power supply voltage is lower than the target voltage level based on the detection result, by being greater than the corresponding external power supply voltage The drive current of the drive current performs data input/output operations. The present invention detects the voltage level of the external power supply voltage and controls the drive current of the input and output circuits in the semiconductor memory device based on the detected voltage level so that the input and output circuits can always have the same operational characteristics. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail hereinafter with reference to the accompanying drawings. Figure 5 is a block diagram illustrating a partial configuration for explaining a semiconductor memory device in accordance with an embodiment of the present invention. Referring to FIG. 5, the semiconductor memory device includes a voltage detector 5, a data input driver 530, a data output driver 55, and an input/output pad 570. The voltage detector 5 10 detects the external power supply voltage vdD. The voltage level generates a first detection signal DET-HVDD and a second detection signal DET_LVDD in response to the external power supply voltage VDD and the external reference voltage VREF. The external reference voltage VREF is a voltage supplied from the outside and has, for example, applied to The external power supply voltage VDD of the semiconductor memory device is 1 / 2 level. The data input driver 530 receives the input data 137511.doc •10-201011773 k DIN from the input/output pad 570 to generate an internal data signal DΑΤ—ΙΝΝ, and the data output driver 550 obtains the data signals DAT_PU and DAT_PD to be output for generation. The output data signal D〇UT is output to the input/output pad 570. Here, the 'data input driver 530 and the data output driver 550 receive the external power supply voltage VDD ' and the driving current of the data input driver 530 and the driving current of the data output driver 550 can be responsive to the first extracted signal DET-HVDD and described later. The second detection signal DETJLVDD is controlled. Figure 6 is a detailed circuit diagram illustrating the voltage detector 5 1 展示 shown in Figure 5. Referring to FIG. 6, the voltage detector 510 includes a first debt signal generator 610 and a second detection signal generator 630 for generating a first price signal DET-HVDD and a second detection signal DETJLVDD, respectively. The first detection signal generator 610 is configured to detect the voltage level of the external power supply voltage VDD to generate the first detection signal DET_HVDD, and has a voltage divider 612, a voltage comparator 614, and a detection signal output portion 61. The voltage divider 612 is configured to divide the external power supply voltage VDD to generate a first reference voltage HVREF having a predetermined voltage level, and has a first resistor coupled between the external power supply voltage VDD terminal and the ground voltage VSS terminal. A diode D1. The predetermined voltage level of the first reference voltage HVREF may be changed based on the size of the designed first resistor R1 and the first diode D1, as will be described later. The voltage comparator 614 compares the first reference voltage HVREF with the external reference voltage VREF to output a comparison result. If the first reference voltage HVREf is higher than the external reference voltage VREF, the voltage comparator 614 outputs a comparison result of logic 'high, and if the first reference voltage HVREF is lower than the external reference voltage vref, Its output comparison result is logical 'low'. The comparison result of the output signal comparator 614 of the detection signal output portion 616 is taken as the first detection signal DET_HVDD. The transfer gate provided in the detection signal output portion 616 functions to be produced from the second detection signal generator 63.

❹ 生之第二偵測信號DET_LVDD的輸出時間與第一偵測信號 DET—HVDD之輸出時間同步。 同時，第二偵測信號產生器63〇具有與第一偵測信號產 生器610類似之組態，且因此，此處將省略其詳細描述。 ，二而，較佳以第一谓測信號產生器61 〇中之第一電阻器尺1 及第一極體D1具有與第二偵測信號產生器63〇中之第二 電阻器R2及第二二極體⑴的大小不同之大小的方式來設 計。亦即，回應於外部電源電壓VDD,自第一偵測信號產 生器610所產生之第一參考電壓η vref及來自第二偵測信 號產生器630之第二參考電壓LVREF應具有預定電壓位 準在實施例中，較佳設計第一參考電壓HVREF可具有高 於第一參考電壓LVREF之電壓位準。 圖7為用於解釋圖6中之電壓偵測器51〇之操作的波形 圖，其展示外部參考電壓VREF、第一參考電壓HVREF及 第一參考電壓LVREF，以及第一偵測信號DET_HVDD及第 债測L號DET_LVDD。此處，外部參考電壓vref可具 有外部電源電壓VDD之1/2位準，如上所提。 如圖7所展示，可藉由將外部參考電壓VREF、第一參考 137511.doc -12- 201011773 電壓HVREF及第二參考電壓LVREF劃分為三個狀況之時間 間隔來解釋外部參考電壓VREF與第一參考電壓HVREF及 第二參考電壓LVREF之間的關係，如下。 第一時間間隔①為在外部參考電壓VREF之電壓位準低 於第一參考電壓HVREF及第二參考電壓LVREF之電壓位準 時的時間間隔，且第二時間間隔②為在外部參考電壓 VREF之電壓位準低於第一參考電壓HVREF之電壓位準但 高於第二參考電壓LVREF之電壓位準時的時間間隔。第三 時間間隔③為在外部參考電壓VREF之電壓位準高於第一 參考電壓HVREF及第二參考電壓LVREF之電壓位準時的時 間間隔。僅供參考，規範中所界定之目標電壓位準可對應 於第一參考電壓HVREF與第二參考電壓LVREF之間的時間 間隔。 在第一時間間隔①之狀況中，第一偵測信號DET_HVDD 變為邏輯’低'，且第二偵測信號DET_LVDD變為邏輯'高“ 在第二時間間隔②之狀況中，第一偵測信號DET_HVDD及 第二偵測信號DET—LVDD兩者均變為邏輯，低，。且在第三 時間間隔③之狀況中，第一偵測信號DET_HVDD變為邏輯’ 高，，且第二偵測信號DET—LVDD變為邏輯，低，。 圖8為說明圖5中所展示之資料輸入驅動器530的詳細電 路圖。 參看圖8，資料輸入驅動器530具備輸入部分810、輸入 驅動電流控制器830、緩衝部分850及輸入控制信號產生器 870 ° 137511.doc 13- 201011773 輸入部分810用於接收輸入資料信號DIN且比較外部參 考電壓VREF與輸入資料信號DIN以產生比較結果。舉例而 言，若輸入資料信號DIN之電壓位準高於外部參考電壓 VREF，則輸入部分810輸出對應於邏輯’低，之電壓位準， 且若輸入資料信號DIN之電壓位準低於外部參考電壓 VREF，則其輸出對應於邏輯•高|之電壓位準。 輸入驅動電流控制器830用以回應於第一至第三輸入控 制信號CTR1_IN、CTR2_IN及CTR3_IN而控制輸入部分81〇 之驅動電流，且具備第一至第三NMOS電晶體NM1、NM2 及NM3，該等NMOS電晶體具有建立於輸入部分810與接地 電壓VSS端子之間的源極-汲極路徑且分別接收第一至第三 輸入控制信號CTR1_IN、CTR2_IN及CTR3_IN。 緩衝部分850用於緩衝輸入部分810之輸出信號以產生内 部資料信號dat_inn。 輸入控制信號產生器870用以回應於第一偵測信號 DET_HVDD及第二偵測信號DET_LVDD而產生第一至第三 輸入控制信號CTR1_IN、CTR2_IN及CTR3_IN，且具備第 一至第三輸入控制信號產生器872、874及876。 第一輸入控制信號產生器872回應於啟動信號EN而產生 第一輸入控制信號CTR1_IN。此處，啟動信號EN用以啟動 資料至輸入部分之輸入操作。舉例而言，啟動信號為在半 導體記憶體裝置之寫入操作後即啟動之信號。第二輸入控 制信號產生器874回應於啟動信號EN及第一偵測信號 DET HVDD而產生第二輸入控制信號CTR2_IN，且第三輸 137511.doc -14- 201011773 入控制信號產生器876回應於啟動信號ΕΝ及第二偵測信號 DET_LVDD而產生第三輸入控制信號CTR3—IN。 首先，將簡單地描述輸入控制信號產生器870之操作。 當啟動信號EN經啟動時，第一輸入控制信號CTR1_IN經啟 動，且當第一偵測信號DET_HVDD經啟動時，第二輸入控 制信號CTR2_IN回應於啟動信號EN而啟動。且當第二偵測 信號DETJLVDD經啟動時，第三輸入控制信號CTR3_IN回 應於啟動信號EN而啟動。亦即，在輸入部分810經啟動時 之時間間隔中，輸入控制信號產生器870可啟動第一至第 三輸入控制信號CTR1_IN、CTR2_IN及CTR3_IN。 再次參看圖7及圖8，在第一時間間隔①之狀況中，第一 至第三輸入控制信號CTR1_IN、CTR2_IN及CTR3_IN全部 經啟動，使得第一至第三NMOS電晶體NM1、NM2及NM3 可全部接通。換言之，在半導體記憶體裝置使用相對低之 外部電源電壓VDD之狀況中，亦即，在半導體記憶體裝置 接收低於目標電壓位準之外部電源電壓VDD的狀況中，資 料輸入驅動器530可具有對應於第一至第三NMOS電晶體 NM1、NM2及NM3之驅動電流。 在第二時間間隔②之狀況中，第一輸入控制信號 CTR1_IN及第二輸入控制信號CTR2_IN經啟動且第三輸入 控制信號CTR3_IN經撤銷，使得第一 NMOS電晶體NM1及 第二NMOS電晶體NM2可接通。亦即，在半導體記憶體裝 置接收與目標電壓位準相等之外部電源電壓VDD之狀況 中，資料輸入驅動器530可具有對應於第一NMOS電晶體 137511.doc • 15· 201011773 NM1及第二NMOS電晶體NM2之驅動電流。 在第三時間間隔③之狀況中，僅第一輸入控制信號 CTR1 一IN經啟動且第二輸入控制信號ctR2_IN及第三輸入 控制信號CTR3_IN經撤銷，使得僅第一NMOS電晶體NM1 可接通。換言之’在半導體記憶體裝置接收高於目標電壓 位準之外部電源電壓VDD之狀況中，資料輸入驅動器530 可具有對應於第一 NMOS電晶體NM1之驅動電流。 因為本發明之資料輸入驅動器530可視外部電源電壓 VDD之電壓位準而控制驅動電流，所以内部資料信號 DAT_INN可始終具有松同特性β亦即，通常，如圖2a、 圖2Β及圖2C中所展示之狀況視外部電源電壓vdd之電壓 位準的改變而發生。然而’在本發明中，因為資料輸入驅 動器530之驅動電流由外部電源電壓vdd控制，所以儘管 外部電源電壓VDD之電壓位準如圖2B及圖2C之狀況中而 改變’但内部資料信號DATJNN可始終具有如圖2A之狀 況中之5 0:5 0的作用時間比率。 圖9為說明圖5中所展示之資料輸出驅動器55〇中之預驅 動單元的詳細電路圖。僅供參考，資料輸出驅動器55〇包 括預驅動單元及主驅動單元，其中下文將參看圖1〇詳細描 述主驅動單元。 參看圖9’預驅動單元具備上拉預驅動器91〇、下拉預驅 動器930、上拉預驅動電流控制器95〇、下拉預驅動電流控 制器970及預控制信號產生器990。 上拉預驅動器910用以回應於上拉資料信號DAT_pu而產 137511.doc -16- 201011773 生上拉驅動控制信號CTR_PU，且具備第一 PMOS電晶體 PM1及第一 NMOS電晶體NM1，該第一 PM0S電晶體PM1及 該第一 NMOS電晶體NM1之源極-汲極路徑建立於外部電源 電壓VDD端子與接地電壓VSS端子之間且該第一 PM0S電 晶體PM1及該第一 NMOS電晶體NM1之閘極接收上拉資料 信號DAT_PU。此外，下拉預驅動器930用以回應於下拉資 料信號DAT_PD而產生下拉驅動控制信號CTR_PD。下拉預 驅動器930之電路組態與上拉預驅動器910之電路組態類 似，除了其接收下拉資料信號DAT_PD而非輸入至上拉預 驅動器910之上拉資料信號DAT_UP且輸出下拉驅動控制信 號CTR_PD而非上拉驅動控制信號CTR_PU。因此，此處將 省略對其之詳細描述。 上拉預驅動電流控制器950回應於第一預控制信號 CTR1_PRE、/CTR1_PRE 及第二預控制信號 CTR2_PRE、 /CTR2_PRE以及上拉資料信號DAT_PU而產生上拉驅動控 制信號CTR_PU，且其可具備第一上拉預驅動電流控制器 952及第二上拉預驅動電流控制器954。 第一上拉預驅動電流控制器952具備：第二PMOS電晶體 PM2及第三PMOS電晶體PM3，第二PMOS電晶體PM2及第 三PMOS電晶體PM3之源極-汲極路徑形成於外部電源電壓 VDD端子與上拉驅動控制信號CTR_PU輸出端子（此處，為 解釋方便起見，省略穿過上拉驅動控制信號CTR_PU之電 阻器）之間且第二PMOS電晶體PM2及第三PMOS電晶體PM3 之閘極分別獲得第一正預控制信號CTR1_PRE及上拉資料 137511.doc -17- 201011773 信號DAT_PU ;及第二NMOS電晶體NM2及第三NMOS電晶 體NM3，第二NMOS電晶體NM2及第三NMOS電晶體NM3 之源極-汲極路徑配置於上拉驅動控制信號CTR_PU輸出端 子與接地電壓VSS端子之間且第二NMOS電晶體NM2及第 三NMOS電晶體NM3之閘極分別接收第一負預控制信號 /CTR1_PRE及上拉資料信號DAT_PU。此處，將在稍後描 述預控制信號產生器990時提供第一正/負預控制信號 CTR1—PRE及/CTR1_PRE之細節。 第二上拉預驅動電流控制器954具備：第四PMOS電晶體 PM4及第五PMOS電晶體PM5，第四PMOS電晶體PM4及第 五PMOS電晶體PM5之源極-汲極路徑建立於外部電源電壓 VDD端子與接地電壓VSS端子之間且第四PMOS電晶體PM4 及第五PMOS電晶體PM5之閘極分別獲得第二負預控制信 號/CTR2_PRE及上拉資料信號DAT_PU ;及第四NMOS電晶 體NM4及第五NMOS電晶體NM5，第四NMOS電晶體NM4 及第五NMOS電晶體NM5之閘極分別接收第二正預控制信 號CTR2_PRE及下拉資料信號DAT_PD。此處，將在稍後描 述預控制信號產生器990時提供第二正/負預控制信號 CTR2_PRE及/CTR2_PRE之細節。 下拉預驅動電流控制器970用以回應於第一預控制信號 CTR1PRE、/CTR1_PRE 及第二預控制信號 CTR2_PRE、 /CTR2—PRE以及下拉資料信號DAT—PD而產生下拉驅動控 制信號CTR_PD »因為下拉預驅動電流控制器970之電路組 態與上拉預驅動電流控制器950之電路組態類似，除了其 137511.doc -18- 201011773 接收下拉資料信號DAT_PD而非輸入至上拉預驅動電流控 制器950之上拉資料信號DAT_UP且輸出下拉驅動控制信號 CTR—PD而非上拉驅動控制信號CTR—PU。因此，此處將省 略對其之詳細描述。 此處，因為上拉預驅動電流控制器950及下拉預驅動電 流控制器970分別接收上拉資料信號DAT_PU及下拉資料信 號DAT_PD，所以上拉預驅動電流控制器950在上拉預驅動 器910經啟動時之時間間隔期間操作，且下拉預驅動電流 控制器970在下拉預驅動器930經啟動時之時間間隔期間操 作。 同時，預控制信號產生器990用於回應於第一偵測信號 DETJHVDD及第二偵測信號DET_LVDD而產生第一負預控 制信號/CTR1_PRE及第二負預控制信號CTR1_PRE，且具 備第一預控制信號產生器992及第二預控制信號產生器 994。此處，第一偵測信號DET_HVDD可為如上所提之第 一正預控制信號CTR1__PRE且第二偵測信號DET_LVDD可 為第二正預控制信號CTR2_PRE。又，第一負預控制信號 /CTR1_PRE可為第一正預控制信號CTR1_PRE之反信號且 第二負預控制信號/CTR2_PRE可為第二正預控制信號 CTR2_PRE之反信號。 下文中，將簡單地描述預驅動單元之操作。為解釋方便 起見，將參看圖7及圖9代表性地描述上拉預驅動器950。 如圖7所展示，在第一時間間隔①之狀況中’亦即’在 半導體記憶體裝置接收低於目標電壓位準之外部電源電壓 137511.doc -19- 201011773 VDD之狀況中，第一正預控制信號CTR1_PRE變為邏輯'低·， 且第二正預控制信號CTR2_PRE變為邏輯'高'。又，第一負 預控制信號/CTR1_PRE變為邏輯’高•，且第二負預控制信 號/CTR2—PRE變為邏輯'低'。由於此，第一上拉預驅動電 流控制器952之第二PMOS電晶體PM2及第二NMOS電晶體 NM2接通，且第二上拉預驅動電流控制器954之第四PMOS 電晶體PM4及第四NMOS電晶體NM4接通》此時，當施加 上拉資料信號DAT_PU時，上拉預驅動器910以及第一上拉 預驅動電流控制器952及第二上拉預驅動電流控制器954經 啟動，使得上拉驅動控制信號CTR_PU可產生對應驅動電 流。 在第二時間間隔②之狀況中，亦即，在半導體記憶體裝 置接收與目標電壓位準相等之外部電源電壓VDD的狀況 中，第一上拉預驅動電流控制器952之第二PMOS電晶體 PM2及第二NMOS電晶體NM2經接通，且第二上拉預驅動 電流控制器954之第四PMOS電晶體PM4及第四NMOS電晶 體NM4斷開。結果，上拉驅動控制信號CTR_pu可引起對 應於上拉預驅動器910及第一上拉預驅動電流控制器952之 驅動電流的產生。 在第三種狀況③中，亦即，在半導艎記憶體裝置接收高 於目標電壓位準之外部電源電壓VDD之狀況中，因為第一 上拉預驅動電流控制器952及第二上拉預驅動電流控制器 954全部經撤銷，所以上拉驅動控制信號CTR_PU可引起對 應於上拉預驅動器910之驅動電流的產生。 137511.doc •20- 201011773 本發明之預驅動單元可視外部電源電壓VDD之電壓位準 而控制驅動電流，且由此，上拉驅動控制信號CTRpu& 下拉驅動控制信號CTR_PD可始終具有相同特性。亦即， 通电如圖3之（A)至（C)中所示之狀況視外部電源電壓 VDD之電壓位準的改變而發生。然❿，根據本發明，因為 預驅動單元之驅動電流由外部電源電壓控制，所以主驅動 單7L(回應於上拉驅動控制信號CTR—pu及下拉驅動控制信 號CTR一PD而判定其接通/斷開時間點）可產生具有如圖3之 (A)中所示之特性的輸出資料信號d〇ut。 圖10為說明圖5中所展示之資料輸出驅動器55〇中之主驅 動單元的詳細電路圖。 參看圖10，主驅動單元具僙上拉主驅動器1〇1〇、下拉主 驅動器1020、上拉主驅動電流控制器1〇3〇、下拉主驅動電 流控制器1040、上拉主控制信號產生器1〇5〇及下拉主控制 信號產生器1060。 上拉主驅動器1010用於回應於上拉驅動控制信號 CTR—PU而驅動輸出一輸出資料信號d〇ut之輸出端子，且 具備第一 PMOS電晶體PM1，該第一 pm〇S電晶體PMl之源 極-汲極路徑建立於外部電源電壓VDD端子與輸出端子之 間且該第一 PMOS電晶體PM1之閘極接收第一上拉主控制 信號CTR1一MN—PU，其中為解釋方便起見，省略耦接於第 一 PMOS電晶體PM 1與輸出端子之間的電阻器。 下拉主驅動器1020用於回應於下拉驅動控制信號 CTR_PD而驅動輸出該輸出資料信號D〇UT之輸出端子且 137511.doc •21 - 201011773 具備第一 NMOS電晶體NMl，該第一 NMOS電晶體NM1之 源極-汲極路徑配置於輸出端子與接地電壓VSS端子之間且 該第一 NMOS電晶體NM1之閘極獲得第一下拉主控制信號 CTR1_MN_PD。 上拉主驅動器103 0用於回應於第二上拉主控制信號 CTR2_MN_PU及第三上拉主控制信號CTR3_MN_PU而驅動 輸出該輸出資料信號DOUT之輸出端子，且具備第二PMOS 電晶體PM2及第三PMOS電晶體PM3，該第二PMOS電晶體 PM2及第三PMOS電晶體PM3之源極-汲極路徑建立於外 部電源電壓VDD端子與輸出端子之間且該第二PMOS電 晶體PM2及第三PMOS電晶體PM3之閘極分別接收第二上 拉主控制信號CTR2_MN_PU及第三上拉主控制信號 CTR3_MN_PU。 下拉主驅動器1040用於回應於第二下拉主控制信號 CTR2_MN_PD及第三下拉主控制信號CTR3_MN_PD而驅動 輸出該輸出資料信號DOUT之輸出端子，且具備第二 NMOS電晶體NM2及第三NMOS電晶體NM3，該第二NMOS 電晶體NM2及第三NMOS電晶體NM3之源極-汲極路徑建 立於輸出端子與接地電壓VSS端子之間且該第二NMOS 電晶體NM2及第三NMOS電晶體NM3之閘極接收第二下 拉主控制信號CTR2_MN_PD及第三下拉主控制信號 CTR3_MN_PD。 上拉主控制信號產生器1050用以回應於上拉驅動控制 信號CTR_PU以及第一偵測信號DET_HVDD及第二偵測 137511.doc -22- 201011773 信號DET_LVDD而產生第一至第三上拉主控制信號 CTR1_MN_PU、CTR2_MN_PU及 CTR3_MN_PU，且具備第 一至第三上拉主控制信號產生器1052、1054及1056。 第一上拉主控制信號產生器1052可回應於上拉驅動控制 信號CTR_PU而產生第一上拉主控制信號CTR1_MN_PU， 第二上拉主控制信號產生器1054可回應於上拉驅動控制信 號CTR—PU及第一偵測信號DET 一 HVDD而產生第二上拉主 控制信號CTR2_MN_PU，且第三上拉主控制信號產生器 1056可回應於上拉驅動控制信號CTR_PU及第二偵測信號 DET_LVDD而產生第三上拉主控制信號CTR3_MN_PU。 首先，將簡單地描述上拉主控制信號產生器1050之操 作。回應於上拉驅動控制信號CTR_PU，第一上拉主控制 信號CTR1_MN_PU經啟動。當第一偵測信號DET經啟動 時，第二上拉主控制信號CTR2_MN_PU回應於上拉驅動控 制信號CTR_PU而啟動。且當第二偵測信號DET—LVDD經 啟動時，第三上拉主控制信號CTR3_MN_PU回應於上拉驅 動控制信號CTR_PU而啟動。亦即，在上拉主驅動器1010 回應於上拉驅動控制信號CTR_PU而啟動時之時間間隔期 間，上拉主控制信號產生器1050可啟動第一至第三主控制 信號 CTR1 _MN_PU、CTR2_MN_PU及 CTR3_MN_PU。 同時，當與上拉主控制信號產生器1050相比較時，下 拉主控制信號產生器1060接收下拉驅動控制信號 CTR—PD而非上拉驅動控制信號CTR—PU，且輸出第一至 第三下拉主控制信號CTR1_MN_PD、CTR2_MN_PD及 137511.doc •23· 201011773 CTR3_MN_PD而非第一至第三上拉主控制信號 CTR1_MN_PU、CTR2_MN_PU及 CTR3_MN_PU » 因此’此 處將省略其電路組態與操作之詳細描述。 下文中，將參看圖7至圖10描述主驅動單元之簡單電路 操作。為解釋方便起見，將參考上拉驅動控制信號 CTR_PU經啟動至邏輯'低'之狀況。對於資訊，因為在彼時 下拉驅動控制信號CTR_PD變為邏輯•低•，所以第一至第三 下拉主控制信號CTR1_MN_PD、CTR2_MN_PD及 β CTR3_MN_PD將全部撤銷至邏輯'低'。 如圖7中所展示，在第一時間間隔①之狀況中，亦即， 在半導體記憶體裝置接收低於目標電壓位準之外部電源電 壓VDD之狀況中，第一上拉主控制信號CTR1_MN_PU回應 於上拉驅動控制信號CTR_PU而變為邏輯•低1。此時，第二 上拉主控制信號CTR2_MN_PD及第三上拉主控制信號 CTR3_MN_PD變為邏輯•低％亦即，上拉主驅動器1010之 _ 第一 PMOS電晶體PM1以及上拉主驅動電流控制器1030之The output time of the second detection signal DET_LVDD is synchronized with the output time of the first detection signal DET_HVDD. Meanwhile, the second detection signal generator 63A has a configuration similar to that of the first detection signal generator 610, and thus, a detailed description thereof will be omitted herein. Preferably, the first resistor scale 1 and the first pole body D1 of the first preamble signal generator 61 have a second resistor R2 and the second of the second detection signal generator 63 The size of the diode (1) is designed to be different in size. That is, in response to the external power supply voltage VDD, the first reference voltage η vref generated from the first detection signal generator 610 and the second reference voltage LVREF from the second detection signal generator 630 should have a predetermined voltage level. In an embodiment, the first reference voltage HVREF is preferably designed to have a voltage level higher than the first reference voltage LVREF. 7 is a waveform diagram for explaining the operation of the voltage detector 51 in FIG. 6, showing an external reference voltage VREF, a first reference voltage HVREF and a first reference voltage LVREF, and a first detection signal DET_HVDD and a Debt measurement L number DET_LVDD. Here, the external reference voltage vref may have a 1/2 level of the external power supply voltage VDD, as mentioned above. As shown in FIG. 7, the external reference voltage VREF and the first one can be interpreted by dividing the external reference voltage VREF, the first reference 137511.doc -12-201011773 voltage HVREF, and the second reference voltage LVREF into time intervals of three conditions. The relationship between the reference voltage HVREF and the second reference voltage LVREF is as follows. The first time interval 1 is a time interval when the voltage level of the external reference voltage VREF is lower than the voltage level of the first reference voltage HVREF and the second reference voltage LVREF, and the second time interval 2 is the voltage at the external reference voltage VREF. The time interval when the level is lower than the voltage level of the first reference voltage HVREF but higher than the voltage level of the second reference voltage LVREF. The third time interval 3 is a time interval when the voltage level of the external reference voltage VREF is higher than the voltage levels of the first reference voltage HVREF and the second reference voltage LVREF. For reference only, the target voltage level defined in the specification may correspond to a time interval between the first reference voltage HVREF and the second reference voltage LVREF. In the first time interval 1, the first detection signal DET_HVDD becomes logic 'low', and the second detection signal DET_LVDD becomes logic 'high'. In the second time interval 2, the first detection The signal DET_HVDD and the second detection signal DET_LVDD both become logic, low, and in the third time interval 3, the first detection signal DET_HVDD becomes logic 'high, and the second detection The signal DET_LVDD becomes logic, low.Figure 8 is a detailed circuit diagram illustrating the data input driver 530 shown in Figure 5. Referring to Figure 8, the data input driver 530 is provided with an input portion 810, an input drive current controller 830, and a buffer. Section 850 and input control signal generator 870 ° 137511.doc 13- 201011773 The input portion 810 is configured to receive the input data signal DIN and compare the external reference voltage VREF with the input data signal DIN to generate a comparison result. For example, if the input data signal is input If the voltage level of DIN is higher than the external reference voltage VREF, the input portion 810 outputs a voltage level corresponding to the logic 'low, and if the voltage level of the input data signal DIN is lower than The reference voltage VREF is output corresponding to the voltage level of the logic • high. The input driving current controller 830 controls the driving of the input portion 81 in response to the first to third input control signals CTR1_IN, CTR2_IN and CTR3_IN. Current, and having first to third NMOS transistors NM1, NM2, and NM3 having source-drain paths established between the input portion 810 and the ground voltage VSS terminal and receiving the first to the first The three input control signals CTR1_IN, CTR2_IN and CTR3_IN are used to buffer the output signal of the input portion 810 to generate an internal data signal dat_inn. The input control signal generator 870 is responsive to the first detection signal DET_HVDD and the second detection. The first to third input control signals CTR1_IN, CTR2_IN, and CTR3_IN are generated by the signal DET_LVDD, and the first to third input control signal generators 872, 874, and 876 are provided. The first input control signal generator 872 is responsive to the enable signal EN. A first input control signal CTR1_IN is generated. Here, the enable signal EN is used to initiate an input operation of the data to the input portion. The start signal is a signal that is activated after a write operation of the semiconductor memory device. The second input control signal generator 874 generates a second input control signal CTR2_IN in response to the enable signal EN and the first detection signal DET HVDD, and The three-input 137511.doc -14- 201011773 incoming control signal generator 876 generates a third input control signal CTR3-IN in response to the enable signal ΕΝ and the second detection signal DET_LVDD. First, the operation of the input control signal generator 870 will be briefly described. When the enable signal EN is activated, the first input control signal CTR1_IN is activated, and when the first detection signal DET_HVDD is activated, the second input control signal CTR2_IN is activated in response to the enable signal EN. And when the second detection signal DETJLVDD is activated, the third input control signal CTR3_IN is activated in response to the enable signal EN. That is, the input control signal generator 870 can activate the first to third input control signals CTR1_IN, CTR2_IN, and CTR3_IN during the time interval when the input portion 810 is activated. Referring again to FIGS. 7 and 8, in the case of the first time interval 1, the first to third input control signals CTR1_IN, CTR2_IN, and CTR3_IN are all activated, so that the first to third NMOS transistors NM1, NM2, and NM3 can be All turned on. In other words, in the case where the semiconductor memory device uses a relatively low external power supply voltage VDD, that is, in the case where the semiconductor memory device receives the external power supply voltage VDD lower than the target voltage level, the data input driver 530 may have a corresponding Driving currents of the first to third NMOS transistors NM1, NM2, and NM3. In the second time interval 2, the first input control signal CTR1_IN and the second input control signal CTR2_IN are activated and the third input control signal CTR3_IN is cancelled, so that the first NMOS transistor NM1 and the second NMOS transistor NM2 can be Turn on. That is, in the case where the semiconductor memory device receives the external power supply voltage VDD equal to the target voltage level, the data input driver 530 may have a corresponding NMOS transistor 137511.doc • 15· 201011773 NM1 and the second NMOS battery The driving current of the crystal NM2. In the case of the third time interval 3, only the first input control signal CTR1_IN is activated and the second input control signal ctR2_IN and the third input control signal CTR3_IN are deactivated, so that only the first NMOS transistor NM1 can be turned on. In other words, in the case where the semiconductor memory device receives the external power supply voltage VDD higher than the target voltage level, the data input driver 530 may have a drive current corresponding to the first NMOS transistor NM1. Since the data input driver 530 of the present invention can control the driving current according to the voltage level of the external power supply voltage VDD, the internal data signal DAT_INN can always have the same characteristic β, that is, generally, as shown in FIG. 2a, FIG. 2, and FIG. 2C. The condition of the display occurs depending on the change in the voltage level of the external power supply voltage vdd. However, in the present invention, since the driving current of the data input driver 530 is controlled by the external power supply voltage vdd, although the voltage level of the external power supply voltage VDD changes as shown in the conditions of FIG. 2B and FIG. 2C, the internal data signal DATJNN can be There is always a ratio of action time of 50:50 in the situation of Figure 2A. Figure 9 is a detailed circuit diagram illustrating the pre-drive unit in the data output driver 55A shown in Figure 5. For reference only, the data output driver 55 includes a pre-drive unit and a main drive unit, which will be described in detail below with reference to FIG. Referring to Fig. 9', the pre-drive unit is provided with a pull-up pre-driver 91A, a pull-down pre-driver 930, a pull-up pre-drive current controller 95A, a pull-down pre-drive current controller 970, and a pre-control signal generator 990. The pull-up pre-driver 910 is configured to generate a pull-up drive control signal CTR_PU in response to the pull-up data signal DAT_pu, and has a first PMOS transistor PM1 and a first NMOS transistor NM1, the first The source-drain path of the PM0S transistor PM1 and the first NMOS transistor NM1 is established between the external power supply voltage VDD terminal and the ground voltage VSS terminal, and the first PMOS transistor PM1 and the first NMOS transistor NM1 The gate receives the pull-up data signal DAT_PU. In addition, the pull-down pre-driver 930 is operative to generate a pull-down drive control signal CTR_PD in response to the pull-down data signal DAT_PD. The circuit configuration of the pull-down pre-driver 930 is similar to the circuit configuration of the pull-up pre-driver 910 except that it receives the pull-down data signal DAT_PD instead of the pull-up pre-driver 910 and pulls the data signal DAT_UP and outputs the pull-down drive control signal CTR_PD instead of Pull-up drive control signal CTR_PU. Therefore, a detailed description thereof will be omitted herein. The pull-up pre-drive current controller 950 generates a pull-up drive control signal CTR_PU in response to the first pre-control signals CTR1_PRE, /CTR1_PRE and the second pre-control signals CTR2_PRE, /CTR2_PRE, and the pull-up data signal DAT_PU, and may have the first Pull-up pre-drive current controller 952 and second pull-up pre-drive current controller 954. The first pull-up pre-drive current controller 952 includes: a second PMOS transistor PM2 and a third PMOS transistor PM3, and a source-drain path of the second PMOS transistor PM2 and the third PMOS transistor PM3 is formed on the external power source The voltage VDD terminal and the pull-up drive control signal CTR_PU output terminal (here, for convenience of explanation, omitting the resistor passing through the pull-up drive control signal CTR_PU) and the second PMOS transistor PM2 and the third PMOS transistor The gate of PM3 obtains a first positive pre-control signal CTR1_PRE and a pull-up data 137511.doc -17-201011773 signal DAT_PU; and a second NMOS transistor NM2 and a third NMOS transistor NM3, a second NMOS transistor NM2 and a The source-drain path of the three NMOS transistor NM3 is disposed between the pull-up drive control signal CTR_PU output terminal and the ground voltage VSS terminal, and the gates of the second NMOS transistor NM2 and the third NMOS transistor NM3 respectively receive the first Negative pre-control signal /CTR1_PRE and pull-up data signal DAT_PU. Here, details of the first positive/negative pre-control signals CTR1 - PRE and / CTR1_PRE will be provided later when the pre-control signal generator 990 is described. The second pull-up pre-drive current controller 954 includes: a fourth PMOS transistor PM4 and a fifth PMOS transistor PM5, and a source-drain path of the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 is established at an external power source a gate between the voltage VDD terminal and the ground voltage VSS terminal and the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 respectively obtain a second negative pre-control signal /CTR2_PRE and a pull-up data signal DAT_PU; and a fourth NMOS transistor The gates of the NM4 and the fifth NMOS transistor NM5, the fourth NMOS transistor NM4, and the fifth NMOS transistor NM5 receive the second positive pre-control signal CTR2_PRE and the pull-down data signal DAT_PD, respectively. Here, the details of the second positive/negative pre-control signals CTR2_PRE and /CTR2_PRE will be provided later when the pre-control signal generator 990 is described. The pull-down pre-drive current controller 970 is configured to generate a pull-down drive control signal CTR_PD in response to the first pre-control signals CTR1PRE, /CTR1_PRE and the second pre-control signals CTR2_PRE, /CTR2_PRE, and the pull-down data signal DAT_PD. The circuit configuration of the drive current controller 970 is similar to that of the pull-up pre-drive current controller 950 except that its 137511.doc -18-201011773 receives the pull-down data signal DAT_PD instead of the pull-up pre-drive current controller 950. The data signal DAT_UP is pulled up and the pull-down drive control signal CTR_PD is output instead of the pull-up drive control signal CTR-PU. Therefore, a detailed description thereof will be omitted here. Here, since the pull-up pre-drive current controller 950 and the pull-down pre-drive current controller 970 receive the pull-up data signal DAT_PU and the pull-down data signal DAT_PD, respectively, the pull-up pre-drive current controller 950 is activated in the pull-up pre-driver 910. The time interval is operated and the pull-down pre-drive current controller 970 operates during the time interval when the pull-down pre-driver 930 is activated. At the same time, the pre-control signal generator 990 is configured to generate the first negative pre-control signal /CTR1_PRE and the second negative pre-control signal CTR1_PRE in response to the first detection signal DETJHVDD and the second detection signal DET_LVDD, and has the first pre-control Signal generator 992 and second pre-control signal generator 994. Here, the first detection signal DET_HVDD may be the first positive pre-control signal CTR1__PRE as mentioned above and the second detection signal DET_LVDD may be the second positive pre-control signal CTR2_PRE. Also, the first negative pre-control signal /CTR1_PRE may be the inverse of the first positive pre-control signal CTR1_PRE and the second negative pre-control signal /CTR2_PRE may be the inverse of the second positive pre-control signal CTR2_PRE. Hereinafter, the operation of the pre-drive unit will be briefly described. For convenience of explanation, the pull-up pre-driver 950 will be representatively described with reference to FIGS. 7 and 9. As shown in FIG. 7, in the condition of the first time interval 1, 'that is, 'in the condition that the semiconductor memory device receives the external power supply voltage 137511.doc -19-201011773 VDD lower than the target voltage level, the first positive The pre-control signal CTR1_PRE becomes logic 'low·, and the second positive pre-control signal CTR2_PRE becomes logic 'high'. Also, the first negative pre-control signal /CTR1_PRE becomes logic 'HIGH', and the second negative pre-control signal /CTR2_PRE becomes logic 'LOW'. Because of this, the second PMOS transistor PM2 and the second NMOS transistor NM2 of the first pull-up pre-drive current controller 952 are turned on, and the fourth PMOS transistor PM4 and the second pull-up pre-drive current controller 954 are turned on. The four NMOS transistor NM4 is turned on. At this time, when the pull-up data signal DAT_PU is applied, the pull-up pre-driver 910 and the first pull-up pre-drive current controller 952 and the second pull-up pre-drive current controller 954 are activated. The pull-up drive control signal CTR_PU is caused to generate a corresponding drive current. In the case of the second time interval 2, that is, in the case where the semiconductor memory device receives the external power supply voltage VDD equal to the target voltage level, the second PMOS transistor of the first pull-up pre-drive current controller 952 The PM2 and the second NMOS transistor NM2 are turned on, and the fourth PMOS transistor PM4 and the fourth NMOS transistor NM4 of the second pull-up pre-drive current controller 954 are turned off. As a result, the pull-up drive control signal CTR_pu can cause the generation of the drive current corresponding to the pull-up pre-driver 910 and the first pull-up pre-drive current controller 952. In the third condition 3, that is, in the case where the semiconductor memory device receives the external power supply voltage VDD higher than the target voltage level, because the first pull-up pre-drive current controller 952 and the second pull-up The pre-drive current controller 954 is all revoked, so the pull-up drive control signal CTR_PU can cause the generation of the drive current corresponding to the pull-up pre-driver 910. 137511.doc • 20- 201011773 The pre-drive unit of the present invention controls the drive current according to the voltage level of the external power supply voltage VDD, and thus, the pull-up drive control signal CTRpu& pull-down drive control signal CTR_PD can always have the same characteristics. That is, the energization occurs as shown in (A) to (C) of Fig. 3 depending on the change in the voltage level of the external power supply voltage VDD. Then, according to the present invention, since the drive current of the pre-drive unit is controlled by the external power supply voltage, the main drive unit 7L (in response to the pull-up drive control signal CTR_pu and the pull-down drive control signal CTR-PD, determines that it is turned on/ The off time point can produce an output data signal d〇ut having the characteristics as shown in (A) of FIG. Figure 10 is a detailed circuit diagram showing the main driving unit in the data output driver 55A shown in Figure 5. Referring to FIG. 10, the main driving unit has a pull-up main driver 1〇1〇, a pull-down main driver 1020, a pull-up main driving current controller 1〇3〇, a pull-down main driving current controller 1040, and a pull-up main control signal generator. 1〇5〇 and pull down the main control signal generator 1060. The pull-up main driver 1010 is configured to drive an output terminal of the output data signal d〇ut in response to the pull-up driving control signal CTR-PU, and is provided with a first PMOS transistor PM1, and the first pm 电S transistor PM1 The source-drain path is established between the external power supply voltage VDD terminal and the output terminal, and the gate of the first PMOS transistor PM1 receives the first pull-up main control signal CTR1-MN-PU, for convenience of explanation, The resistor coupled between the first PMOS transistor PM 1 and the output terminal is omitted. The pull-down main driver 1020 is configured to drive the output terminal of the output data signal D〇UT in response to the pull-down driving control signal CTR_PD and 137511.doc • 21 - 201011773 is provided with a first NMOS transistor NM1, the first NMOS transistor NM1 The source-drain path is disposed between the output terminal and the ground voltage VSS terminal, and the gate of the first NMOS transistor NM1 obtains the first pull-down main control signal CTR1_MN_PD. The pull-up main driver 103 0 is configured to drive the output terminal of the output data signal DOUT in response to the second pull-up main control signal CTR2_MN_PU and the third pull-up main control signal CTR3_MN_PU, and has a second PMOS transistor PM2 and a third The source-drain path of the PMOS transistor PM3, the second PMOS transistor PM2 and the third PMOS transistor PM3 is established between the external power supply voltage VDD terminal and the output terminal, and the second PMOS transistor PM2 and the third PMOS The gate of the transistor PM3 receives the second pull-up main control signal CTR2_MN_PU and the third pull-up main control signal CTR3_MN_PU, respectively. The pull-down main driver 1040 is configured to drive the output terminal of the output data signal DOUT in response to the second pull-down main control signal CTR2_MN_PD and the third pull-down main control signal CTR3_MN_PD, and is provided with the second NMOS transistor NM2 and the third NMOS transistor NM3. The source-drain path of the second NMOS transistor NM2 and the third NMOS transistor NM3 is established between the output terminal and the ground voltage VSS terminal and the gates of the second NMOS transistor NM2 and the third NMOS transistor NM3 The pole receives the second pull-down main control signal CTR2_MN_PD and the third pull-down main control signal CTR3_MN_PD. The pull-up main control signal generator 1050 is configured to generate first to third pull-up main control in response to the pull-up driving control signal CTR_PU and the first detecting signal DET_HVDD and the second detecting 137511.doc -22-201011773 signal DET_LVDD The signals CTR1_MN_PU, CTR2_MN_PU, and CTR3_MN_PU are provided with first to third pull-up main control signal generators 1052, 1054, and 1056. The first pull-up main control signal generator 1052 may generate a first pull-up main control signal CTR1_MN_PU in response to the pull-up driving control signal CTR_PU, and the second pull-up main control signal generator 1054 may respond to the pull-up driving control signal CTR- The PU and the first detection signal DET-HVDD generate a second pull-up main control signal CTR2_MN_PU, and the third pull-up main control signal generator 1056 is generated in response to the pull-up driving control signal CTR_PU and the second detection signal DET_LVDD. The third pull-up main control signal CTR3_MN_PU. First, the operation of the pull-up main control signal generator 1050 will be briefly described. In response to the pull-up drive control signal CTR_PU, the first pull-up master control signal CTR1_MN_PU is activated. When the first detection signal DET is activated, the second pull-up main control signal CTR2_MN_PU is activated in response to the pull-up drive control signal CTR_PU. And when the second detection signal DET_LVDD is activated, the third pull-up main control signal CTR3_MN_PU is activated in response to the pull-up driving control signal CTR_PU. That is, the pull-up main control signal generator 1050 can activate the first to third main control signals CTR1_MN_PU, CTR2_MN_PU, and CTR3_MN_PU during a time interval when the pull-up main driver 1010 is activated in response to the pull-up driving control signal CTR_PU. Meanwhile, when compared with the pull-up main control signal generator 1050, the pull-down main control signal generator 1060 receives the pull-down drive control signal CTR_PD instead of the pull-up drive control signal CTR-PU, and outputs the first to third pull-downs. Main control signals CTR1_MN_PD, CTR2_MN_PD, and 137511.doc • 23· 201011773 CTR3_MN_PD instead of the first to third pull-up main control signals CTR1_MN_PU, CTR2_MN_PU, and CTR3_MN_PU » Therefore, a detailed description of the circuit configuration and operation thereof will be omitted herein. Hereinafter, a simple circuit operation of the main drive unit will be described with reference to Figs. For convenience of explanation, the pull-up drive control signal CTR_PU is initiated to a logic 'low' condition. For information, the first to third pull-down master control signals CTR1_MN_PD, CTR2_MN_PD, and β CTR3_MN_PD will all be decremented to logic 'low' because at the time the pull-down drive control signal CTR_PD becomes logic low. As shown in FIG. 7, in the condition of the first time interval 1, that is, in the case where the semiconductor memory device receives the external power supply voltage VDD lower than the target voltage level, the first pull-up main control signal CTR1_MN_PU responds It becomes logic•low1 on the pull-up drive control signal CTR_PU. At this time, the second pull-up main control signal CTR2_MN_PD and the third pull-up main control signal CTR3_MN_PD become logic•low%, that is, the first PMOS transistor PM1 of the pull-up main driver 1010 and the pull-up main driving current controller 1030

W 第二PMOS電晶體PM2及第三PMOS電晶體PM3經接通。因 此，輸出該輸出資料信號DOUT之輸出端子可具有對應於 第一至第三PMOS電晶體PM1、PM2及PM3之驅動電流。 在第二時間間隔②之狀況中，亦即，在半導體記憶體裝 置接收與目標電壓位準相等之外部電源電壓VDD的狀況 中，上拉主驅動器1010之第一 PMOS電晶體PM1及上拉主 驅動電流控制器1030之第二PMOS電晶體PM2經接通，且 第三PMOS電晶體PM3斷開。結果，輸出該輸出資料信號 137511.doc -24- 201011773 DOUT之輸出端子可具有對應於第一 PMOS電晶體PM1及第 二PMOS電晶體PM2之驅動電流。 在第三時間間隔③之狀況中，亦即，在半導體記憶體裝 置接收高於目標電壓位準之外部電源電壓VDD之狀況中， 因為上拉主驅動電控制器1 〇3〇經撤銷，所以輸出該輸出 資料信號DOUT之輸出端子可具有對應於第一 pM〇s電晶體 PM1之驅動電流。W second PMOS transistor PM2 and third PMOS transistor PM3 are turned on. Therefore, the output terminal outputting the output data signal DOUT can have drive currents corresponding to the first to third PMOS transistors PM1, PM2, and PM3. In the case of the second time interval 2, that is, in the state where the semiconductor memory device receives the external power supply voltage VDD equal to the target voltage level, the first PMOS transistor PM1 and the pull-up master of the pull-up main driver 1010 are pulled up. The second PMOS transistor PM2 of the drive current controller 1030 is turned on, and the third PMOS transistor PM3 is turned off. As a result, the output terminal of the output data signal 137511.doc -24- 201011773 DOUT may have a drive current corresponding to the first PMOS transistor PM1 and the second PMOS transistor PM2. In the case of the third time interval 3, that is, in the case where the semiconductor memory device receives the external power supply voltage VDD higher than the target voltage level, since the pull-up main drive electric controller 1 〇3 is revoked, The output terminal outputting the output data signal DOUT may have a drive current corresponding to the first pM〇s transistor PM1.

圖11A及圖11B為用於依據圖中之主驅動單元之外部 電源電壓VDD解釋電流特性的視圖。圖UA展示在下拉操 作期間流過輸出資料信號DOUT之輸出端子之電流的特性 且圖11B展示在上拉操作期間流過輸出資料信號D〇UT之輸 出端子之電流的特性。在圖式中，①指示規範中所界定之 消耗電流之上限及下限，②展示外部電源電壓VDD高於目 標電壓位準之狀況，③展示外部電源電壓VDD具有目標電 壓位準之狀況’且④展示外部電源電壓VDD低於目標電麗 位準之狀況。 如自圖11A及圖11B可見，儘管外部電源電壓之電壓位 準變化，但主驅動單元之電流特性可滿足規範。亦即，因 為本發明之主驅動單元可基於外部電源電壓vdd之電麼位 準控制驅動電流，所以流過輸出該輸出資料信號D0UT之 輸出端子的電流可始終具有滿足規範之特性。 如上所提及’根據本發明之半導體記憶趙裝置可 電源電MVDD之錢位準而調整資料輸人㈣H 530(參見 圖”及資料輸出驅動器55。之驅動電流。，亦即，若外部電 137511.doc -25· 201011773 源電壓VDD之電壓位準高於目標電壓位準，則半導體呓憶 體裝置調整驅動電流，使得其具有少於對應於所施加之外 部電源電™之電流量的電流量。且若外部電編 之電壓位準低於目標電壓位準，則半導體記憶體裝置 調整驅動電流，使得其且右客μ @ _ 况付丹八有多於對應於所施加之外部電源 電壓VDD之電流量的電流量。結果，即使存在外部電源電 壓VDD之電壓位準的變化，半導體記憶體裝置亦可始終由 相同驅動電流控制。11A and 11B are views for explaining current characteristics in accordance with the external power supply voltage VDD of the main driving unit in the drawing. Figure UA shows the characteristics of the current flowing through the output terminal of the output data signal DOUT during the pull-down operation and Figure 11B shows the characteristics of the current flowing through the output terminal of the output data signal D〇UT during the pull-up operation. In the figure, 1 indicates the upper and lower limits of the current consumption defined in the specification, 2 shows the condition that the external power supply voltage VDD is higher than the target voltage level, and 3 shows the condition that the external power supply voltage VDD has the target voltage level' and 4 Shows the condition that the external power supply voltage VDD is lower than the target battery level. As can be seen from Fig. 11A and Fig. 11B, although the voltage level of the external power supply voltage changes, the current characteristics of the main drive unit can satisfy the specifications. That is, since the main driving unit of the present invention can control the driving current based on the electric power level of the external power supply voltage vdd, the current flowing through the output terminal outputting the output data signal DOUT can always satisfy the specification. As mentioned above, the semiconductor memory device according to the present invention can adjust the data input level of the power supply MVDD (4) H 530 (see figure) and the data output driver 55. The driving current, that is, if the external power 137511 .doc -25· 201011773 The voltage level of the source voltage VDD is higher than the target voltage level, and the semiconductor memory device adjusts the driving current so that it has less current than the amount of current corresponding to the applied external power supply TM And if the voltage level of the external electric code is lower than the target voltage level, the semiconductor memory device adjusts the driving current so that the right guest μ @ _ 付付丹八有有 corresponds to the applied external power supply voltage VDD The amount of current of the current amount. As a result, even if there is a change in the voltage level of the external power supply voltage VDD, the semiconductor memory device can always be controlled by the same drive current.

因此，儘管存在外部電源電壓VDD之電壓位準的變化， 但有可能執行始終具有恆定特性之輸入/輸出操作。此可 使確保CPU與半導體記憶體裝置之間的資料交換操作之足 夠可靠性成為可能。另夕卜，根據本發明之半導體記憶體裝 置可始終執行滿足規範之操作，其提供高的大量生產及高 相容性》 此外，儘管已借助於實例描述以上實施例，但相對於藉 由使用具有數位特性之第一偵測信號DET_HVDD及第二偵 測信號DET一LVDD而判定外部電源電壓VDD是高於還是低 於目標電壓位準以基於該判定控制驅動電流之狀況，本發 明可應用至藉由使用具有對應於外部電源電壓VDD之電壓 位準之類比特性的偵測信號而非第一偵測信號DET_hvdd 及第二偵測信號DET一LVDD來控制驅動電流的狀況。在此 狀/兄下’當控制資料輸入/輸出驅動器之驅動電流時，較 佳具有驅動電流係基於具有類比特性之偵測信號而調整的 組態。 ^37511.^0) -26 - 201011773 此外’應注意，可基於輸入信號之極性而將上文提及之 實施例中所使用的邏輯閘及電晶體以不同位置配置且以不 同類型實施。 儘管已關於特定實施例描述本發明，但熟習此項技術者 將易瞭解，在不脫離以下申請專利範圍中所界定之本發明 之精神及範疇的情況下，可進行各種改變及修改。 【圖式簡單說明】 圖1為描述典型資料输入驅動器110及資料輸出驅動器 130之電路圖。 圖2A、圖2B及圖2C為用於解釋圖1中所展示之資料輸入 驅動器110之輸入操作的波形圖。 圖3展示用於解釋圖丨中所展示之資料輸出驅動器13〇之 輸出操作的波形。 圖4A及圖4B為依據圖1中之主驅動單元13〇之外部電源 VDD描述電流特性的曲線圖。 _ 圖5為說明用於解釋根據本發明之實施例的半導體記憶 體裝置之部分組態的方塊圖。 圖6為說明圖5中所展示之電壓偵測器5丨〇的詳細電路 圖。 、圖7為用於解釋圖6中所展示之電壓偵測器51〇之操作 波形圖。 圖8為說明圖5中所展示之資料輸入驅動器530之詳細雷 路圖。 τ，田电 圖為說明圖5中所展示之資料輸出驅動器550中之預驅 137511.doc •27· 201011773 動單元的電路圖。 圖10為說明圖5中所孱丨 . 不之資料輸出驅動器550中之主驅 動單元的電路圖。 圖11A及圖11B為依據圖1〇中之主驅動單元之外部電源 電壓VDD展示電流特性的視圖。 【主要元件符號說明】Therefore, although there is a change in the voltage level of the external power supply voltage VDD, it is possible to perform an input/output operation that always has a constant characteristic. This makes it possible to ensure sufficient reliability of the data exchange operation between the CPU and the semiconductor memory device. In addition, the semiconductor memory device according to the present invention can always perform an operation satisfying specifications, which provides high mass production and high compatibility. Further, although the above embodiment has been described by way of example, it has a digital position as compared with The first detecting signal DET_HVDD and the second detecting signal DET_LVDD of the characteristic determine whether the external power supply voltage VDD is higher or lower than the target voltage level to control the driving current based on the determination, and the present invention can be applied to The condition of the drive current is controlled using a detection signal having an analog characteristic corresponding to the voltage level of the external power supply voltage VDD instead of the first detection signal DET_hvdd and the second detection signal DET_LVDD. In this case, when controlling the drive current of the data input/output driver, it is preferable to have a configuration in which the drive current is adjusted based on the detection signal having the analog characteristic. ^37511.^0) -26 - 201011773 Furthermore, it should be noted that the logic gates and transistors used in the above-mentioned embodiments can be configured in different positions and implemented in different types based on the polarity of the input signal. While the invention has been described with respect to the specific embodiments of the present invention, it will be understood that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a typical data input driver 110 and a data output driver 130. 2A, 2B, and 2C are waveform diagrams for explaining an input operation of the data input driver 110 shown in Fig. 1. Fig. 3 shows waveforms for explaining the output operation of the data output driver 13A shown in Fig. 4A and 4B are graphs depicting current characteristics in accordance with the external power supply VDD of the main driving unit 13A of Fig. 1. Fig. 5 is a block diagram showing a part of the configuration for explaining a semiconductor memory device according to an embodiment of the present invention. Figure 6 is a detailed circuit diagram illustrating the voltage detector 5A shown in Figure 5. Fig. 7 is a waveform diagram for explaining the operation of the voltage detector 51 shown in Fig. 6. Figure 8 is a detailed diagram showing the data input driver 530 shown in Figure 5. τ, the field diagram is a circuit diagram illustrating the pre-driver 137511.doc • 27· 201011773 moving unit in the data output driver 550 shown in FIG. Fig. 10 is a circuit diagram showing the main driving unit in the data output driver 550 shown in Fig. 5. 11A and 11B are views showing the current characteristics of the external power supply voltage VDD according to the main driving unit of Fig. 1. [Main component symbol description]

110 資料輸入驅動器 130 資料輸出驅動器 132 上拉預驅動單元 134 下拉預驅動單元 136 主驅動單元 150 輸入/輸出襯墊 510 電壓偵測器 530 資料輸入驅動器 550 資料輸出驅動器 570 輸入/輸出襯墊 610 第一偵測信號產生器 612 分壓器 614 電壓比較器 616 4貞測信號輸出部分 630 第二偵測信號產生器 810 輸入部分 830 輸入驅動電流控制器 850 緩衝部分 137511.doc -28- 201011773 870 輸入控制信號產生器 872 第一輸入控制信號產生器 874 第二輸入控制信號產生器 876 第三輸入控制信號產生器 910 上拉預驅動器 930 下拉預驅動器 950 上拉預驅動電流控制器 952 ® 954 第一上拉預驅動電流控制器 第二上拉預驅動電流控制器 970 下拉預驅動電流控制器 990 預控制信號產生器 992 第一預控制信號產生器 994 第二預控制信號產生器 1010 上拉主驅動器 1020 下拉主驅動器 1030 ❹ 上拉主驅動電流控制器 1040 下拉主驅動電流控制器 1050 上拉主控制信號產生器 1052 1054 第一上拉主控制信號產生器 第二上拉主控制信號產生器 1056 第三上拉主控制信號產生器 1060 下拉主控制信號產生器 CTRPD 下拉驅動控制信號 CTR_PU 上拉驅動控制信號 137511.doc -29· 201011773110 data input driver 130 data output driver 132 pull-up pre-drive unit 134 pull-down pre-drive unit 136 main drive unit 150 input / output pad 510 voltage detector 530 data input driver 550 data output driver 570 input / output pad 610 A detection signal generator 612 voltage divider 614 voltage comparator 616 4 detection signal output portion 630 second detection signal generator 810 input portion 830 input drive current controller 850 buffer portion 137511.doc -28- 201011773 870 input Control signal generator 872 first input control signal generator 874 second input control signal generator 876 third input control signal generator 910 pull-up pre-driver 930 pull-down pre-driver 950 pull-up pre-drive current controller 952 ® 954 first Pull-up pre-drive current controller second pull-up pre-drive current controller 970 pull-down pre-drive current controller 990 pre-control signal generator 992 first pre-control signal generator 994 second pre-control signal generator 1010 pull-up main driver 1020 pull down main drive 1030 ❹ Pull main drive current controller 1040 pull-down main drive current controller 1050 pull-up main control signal generator 1052 1054 first pull-up main control signal generator second pull-up main control signal generator 1056 third pull-up main control signal generation 1060 pull-down main control signal generator CTRPD pull-down drive control signal CTR_PU pull-up drive control signal 137511.doc -29· 201011773

CTR1_IN 第一輸入控制信號 CTR1_MN_PD 第一下拉主控制信號 CTR1—MN_PU 第一上拉主控制信號 CTR1_PRE 第一正預控制信號 /CTR1_PRE 第一負預控制信號 CTR2_IN 第二輸入控制信號 CTR2_MN_PD 第二下拉主控制信號 CTR2_MN_PU 第二上拉主控制信號 CTR2_PRE 第二正預控制信號 /CTR2_PRE 第二負預控制信號 CTR3_IN 第三輸入控制信號 CTR3_MN_PD 第三下拉主控制信號 CTR3_MN_PU 第三上拉主控制信號 D1 第一二極體 D2 第二二極體 DAT_INN 内部資料信號 DAT_INN_H 内部資料信號 DAT_INN_L 内部資料信號 DAT_INN_M 内部資料信號 DAT_PD 下拉資料信號 DAT_PU 上拉資料信號 DET_HVDD 第一偵測信號 DET_LVDD 第二偵測信號 DET_HVDD[CTR1_PRE] 第一偵測信號[第一正預控制 137511.doc -30· 201011773 信號] DET_HVDD[CTR2_PRE]第一偵測信號[第二正預控制 信號] DIN 輸入資料信號 DIN_H 輸入資料信號 DIN_L 輸入資料信號 DIN_M 輸入資料信號 DOUT 輸出資料信號 ❿ DOUT—Η 輸出資料信號 DOUT_L 輸出資料信號 DOUT_M 輸出資料信號 EN 啟動信號 HVREF 第一參考電壓 LVREF 第二參考電壓 NM1 第一 NMOS電晶體 NM2 ❹ 第二NMOS電晶體 NM3 第三NMOS電晶體 NM4 第四NMOS電晶體 • NM5 第五NMOS電晶體 PM1 第一 PMOS電晶體 PM2 第二PMOS電晶體 PM3 第三PMOS電晶體 PM4 第四PMOS電晶體 PM5 第五PMOS電晶體 137511.doc -31 - 201011773 R1 第一電阻器 R2 第二電阻器 VDD 外部電源電壓 VREF 外部參考信號/外部參考電壓 VREF_ _H 外部參考電壓 VREF_ _L 外部參考電壓 VREF_ _M 外部參考電壓 VSS 接地電壓 參 ❹ 137511.doc -32-CTR1_IN first input control signal CTR1_MN_PD first pull-down main control signal CTR1_MN_PU first pull-up main control signal CTR1_PRE first positive pre-control signal /CTR1_PRE first negative pre-control signal CTR2_IN second input control signal CTR2_MN_PD second pull-down main Control signal CTR2_MN_PU Second pull-up main control signal CTR2_PRE Second positive pre-control signal /CTR2_PRE Second negative pre-control signal CTR3_IN Third input control signal CTR3_MN_PD Third pull-down main control signal CTR3_MN_PU Third pull-up main control signal D1 First two Pole body D2 Second diode DAT_INN Internal data signal DAT_INN_H Internal data signal DAT_INN_L Internal data signal DAT_INN_M Internal data signal DAT_PD Pull-down data signal DAT_PU Pull-up data signal DET_HVDD First detection signal DET_LVDD Second detection signal DET_HVDD[CTR1_PRE] A detection signal [first positive pre-control 137511.doc -30· 201011773 signal] DET_HVDD[CTR2_PRE] first detection signal [second positive pre-control signal] DIN input data signal DIN_H input data signal DIN_L input data signal DIN_M Data signal DOUT Output data signal ❿ DOUT—Η Output data signal DOUT_L Output data signal DOUT_M Output data signal EN Start signal HVREF First reference voltage LVREF Second reference voltage NM1 First NMOS transistor NM2 ❹ Second NMOS transistor NM3 Third NMOS transistor NM4 fourth NMOS transistor • NM5 fifth NMOS transistor PM1 first PMOS transistor PM2 second PMOS transistor PM3 third PMOS transistor PM4 fourth PMOS transistor PM5 fifth PMOS transistor 137511.doc - 31 - 201011773 R1 First Resistor R2 Second Resistor VDD External Supply Voltage VREF External Reference Signal / External Reference Voltage VREF_ _H External Reference Voltage VREF_ _L External Reference Voltage VREF_ _M External Reference Voltage VSS Ground Voltage Reference 137511.doc -32 -

Claims (1)

201011773 七、申請專利範圍： 1. 一種用於接收一外部電源電壓之半導體記憶體裴置其 包含： ' 一資料輸入驅動器’其經組態以接收一外部電源電壓 且輸入資料； 一資料輸出驅動器，其經組態以接收一外部電源電壓 * 且輸出資料；及 一電壓偵測器’其經組態以偵測該外部電源電壓，且 參 產生一偵測信號’ 其中一驅動該資料輸入驅動器之輸入驅動電流及一驅 動該資料輸出驅動器之輸出驅動電流由該偵測信號控 制。 2. 如請求項1之半導體記憶體裝置，其中該電壓偵測器包 括： 一分壓器，其經組態以劃分該外部電源電壓，且產生 一具有一預定電壓位準之内部參考電壓； ❹ 一比較器，其經組態以比較該内部參考電壓與該外部 電源電壓；及 • 一輸出部分，其經組態以自該比較器輸出該偵測信 .號。 3. 如請求項1之半導體記憶體裝置，其中該輸入資料驅動 器包括 一輸入部分，其接收輸入資料及該輸入驅動電流；及 一輸入驅動電流控制器，其經組態以基於該偵測信號 137511.doc 201011773 控制該輸入驅動電流。 4. 如請求項3之半導體記憶體裝置，其進一步包含—緩衝 器’該緩衝器經組態以緩衝一來自該輸入部分之輸出信 號’且輪出一經緩衝之信號作為内部資料。 5. 如請求項3之半導體記憶體裝置，其進一步包含—輸入 控制信號產生器，該輸入控制信號產生器經組態以基於 該谓測信號產生一輸入控制信號以控制該輸入驅動電流 控制器。 6. 如請求項5之半導體記憶體裝置，其中該輸入控制信號 產生器在一輸入部分啟動時間間隔期間啟動該輸入控制 信號。 7. 如請求項丨之半導體記憶體裝置，其中該資料輸出驅動 器包括： 一預驅動單元，其經組態以基於待輸出之資料及該偵 測信號控制一預驅動電流，且基於該預驅動電流產生一 0 驅動控制信號；及 一主驅動單元，其經組態以回應於該驅動控制信號及 该偵测信號而控制一主驅動電流，且基於該主驅動電流 •驅動其輸出端子。 8. 如請求項7之半導體記憶體裝置，其中該預驅動單元包 括： 預驅動器，其經組態以基於該待輸出之 驅動控制信號；及 ^ 一預驅動電流控帝，其、經組態以基於待輸出之資料 137511.doc 201011773 及该偵測信號控制該預驅動電流。 9.如請求項8之半導體記憶體裝置，其進一步包含一預控 制心號產生器，該預控制信號產生器經組態以基於該偵 測t號產生一預控制信號以控制該預驅動電流控制器。 〇·如：求項8之半導體記憶體裝置，其中該預驅動電流控 制器在一預驅動器啟動時間間隔期間操作。 Π.如請求項7之半導體記憶體裝置，其中該主驅動單元包 括： 一主驅動器，其經組態以基於該驅動控制信號驅動該 輸出端子；及 一主驅動電流控制器，其經組態以基於該驅動控制信 號及該偵測信號驅動該主驅動電流。 12. 如請求項11之半導體記憶體裝置，其進一步包含一主控 制信號產生器，該主控制信號產生器經組態以基於該驅 動控制仏號及該偵測信號產生一主控制信號以控制該主 驅動電流控制器。 13. 如請求項12之半導體記憶體裝置，其中該主控制信號產 生器在一主驅動器啟動時間間隔期間啟動該主控制信 號。 14· 一種用於一半導體記憶體裝置中之讀取驅動電路，該讀 取驅動電路包含： 一預驅動單元，其經組態以產生一對應於内部資料之 驅動控制信號； 一主驅動單元，其經組態以基於該驅動控制信號將對 137511.doc 201011773 應；"亥内邛資料之輸出資料提供至一主驅動輸出端子；及 一電壓偵測器，其經組態以偵測一外部電源電壓，且 產生—偵測信號，該偵測信號用以控制該預驅動單元之 一預驅動電流及該主驅動單元之一主驅動電流。 15. 如請求項14之讀取驅動電路，其中該預驅動單元及該主 驅動單元中之每一者接收該外部電源電壓。 16. 如請求項14之讀取驅動電路，其中該預驅動單元包括： 一預驅動器，其經組態以基於該内部資料產生該驅動 控制信號；及 一預驅動電流控制器’其經組態以基於該内部資料及 該偵測信號控制該預驅動電流。 17. 如請求項16之讀取驅動電路，其進一步包含一預控制信 號產生器’該預控制信號產生器經組態以回應於該偵測 信號而產生一預控制信號以控制該預驅動電流控制器。 18·如請求項16之讀取驅動電路，其中該預驅動電流控制器 在一預驅動器啟動時間間隔期間操作。 19. 如請求項14之讀取驅動電路，其中該主驅動單元包括： 一主驅動器’其經組態以回應於該驅動控制信號而驅 動該主驅動輸出端子；及 一主電流控制器，其經組態以基於該驅動控制信號及 該偵測信號控制該主驅動電流。 20. 如請求項19之讀取驅動電路，其進一步包含一主控制信 號產生器’該主控制信號產生器經組態以基於該驅動控 制信號及該偵測信號產生一主控制信號以控制該主電流 137511.doc 201011773 控制器。 21. 如請求項2〇之讀取驅動電路，其中該控制信號產生器在 一主驅動器啟動時間間隔期間啟動該控制信號。 22. —種一半導體記憶體裝置之驅動方法，其包含： 偵測一外部電源電壓之一電壓位準且產生一谓測結 果；201011773 VII. Patent application scope: 1. A semiconductor memory device for receiving an external power supply voltage, comprising: 'a data input driver' configured to receive an external power supply voltage and input data; a data output driver , configured to receive an external power supply voltage* and output data; and a voltage detector 'configured to detect the external power supply voltage and to generate a detection signal' wherein one of the data input drivers is driven The input drive current and an output drive current driving the data output driver are controlled by the detection signal. 2. The semiconductor memory device of claim 1, wherein the voltage detector comprises: a voltage divider configured to divide the external supply voltage and generate an internal reference voltage having a predetermined voltage level; a comparator configured to compare the internal reference voltage to the external supply voltage; and an output portion configured to output the detection signal number from the comparator. 3. The semiconductor memory device of claim 1, wherein the input data driver comprises an input portion that receives input data and the input drive current; and an input drive current controller configured to be based on the detection signal 137511.doc 201011773 Controls the input drive current. 4. The semiconductor memory device of claim 3, further comprising - a buffer - the buffer configured to buffer an output signal from the input portion and to rotate a buffered signal as internal data. 5. The semiconductor memory device of claim 3, further comprising an input control signal generator configured to generate an input control signal to control the input drive current controller based on the preamble signal . 6. The semiconductor memory device of claim 5, wherein the input control signal generator activates the input control signal during an input portion start time interval. 7. The semiconductor memory device of claim 1, wherein the data output driver comprises: a pre-drive unit configured to control a pre-drive current based on the data to be output and the detection signal, and based on the pre-drive The current generates a zero drive control signal; and a main drive unit configured to control a main drive current in response to the drive control signal and the detection signal, and to drive its output terminal based on the main drive current. 8. The semiconductor memory device of claim 7, wherein the pre-drive unit comprises: a pre-driver configured to be based on the drive control signal to be output; and a pre-drive current control, configured The pre-drive current is controlled based on the data to be output 137511.doc 201011773 and the detection signal. 9. The semiconductor memory device of claim 8, further comprising a pre-control heart generator, the pre-control signal generator configured to generate a pre-control signal based on the detected t-number to control the pre-drive current Controller. The semiconductor memory device of claim 8, wherein the pre-drive current controller operates during a pre-driver start time interval. The semiconductor memory device of claim 7, wherein the main driving unit comprises: a main driver configured to drive the output terminal based on the driving control signal; and a main driving current controller configured The main drive current is driven based on the drive control signal and the detection signal. 12. The semiconductor memory device of claim 11, further comprising a main control signal generator configured to generate a main control signal based on the drive control signal and the detection signal to control The main drive current controller. 13. The semiconductor memory device of claim 12, wherein the main control signal generator activates the main control signal during a main drive start time interval. 14. A read drive circuit for use in a semiconductor memory device, the read drive circuit comprising: a pre-drive unit configured to generate a drive control signal corresponding to internal data; a main drive unit, It is configured to provide an output data of 137511.doc 201011773 based on the drive control signal to the main drive output terminal; and a voltage detector configured to detect one The external power supply voltage generates a detection signal for controlling one of the pre-drive unit pre-drive current and one of the main drive unit main drive currents. 15. The read drive circuit of claim 14, wherein the pre-drive unit and each of the main drive units receive the external supply voltage. 16. The read drive circuit of claim 14, wherein the pre-drive unit comprises: a pre-driver configured to generate the drive control signal based on the internal data; and a pre-drive current controller 'configured The pre-drive current is controlled based on the internal data and the detection signal. 17. The read drive circuit of claim 16, further comprising a pre-control signal generator configured to generate a pre-control signal in response to the detect signal to control the pre-drive current Controller. 18. The read drive circuit of claim 16, wherein the pre-drive current controller operates during a pre-driver start time interval. 19. The read drive circuit of claim 14, wherein the main drive unit comprises: a main drive 'configured to drive the main drive output terminal in response to the drive control signal; and a main current controller The configuration is configured to control the main drive current based on the drive control signal and the detection signal. 20. The read drive circuit of claim 19, further comprising a main control signal generator configured to generate a main control signal based on the drive control signal and the detection signal to control the Main current 137511.doc 201011773 controller. 21. The read drive circuit of claim 2, wherein the control signal generator activates the control signal during a main drive start time interval. 22. A method of driving a semiconductor memory device, comprising: detecting a voltage level of an external power supply voltage and generating a predetermined measurement result; 23. 若該外部電源電壓基於該偵測結果而高於一目標電壓 位準，則藉由低於一對應於該外部電源電壓之驅動電流 的一驅動電流執行資料輸入/輸出操作；及 若該外部電源電壓基於該偵測結$而低於該目標電壓 位準’則藉由高於一對應於該外部電源電壓之驅動電流 的一驅動電流執行資料輸入/輸出操作。 如請求項22之驅動方法，竟中姑 再肀該偵測包括比較該外部電 源電壓與一對應於該目標雷壓/ 知冤壓位準之内部參考電壓。23. if the external power supply voltage is higher than a target voltage level based on the detection result, performing a data input/output operation by a driving current lower than a driving current corresponding to the external power supply voltage; and if The external power supply voltage is lower than the target voltage level based on the detection threshold $, and the data input/output operation is performed by a driving current higher than a driving current corresponding to the external power supply voltage. According to the driving method of claim 22, the detection includes comparing the external power source voltage with an internal reference voltage corresponding to the target lightning pressure/knowledge pressure level. 137511.doc137511.doc
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