KR20090047969A - Vbb detector and vbb generation circuit including the same - Google Patents

Vbb detector and vbb generation circuit including the same Download PDF

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Publication number
KR20090047969A
KR20090047969A KR1020070114117A KR20070114117A KR20090047969A KR 20090047969 A KR20090047969 A KR 20090047969A KR 1020070114117 A KR1020070114117 A KR 1020070114117A KR 20070114117 A KR20070114117 A KR 20070114117A KR 20090047969 A KR20090047969 A KR 20090047969A
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South Korea
Prior art keywords
detector
signal
test mode
output
mode signal
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KR1020070114117A
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Korean (ko)
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최향화
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주식회사 하이닉스반도체
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Publication of KR20090047969A publication Critical patent/KR20090047969A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

Abstract

The bulk voltage detector of the present invention includes a controller configured to generate a detector control signal enabled when the first test mode signal or the second test mode signal is enabled; A first detector outputting a first sensing signal in accordance with a bulk voltage level; A second detector driven according to a detector control signal to output a second sensing signal and to provide a current path to the bulk substrate; And a selector configured to output one of the first sensing signal and the second sensing signal as a bulk voltage sensing signal according to the second test mode signal.

Bulk Voltage, Cell Capacitor Coupling

Description

Bulk voltage detector and bulk voltage generating circuit comprising same {VBB Detector And VBB Generation Circuit Including The Same}

The present invention relates to a semiconductor integrated circuit, and more particularly, to a bulk voltage detector and a bulk voltage generation circuit including the same.

Due to the high speed, high density, and low power of semiconductor memory devices, the stability of the internal power source used internally has a great influence on the reliability of DRAM operation. The bulk voltage VBB is used to increase the data retention time by increasing the threshold voltage of the cell transistor. Since the cell transistor is composed of NMOS transistors, there is a loss of the threshold voltage when transferring high-level data. When the threshold voltage of the cell transistor is high, since the data to be written to the cell at the time of writing must overcome the threshold voltage of the cell transistor so high, it takes time to store the desired amount of charge in the cell. This problem is exacerbated when the temperature is lowered. This is because the threshold voltage of the cell transistor increases as the temperature decreases, which increases the time for storing the cell.

1 is a block diagram of a bulk voltage generation circuit according to the prior art.

The bulk voltage generation circuit shown in FIG. 1 is composed of a bulk voltage detector 1, an oscillator 2, and a charge pump 3.

The bulk voltage detector 1 outputs a detection signal bbeb according to the bulk voltage VBB level. Although not shown, the bulk voltage detector 1 may include a normal detector and a temperature modulation detector. The normal detector detects a change in the bulk voltage VBB level, and the temperature modulation detector detects a value having a slope according to temperature. In addition, one of the signals sensed by these two circuits is used as an output signal of the bulk voltage detector 1.

The oscillator 2 generates a pulse of a specific period according to the sense signal bbeb.

The charge pump 3 generates the bulk voltage VBB according to the pulse.

In the bulk voltage generation circuit illustrated in FIG. 1, when the absolute value of the bulk voltage VBB is low, the sensing signal bbeb is enabled, and the oscillator 2 is driven to generate the pulse. The charge pump 3 drives the lowered bulk voltage VBB to drive to a target bulk voltage level. In addition, the bulk voltage VBB increased by the charge pump 3 is fed back to the bulk voltage detector 1, and when the bulk voltage VBB reaches a target value, the bulk voltage detector 1 The disabled signal bbeb is output. Thus, the oscillator 2 and the charge pump 3 are not driven and the bulk voltage VBB level is maintained.

The bulk voltage VBB is used to adjust the leakage current and to improve the stability of the cell transistor. The bulk voltage detector 1 may select and use the normal detector or the temperature modulation detector according to the characteristics of the product. However, in the cell transistor of DRAM, a boosted voltage VPP is applied to a gate and the bulk voltage VBB is applied to a bulk. As the chip density increases, the bulk voltage VBB is coupled to a couple of cell transistors. The ring is greatly affected by the boost voltage VPP. Although there may be a difference in each product, there is no current path to the bulk substrate inside the chip, so that the time for the bulk voltage sensing unit 1 to respond to the change in the bulk voltage VBB is slow, and the bulk voltage VBB is unstable. do. Therefore, the bulk voltage generation circuit can generate a stable bulk voltage VBB since the current path with the bulk is designed to exist when driving by the temperature modulation detector, but when driving by the normal detector, the normal detector It is designed so that there is no current pass with the bulk substrate, resulting in an unstable bulk voltage (VBB).

An object of the present invention is to provide a bulk voltage detector and a bulk voltage generation circuit including the same for generating a stable bulk voltage and improving the stability and reliability of a cell transistor.

The bulk voltage detector of the present invention for achieving the above-described technical problem is a control unit for generating a detector control signal enabled by the first test mode signal or the second test mode signal is enabled; A first detector outputting a first sensing signal in accordance with a bulk voltage level; A second detector driven according to the detector control signal to output a second sensing signal and to provide a current path to the bulk substrate; And a selector configured to output one of the first sensing signal and the second sensing signal as a bulk voltage sensing signal according to the second test mode signal.

In the bulk voltage generation circuit including the bulk voltage detector of the present invention, a first detector for sensing a bulk voltage level and outputting a first sense signal as the first test mode signal or the second test mode signal is enabled is driven. A bulk voltage detector configured to provide a current path to the bulk substrate as the second detector is driven, and output the first sense signal as a bulk voltage sense signal; An oscillator driven according to the bulk voltage sensing signal to output a pulse; And a charge pump pumping according to the output of the oscillator to generate a bulk voltage and supplying the bulk voltage to the bulk voltage detector.

The bulk voltage detector and the bulk voltage generation circuit including the same according to the present invention can generate stable bulk voltages to ensure the stability of cell transistors, thereby improving yield, improving test performance, shortening test cost, and shortening test time.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram of a bulk voltage detector 100 and a bulk voltage generation circuit including the same according to the present invention.

The bulk voltage detector 100 illustrated in FIG. 2 includes a controller 10, a first detector 20, a second detector 30, and a selector 40.

The controller 10 generates a detector control signal Vbbtemp that is enabled when the first test mode signal TM_Vbb_Ib or the second test mode signal TM_Vbb_tempb is enabled. The first test mode signal TM_Vbb_Ib and the second test mode signal TM_Vbb_tempb are test mode signals, and the bulk voltage detector 100 may perform different operations according to each test mode signal as shown in Table 1 below. have.

Figure 112007080459322-PAT00001

      [Table 1. Table showing the operation of the present invention according to each test mode signal]

Referring to Table 1, when the first test mode signal TM_Vbb_Ib uses the output of the first detector 20 as the output of the bulk voltage detector 100, the bulk substrate is driven in such a manner as to drive the second detector. It is at a high level to provide a current pass on. The second test mode signal TM_Vbb_tempb is a signal for selecting one of the outputs of the first detector 20 or the second detector 30 as an output signal of the bulk voltage detector 100. If the second test mode signal TM_Vbb_tempb is at a high level, the output of the bulk voltage detector 100 is an output of the first detector 20. If the second test mode signal TM_Vbb_tempb is at a low level, the output of the bulk voltage detector 100 is an output of the second detector 30.

The first detector 20 detects the bulk voltage VBB and outputs a first detection signal A. The first detector 20 outputs the first sensing signal A having a high or low level according to the bulk voltage VBB. The first detector 20 is a detector for detecting a different kind of characteristic from the second detector 30. For example, the first detector 20 detects the first level at a constant level according to a change in temperature. The signal A is output, but the first sensing signal A, which varies according to the bulk voltage VBB level, is output. On the other hand, the second detector 30 outputs the second sensing signal B of a constant level according to the bulk voltage VBB level, but the second sensing signal B fluctuates according to a change in temperature. Is a detector that outputs. The first detector 20 is a detector that is not connected to the bulk substrate so that the bulk current path does not exist.

The second detector 30 is driven according to the detector control signal Vbbtemp to output a second sensing signal B and provide a current path to the bulk substrate. For example, the second detector 30 is a detector that outputs the second sensing signal B having a different value according to a change in temperature, and the second detector 30 passes a current through a bulk substrate during driving. It provides a detector.

The selector 40 outputs a bulk voltage detection signal bbeb of one of the first sensing signal A and the second sensing signal B according to the second test mode signal TM_Vbb_tempb. .

In addition, the bulk voltage generation circuit including the bulk voltage detector 100 illustrated in FIG. 2 includes the bulk voltage detector 100, the oscillator 200, and the charge pump 300.

The bulk voltage detector 100 detects the level of the bulk voltage VBB and outputs the bulk voltage detection signal bbeb. The bulk voltage detector 100 provides a current path to the bulk substrate according to the first test mode signal TM_Vbb_Ib or the second test mode signal TM_Vbb_tempb, and outputs the bulk voltage detection signal bbeb.

The oscillator 200 generates a pulse according to the bulk voltage detection signal bbeb. The oscillator 200 generates the pulse as the bulk voltage sensing signal bbeb is enabled, and does not generate the pulse as the bulk voltage sensing signal bbeb is disabled.

The charge pump 300 generates the bulk voltage VBB according to the pulse. The charge pump 300 increases the absolute value of the bulk voltage VBB every time the pulse is input.

The operation of the bulk voltage detector 100 shown in FIG. 2 and the bulk voltage generation circuit including the same will be described below.

When the bulk voltage VBB is unstable, when the low level is applied to the first test mode signal TM_Vbb_Ib and the high level is applied to the second test mode signal TM_Vbb_tempb, the controller 10 is enabled. The detector control signal Vbbtemp. Therefore, since the second detector 30 is driven and a current path exists to the bulk substrate, the level of the bulk voltage VBB is increased. Accordingly, the first detector 20 outputs the enabled first sensing signal A when the bulk voltage VBB is increased. Since the second test mode signal TM_Vbb_tempb is at a high level, the selector 40 outputs the first detection signal A as an output signal bbeb of the bulk voltage detector 100. The oscillator 200 receives the enabled first sensing signal A and generates the pulse. The charge pump 300 is driven according to the pulse, and drives until the bulk voltage VBB reaches a target value, and the bulk voltage VBB reaches a target value so that the detection signal of the bulk voltage detector 100 is reached. When bbeb is disabled, the charge pump 300 is not driven.

The bulk voltage generation circuit according to the related art does not have a current path to the bulk substrate even when the bulk voltage VBB is unstable, such as a fluctuation in the value of the boost voltage VPP, which is the gate voltage of the cell transistor. (VBB) does not immediately detect any change in the target. As a result, the conventional bulk voltage generation circuit produces an unstable bulk voltage VBB. In order to improve this, the present invention drives the second detector 30 which can provide a current path to the bulk substrate, and the bulk voltage sensing signal bbeb according to the variation of the bulk voltage VBB level is A method of outputting from the first detector 20 is introduced. Therefore, since there is a current path to the bulk substrate, the variation in the bulk voltage VBB can be immediately detected, thereby generating a stable bulk voltage VBB.

In addition, referring to the circuits shown in FIGS. 2 to 5, the present invention may adjust the amount of current flowing through the bulk substrate according to the third test mode signal TM_Vbb_upb and the fourth test mode signal TM_Vbb_dnb.

3 is a circuit diagram illustrating an embodiment of the controller 10 shown in FIG. 2.

The controller 10 includes a first detector signal generator 11 and a second detector signal generator 12.

The first detector signal generator 11 is the first, second, and third control signals Vbbup1 according to the first, third, and fourth test mode signals TM_Vbb_Ib TM_Vbb_upb TM_Vbb_dnb as the first current control signal Vbbno. , Vbbnormal1, Vbboffb1).

The first detector signal generator 11 includes first to third NAND gates ND1 to ND3 and first to third NOR gates NOR1 to NOR3. The first detector signal generator 11 is implemented by a combination of logic gates such as the first to third NAND gates ND1 to ND3 and the first to third NOR gates NOR1 to NOR3.

When the first test mode signal TM_Vbb_Ib is at a high level, the first to third control signals Vbbup1, Vbbnormal1, and Vbboffb1 having different levels are output according to the third and fourth test mode signals TM_Vbb_upb TM_Vbb_dnb. . When the first test mode signal TM_Vbb_Ib is at a low level, the first control signal Vbbup1 is at a low level regardless of the third and fourth test mode signals TM_Vbb_upb TM_Vbb_dnb, and the second and third adjustments. The signals Vbbnormal1 and Vbboffb1 are high level. The first, second, and third control signals Vbbup1, Vbbnormal1, and Vbboffb1 are signals for driving the first detector 20. The third and fourth test mode signals TM_Vbb_upb and TM_Vbb_dnb are test mode signals for adjusting the amount of current flowing through the first detector 20 up, down, and down.

In addition, the first detector signal generator 11 may have a logic level different according to the third and fourth test mode signals TM_Vbb_upb and TM_Vbb_dnb when a power-up signal vpwrup is at a high level. The control signals Vbbup1, Vbbnormal1 and Vbboffb1 are output. Also, when the power-up signal vpwrup is at a low level, the first, second, and third control signals Vbbup1, Vbbnormal1, and Vbboffb1 may be independent of the third and fourth test mode signals TM_Vbb_upb and TM_Vbb_dnb. High, low and low levels, respectively.

The second detector signal generator 12 adjusts fourth, fifth and sixth according to the first and second test mode signals TM_Vbb_Ib TM_Vbb_tempb and the third and fourth test mode signals TM_Vbb_upb and TM_Vbb_dnb. Outputs signals Vbbtempup, Vbbtempnormal, and Vbbtempoffb. The detector control signal Vbbtemp illustrated in FIG. 1 is the same as the fourth, fifth, and sixth control signals Vbbtempup, Vbbtempnormal, and Vbbtempoffb among the outputs of the controller 10.

The second detector signal generator 12 may include fourth to eighth NAND gates ND4 to ND8, a fourth NOR gate NOR4, a first inverter IV1, and first to third level shifters 13 to 15. ). The first to third level shifters 13 to 15 are respectively voltages or currents of the output of the fourth NAND gate ND4, the output of the fourth NOR gate NOR4, and the output of the first inverter IV1. The level is converted to a voltage or current level suitable for the second detector 30.

Figure 112007080459322-PAT00002

      [Table 2. Table showing the output signal of the second detector according to each test mode signal]

Table 2 shows logic levels of output signals of the second detector signal generator 12 according to the first to fourth test mode signals.

The output Vbbup2 of the fourth NAND gate ND4, the output Vbbnormal2 of the fourth NOR gate NOR4, and the sixth NAND gate according to the third and fourth test mode signals TM_Vbb_upb and TM_Vbb_dnb. The output Vbboffb2 of ND6) is as follows. When the third test mode signal TM_Vbb_upb is at a low level and the fourth test mode signal TM_Vbb_dnb is at a high level, an output Vbbup2 of the fourth NAND gate ND4 and the fourth NOR gate NOR4 are provided. The output Vbbnormal2 and the output Vbboffb2 of the sixth NAND gate ND6 are high, low, and high levels, respectively. When the third test mode signal TM_Vbb_upb is at a high level and the fourth test mode signal TM_Vbb_dnb is at a high level, an output Vbbup2 of the fourth NAND gate ND4 and the fourth NOR gate NOR4 are provided. The output Vbbnormal2 of and the output Vbboffb2 of the sixth NAND gate ND6 are low, high, and high levels, respectively. When the third test mode signal TM_Vbb_upb is at a high level and the fourth test mode signal TM_Vbb_dnb is at a low level, an output Vbbup2 of the fourth NAND gate ND4 and the fourth NOR gate NOR4 are provided. The output Vbbnormal2 of and the output Vbboffb2 of the sixth NAND gate ND6 are at low, low, and high levels, respectively.

Accordingly, the first and second level shifters 13 and 14 may receive the output Vbbup2 of the fourth NAND gate ND4 and the output Vbbnormal2 of the fourth NOR gate NOR4. The fourth and fifth control signals Vbbtempup and Vbbtempnormal of the same logic level are output.

If either the first test mode signal TM_Vbb_Ib or the second test mode signal TM_Vbb_tempb is at a low level, the output of the seventh NAND gate ND7 is at a high level, and the sixth control signal Vbbtempoffb is Each is equal to the logic level of the output Vbboffb2 of the sixth NAND gate ND6.

If both of the first test mode signal TM_Vbb_Ib and the second test mode signal TM_Vbb_tempb are high level, the output of the seventh NAND gate ND7 is low level, and thus the sixth adjustment signal Vbbtempoffb is The level is low regardless of the output Vbboffb2 of the sixth NAND gate ND6.

4 is a circuit diagram illustrating an embodiment of the first detector 20 illustrated in FIG. 2.

The first detector 20 includes a first voltage detector 21 and a first current controller 22.

The first detector 20 outputs the first sensing signal A having a high level when the absolute value of the bulk voltage VBB is lower than the first voltage, and when the absolute value of the bulk voltage VBB is lower than the first voltage. The first detection signal A is output.

The first voltage detector 21 outputs the first detection signal A according to the bulk voltage VBB. The first voltage detector 21 includes first to fourth PMOS transistors PM1 to PM4 and first NMOS transistor NM1. The first PMOS transistor PM1 receives a ground voltage Vss at its gate, a core voltage Vcore at its source, and a source of the second PMOS transistor PM2 at its drain. The second to fourth PMOS transistors PM4 receive the bulk voltages VBB at their gates and are a plurality of transistors connected in series with each other. The first sensing signal A may be output from the source of the second PMOS transistor PM2, and the drain of the fourth PMOS transistor PM4 and the drain of the first NMOS transistor NM1 may be reduced. Connected. The first NMOS transistor NM1 is driven by receiving the third control signal Vbboffb1. The first voltage detector 21 is driven as the third control signal Vbboffb1 is enabled, and outputs the first sense signal A according to the level of the bulk voltage VBB.

The first current controller 22 adjusts the amount of current flowing through the first detector 20 according to the first current control signal Vbbno. The first current control signal Vbbno is the same as the first, second, and third control signals Vbbup1, Vbbnormal1, and Vbboffb1 among the outputs of the control unit 10. The first current controller 22 includes second to third NMOS transistors NM2 to NM3. The second NMOS transistor NM2 receives the second control signal Vbbnormal1 through a gate, and a source and a drain are connected to a source and a drain of the fourth PMOS transistor PM4. The third NMOS transistor NM3 receives the first control signal Vbbup1 at a gate, a drain thereof is connected to a source of the third PMOS transistor PM3, and a source thereof is the fourth PMOS transistor PM4. Is connected to the drain.

When the first control signal Vbbup1 is at a low level and the second control signal Vbbnormal1 is at a high level, the amount of current flowing through the first detector 20 increases. This is because the series resistance of the fourth PMOS transistor PM4 is reduced among the resistances of the first voltage detector 21. When the first control signal Vbbup1 is at a high level and the second control signal Vbbnormal1 is at a low level, the amount of current flowing through the first detector 20 is further increased. This is because the series resistance of the third and fourth PMOS transistors PM3 and PM4 among the resistors of the first voltage detector 21 is reduced.

That is, the amount of current flowing through the first detector 20 varies according to the first, second, and third control signals Vbbup1, Vbbnormal1, and Vbboffb1.

FIG. 5 is a circuit diagram illustrating an embodiment of the second detector 30 shown in FIG. 2.

The second detector 30 includes a second voltage detector 31 and a second current controller 32.

The second voltage detector 31 outputs the second detection signal B according to the detector control signal Vbbtemp. The detector control signal Vbbtemp is the same as the fourth, fifth, and sixth control signals Vbbtempup, Vbbtempnormal, and Vbbtempoffb among the outputs of the controller 10. The second voltage detector 31 includes a fifth PMOS transistor PM5 and fourth to seventh NMOS transistors NM4 to NM7. The fifth PMOS transistor PM5 receives the ground voltage Vss at its gate, the core voltage Vcore at its source, and a drain thereof is connected to the drain of the fourth NMOS transistor NM4. The fourth to sixth NMOS transistors NM4 to NM6 are configured by a plurality of transistors which receive the core voltage Vcore through a gate and are connected in series with each other. In addition, the second sensing signal B is output from the drain of the fourth NMOS transistor NM4. The seventh NMOS transistor NM7 receives the sixth control signal Vbbtempoffb at a gate, a bulk voltage VBB is connected to a source, and a source of the sixth NMOS transistor NM6 is connected to a drain. do. That is, the second detector 30 has a current path to the bulk substrate when the second detector 30 is driven.

The second current adjuster 32 adjusts the amount of current flowing through the second detector 30 according to the detector control signals Vbbtempup and Vbbtempnormal. The second current controller 32 includes eighth to ninth NMOS transistors NM8 to NM9.

The eighth NMOS transistor NM8 receives a fifth control signal Vbbtempnormal at a gate and is connected to a drain and a source of the sixth NMOS transistor NM6 at a drain and a source. The ninth NMOS transistor NM9 receives the fourth control signal Vbbtempup at a gate, a drain thereof is connected to a drain of the fifth NMOS transistor NM5, and a source thereof is the seventh NMOS transistor NM9. NM7) is connected to the drain.

When the fourth control signal Vbbtempup is at a low level and the fifth control signal Vbbtempnormal is at a high level, the amount of current flowing through the second detector 30 increases. When the fourth control signal Vbbtempup is at a high level and the fifth control signal Vbbtempnormal is at a low level, the amount of current flowing through the second detector 30 is further increased.

That is, the amount of current flowing through the second detector 30 varies according to the fourth, fifth and sixth control signals Vbbtempup, Vbbtempnormal, and Vbbtempoffb.

FIG. 6 is a circuit diagram illustrating an embodiment of the selector 40 shown in FIG. 2.

The selector 40 includes first and second pass gates PG1 and PG2, a sixth PMOS transistor PM6, a tenth NMOS transistor NM1, a ninth NAND gate ND9, a second, and a second It consists of three inverters IV2 and IV3 and a fourth level shifter 41.

The first pass gate PG1 and the second pass gate PG2 selectively select the first sensing signal A and the second sensing signal B according to the second test mode signal TM_Vbb_tempb, respectively. send. The fourth level shifter 41 adjusts and outputs the output of the ninth NAND gate ND9 to the voltage level of the oscillator 200. Therefore, when the second test mode signal TM_Vbb_tempb is at a high level, the selector 40 outputs the first detection signal A as the bulk voltage detection signal bbeb and the second test mode signal ( When the TM_Vbb_tempb is at a low level, the second sensing signal B is output as the bulk voltage sensing signal bbeb.

In addition, the selector 40 senses the bulk voltage at a high level irrespective of the first sensing signal A and the second sensing signal B when the fifth test mode signal TM_Vbboffb is at a low level. Output the signal bbeb.

Referring to Tables 1 and 2, the operation modes of the present invention according to the first to fourth test mode signals are described as follows.

When the first test mode signal TM_Vbb_Ib is at a high level and the second test mode signal TM_Vbb_tempb is at a high level, the first detector 20 is driven and the second detector 30 is not driven. . The output of the first detector 20 becomes the output bbeb of the bulk voltage detector 100. Same as the prior art operation. The amount of current is adjusted in the first detector according to the third and fourth test mode signals. If the third test mode signal TM_Vbb_upb is at a low level and the fourth test mode signal TM_Vbb_dnb is at a high level, the amount of current is greatest. If the third test mode signal TM_Vbb_upb is at a high level and the fourth test mode signal TM_Vbb_dnb is at a high level, the amount of current is intermediate. If the third test mode signal TM_Vbb_upb is at a high level and the fourth test mode signal TM_Vbb_dnb is at a low level, the amount of current is the smallest.

When the first test mode signal TM_Vbb_Ib is at a high level and the second test mode signal TM_Vbb_tempb is at a low level, the first detector 20 and the second detector 30 are driven, and the second detector 30 is driven. The output of the two detectors 30 becomes the output of the bulk voltage detector 100. When the second detector 30 is a temperature modulation detector, the second detector 30 generates the bulk voltage VBB according to a change in temperature.

When the first test mode signal TM_Vbb_Ib is at a low level and the second test mode signal TM_Vbb_tempb is at a high level, the first detector 20 and the second detector 30 are driven, and the first detector is driven. An output of 20 is the output of the bulk voltage detector 100. According to the present invention, the bulk voltage VBB is generated. The amount of current flowing through the first detector 20 and the second detector 30 varies according to the third and fourth test mode signals TM_Vbb_upb and TM_Vbb_dnb as described above.

When the first test mode signal TM_Vbb_Ib is at a low level and the second test mode signal TM_Vbb_tempb is at a low level, the first detector 20 and the second detector 30 are driven. The output of the second detector 30 is the output of the bulk voltage detector 100. However, the amount of current flowing through the second detector 30 is not variable according to the third and fourth test mode signals TM_Vbb_upb and TM_Vbb_dnb.

As such, those skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without changing the technical spirit or essential features.

Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of a bulk voltage generation circuit according to the prior art,

2 is a block diagram of a bulk voltage detector and a bulk voltage generation circuit including the same according to the present invention;

3 is a circuit diagram illustrating an embodiment of a control unit illustrated in FIG. 2;

4 is a circuit diagram illustrating an embodiment of a first detector illustrated in FIG. 2;

FIG. 5 is a circuit diagram illustrating an embodiment of a second detector shown in FIG. 2;

FIG. 6 is a circuit diagram illustrating an embodiment of the selector illustrated in FIG. 2.

<Description of the symbols for the main parts of the drawings>

10: control unit 20: first detector

30: second detector 40: selection unit

100: bulk voltage detector 200: oscillator

300: charge pump

Claims (15)

A controller configured to generate a detector control signal enabled when the first test mode signal or the second test mode signal is enabled; A first detector outputting a first sensing signal in accordance with a bulk voltage level; A second detector driven according to the detector control signal to output a second sensing signal and to provide a current source to the bulk substrate; And And a selector configured to output one of the first sensing signal and the second sensing signal as a bulk voltage sensing signal according to the second test mode signal. The method of claim 1, As the first test mode signal is low enabled, the second detector is driven to provide a current path to the bulk substrate, and as the second test mode signal is enabled, the output of the first detector is output to the bulk voltage. Bulk voltage detector, characterized in that output as a sense signal. The method of claim 1, The control unit, When the first test mode signal is enabled, the first to third control signals, which are first current control signals, are output according to a third test mode signal and a fourth test mode signal. A first detector signal generator configured to output the first to third adjustment signals irrelevant to the third test mode signal and the fourth test mode signal when the first test mode signal is disabled; And Outputs a fourth control signal and a fourth control signal among the detector control signals having different values according to the third test mode signal and the fourth test mode signal, and according to the first test mode signal and the second test mode signal. And a second detector signal generator configured to output the enabled sixth adjustment signal among the detector control signals. The method of claim 1, The first detector, A first voltage detector configured to output the first sense signal according to the bulk voltage; And And a first current controller configured to adjust an amount of current flowing through the first detector according to a first current control signal. The method of claim 4, wherein The first detector, If the absolute value of the bulk voltage is lower than the first voltage, and outputs the first sense signal of a high level, And when the voltage is higher than the first voltage, outputting the first detection signal having a low level. The method of claim 1, The second detector, A second voltage detector configured to output the second detection signal according to the detector control signal; And And a second current controller configured to adjust an amount of current flowing through the second detector according to the detector control signal. The method of claim 1, The selection unit, And a pass gate for transmitting the first sensed signal and blocking the second sensed signal as the second test mode signal is enabled. As the first test mode signal or the second test mode signal is enabled, a first detector that senses a bulk voltage level and outputs a first sense signal is driven, and a current path is provided to the bulk substrate as the second detector is driven. A bulk voltage detector configured to output the first sense signal as a bulk voltage sense signal; An oscillator driven according to the bulk voltage sensing signal to output a pulse; And And a charge pump pumping according to the output of the oscillator to generate a bulk voltage and supplying the bulk voltage to the bulk voltage detector. The method of claim 8, The bulk voltage detector, A controller configured to generate a detector control signal enabled when the first test mode signal or the second test mode signal is enabled; The first detector outputting the first sensing signal according to the bulk voltage level; The second detector driven according to the detector control signal to output a second sensing signal and to provide a current path to the bulk substrate; And And a selector configured to output one of the first sensing signal and the second sensing signal as the bulk voltage sensing signal according to the second test mode signal. The method of claim 9, And the second detector is driven as the first test mode signal is enabled to provide a current path to the bulk substrate. The method of claim 9, The first detector, A first voltage detector configured to output the first sense signal according to the bulk voltage; And And a first current controller configured to adjust an amount of current flowing through the first detector according to a first current control signal. The method of claim 11, The first detector, If the absolute value of the bulk voltage is lower than the first voltage, and outputs the first sense signal of a high level, And a higher level than the first voltage to output the first sense signal having a low level. The method of claim 9, The second detector, A second voltage detector configured to output the second detection signal according to the detector control signal; And And a second current controller configured to adjust an amount of current flowing through the second detector according to the detector control signal. The method of claim 9, The selection unit, And a pass gate that transmits the first sensed signal and blocks the second sensed signal as the second test mode signal is enabled. The method of claim 9, The control unit, When the first test mode signal is enabled, the first to third control signals that are the first current control signals are output according to the third test mode signal and the fourth test mode signal. A first detector signal generator configured to output the first to third adjustment signals irrelevant to the third test mode signal and the fourth test mode signal when the first test mode signal is disabled; And Outputting fourth and fifth control signals having different values according to the third test mode signal and the fourth test mode signal, and enabling the first test mode signal and the second test mode signal to be enabled according to the first test mode signal and the second test mode signal. And a second detector signal generator for outputting a sixth adjustment signal.
KR1020070114117A 2007-11-09 2007-11-09 Vbb detector and vbb generation circuit including the same KR20090047969A (en)

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