KR20100078223A - Circuit for detecting negative voltage of semiconductor memory apparatus - Google Patents

Circuit for detecting negative voltage of semiconductor memory apparatus Download PDF

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Publication number
KR20100078223A
KR20100078223A KR1020080136420A KR20080136420A KR20100078223A KR 20100078223 A KR20100078223 A KR 20100078223A KR 1020080136420 A KR1020080136420 A KR 1020080136420A KR 20080136420 A KR20080136420 A KR 20080136420A KR 20100078223 A KR20100078223 A KR 20100078223A
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South Korea
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level
voltage
comparator
reference voltage
comparison
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KR1020080136420A
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Korean (ko)
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구기봉
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주식회사 하이닉스반도체
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Priority to KR1020080136420A priority Critical patent/KR20100078223A/en
Publication of KR20100078223A publication Critical patent/KR20100078223A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)

Abstract

PURPOSE: A circuit for detecting negative voltage of a semiconductor memory device is provided to not increase a negative level, thereby reducing negative voltage generation consumption current. CONSTITUTION: A distribution voltage generation(100) has a fixed resistance unit and a variable resistance unit. The distribution voltage generation unit generates a distribution voltage. A first comparison unit(200) compares a distribution voltage and level of a first standard voltage. A first comparison unit generates a first comparison signal. A second comparison unit(300) compares a distribution voltage and level of a second standard voltage. A second comparison unit generates a second comparison signal. A third comparison unit(400) compares a first comparison signal and a level of the second comparison signal. A third comparison unit generates detecting signal.

Description

Circuit for Detecting Negative Voltage of Semiconductor Memory Apparatus

The present invention relates to a semiconductor memory device, and more particularly to a negative voltage sensing circuit.

In general, a semiconductor memory device receives a voltage applied from the outside and generates and uses a voltage necessary for performing an operation of the semiconductor memory device therein. Negative voltage is also one of the voltages generated inside the semiconductor memory device.

In general, a negative voltage generation circuit for generating a negative voltage is a negative voltage detection circuit for detecting a negative voltage level to generate a detection signal, an oscillator for generating an oscillator signal in response to the detection signal, and a pumping operation in response to the oscillator signal, And a charge pump generating a negative voltage through the pumping operation.

In this case, the general negative voltage sensing circuit includes first to fifth transistors P1, P2, N1, N2, and N3, and first and second inverters IV1 and IV2, as shown in FIG. 1. The first to fourth transistors P1, P2, N1, and N2 are connected in series between an external voltage terminal VDD and a negative voltage terminal VBB, and the first and second transistors P1 and P2 are connected to each other in series. A gate is connected to the ground terminal VSS, and gates of the third and fourth transistors N1 and N2 are connected to an external voltage terminal VDD. A drain and a source of the fifth transistor N3 are connected to the drain and the source of the second transistor N2, and a test signal TVBBUP is input to a gate. The first inverter IV1 receives the voltage of the first node A connected to the second and third transistors P2 and N1. The second inverter IV2 receives the output of the first inverter IV1 and outputs a detection signal det.

The general negative voltage sensing circuit configured as described above operates as follows.

The first to fourth transistors P1, P2, N1, and N2 are always turned on, and the voltage level of the first node node A is determined according to the level of the negative voltage terminal VBB. When the level of the negative voltage terminal VBB is lowered, the voltage level of the first node node A is also lowered. When the level of the negative voltage terminal VBB is higher, the voltage level of the first node node A is lowered. Also increases. In addition, when the test signal TVBBUP is enabled and the fifth transistor N3 is turned on, the resistance value between the first node node a and the negative voltage terminal VBB decreases. Therefore, when the fifth transistor N3 is turned on while the negative voltage terminal VBB level is the same, the voltage level of the first node node A is lowered.

The voltage level of the first node A is output as the detection signal det through the first and second inverters IV1 and IV2.

That is, when the voltage level of the first node A rises above a predetermined voltage level, the detection signal det is enabled to a high level.

The enabled sense signal det is input to the oscillator to activate the oscillator, and the activated oscillator outputs the oscillator signal to the charge pump. The charge pump receiving the oscillator signal performs a pumping operation in response to the oscillator signal, and a negative voltage is generated through the pumping operation.

As shown in FIG. 1, the negative voltage sensing circuit designed to perform such an operation may include the first to fourth transistors P1, P2, N1, and N2 connected in series to have an external voltage terminal VDD and a negative voltage terminal ( VBB) is connected, and the current flowing through the first to fourth transistors P1, P2, N1, and N2 flows to the negative voltage terminal VBB, causing the level of the negative voltage VBB to increase. do.

In addition, the first inverter IV1 includes a PMOS transistor P3 and an NMOS transistor N4, and the PMOS transistor P3 and the NMOS transistor N4 are connected to the first node A. FIG. The gates are commonly connected. Accordingly, the PMOS transistor P3 or the NMOS transistor N4 is turned on / off according to the voltage level of the first node A to determine the level of the sensing signal det. As a result, the sensing signal det is generated in a structure that is greatly influenced by the threshold voltage of the transistor constituting the first inverter IV1. In general, the threshold voltage of a transistor is vulnerable to a change in P.V.T (process, voltage, temperature). For example, when the threshold voltage of the PMOS transistor P3 is lowered, the detection signal det may be enabled at a voltage level of the first node A lower than when the threshold voltage is high. In addition, when the threshold voltage of the NMOS transistor N4 decreases, the sensing signal det may be disabled at the voltage level of the first node A lower than when the threshold voltage is high.

That is, the general negative voltage sensing circuit not only has a problem of raising the level of the negative voltage but also has a problem that the negative voltage level of enabling or disabling the sensing signal may change according to a process, voltage, or temperature (PVT) change. have.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a negative voltage sensing circuit of a semiconductor memory device capable of stably detecting a negative voltage level regardless of a PVT change without raising the negative voltage level. There is a purpose.

According to an exemplary embodiment of the present invention, a negative voltage sensing circuit of a semiconductor memory device may include a fixed resistor unit receiving an internal voltage at one end thereof, a second end of the fixed resistor unit connected at one end thereof, and a ground terminal connected at the other end thereof according to a negative voltage level. A variable resistor unit having a variable resistance value includes a divided voltage generator configured to generate a divided voltage at a node to which the fixed resistor unit and the variable resistor unit are connected, and compares a level of the divided voltage with a first reference voltage to obtain a first comparison signal. A first comparator for generating a second comparator for generating a second comparison signal by comparing a level of the divided voltage and a second reference voltage, and sensing the level of the first comparison signal and the second comparison signal And a third comparator for generating a signal.

Since the negative voltage sensing circuit of the semiconductor memory device according to the present invention does not increase the negative voltage level in sensing the negative voltage level, the current consumed to generate the negative voltage can be reduced, and the negative voltage is independent of the PVT change. There is an effect that can be detected stably.

As shown in FIG. 2, the negative voltage sensing circuit of the semiconductor memory device according to the embodiment of the present invention may include a divided voltage generator 100, a first comparator 200, a second comparator 300, and a second comparator 300. 3 includes a comparison unit 400.

The divided voltage generator 100 generates a divided voltage V_dv whose level is changed according to a negative voltage VBB level.

The division voltage generator 100 includes a fixed resistor unit 110 and a variable resistor unit 120.

The fixed resistor unit 110 may be implemented as a passive resistance element, an NMOS transistor to which an external voltage is applied to a gate, or a PMOS transistor having a ground terminal connected to a gate thereof, and receives an internal voltage Vint at one end thereof.

The variable resistor unit 120 has one end connected to the other end of the fixed resistor unit 110 and the other end connected to the ground terminal, and the resistance value of the variable resistor unit 120 depends on the negative voltage VBB level. Variable. For example, when the negative voltage VBB level increases, the resistance value of the variable resistor unit 120 increases, and when the negative voltage VBB level decreases, the resistance value of the variable resistor unit 120 decreases. . In this case, the division voltage V_dv is output from a node to which the fixed resistor unit 110 and the variable resistor unit 120 are connected.

The first comparator 200 generates a first comparison signal com1 by comparing the first reference voltage Vref1 level with the divided voltage V_dv level. For example, the first comparator 200 generates the first comparison signal com1 enabled to a high level when the divided voltage V_dv level is higher than the first reference voltage Vref1 level. . On the contrary, the first comparison unit 200 generates the first comparison signal com1 disabled to a low level when the division voltage V_dv level is lower than the first reference voltage Vref1 level.

The second comparator 300 generates a second comparison signal com2 by comparing the second reference voltage level Vref2 with the divided voltage level V_dv. For example, the second comparator 300 generates the second comparison signal com2 enabled to a low level when the divided voltage V_dv level is higher than the second reference voltage Vref2 level. On the contrary, the second comparator 300 generates the second comparison signal com2 disabled to a high level when the division voltage V_dv level is lower than the second reference voltage Vref2 level. In this case, it is assumed that the level of the first reference voltage Vref1 is higher than the level of the second reference voltage Vref2.

When both the first comparison signal com1 and the second comparison signal com2 are enabled, the third comparison unit 400 generates a preliminary detection signal det_pre enabled at a high level. Meanwhile, the third comparison unit 400 generates the disabled preliminary detection signal det_pre when both the first comparison signal com1 and the second comparison signal com2 are disabled. For example, when the third comparison unit 400 receives the first comparison signal com1 enabled at the high level and the second comparison signal com2 enabled at the low level, the third comparison unit 400 enables the high level. The preliminary detection signal det_pre is generated. In addition, the third comparator 400 receives the first comparison signal com1 disabled at a low level and the second comparison signal com2 disabled at a high level. The preliminary detection signal de_pre is generated.

The first to third comparison units 200 to 400 may receive an internal voltage Vint and a ground voltage VSS as driving voltages for stable comparison operation.

Accordingly, the preliminary detection signal det_pre, which is an output signal of the third comparison unit 400, is a signal that swings to the internal voltage Vint level and the ground voltage VSS level, and thus the preliminary detection signal. The level shifter 500 may be used to convert the det_pre into a signal swinging the external voltage VDD and the ground voltage VSS.

The level shifter 500 is a level shifter which is generally used. The level shifter 500 level shifts the preliminary sensing signal det_pre and outputs it as a sensing signal det swinging to an external voltage VDD level and a ground voltage VSS level. .

As shown in FIG. 3, the divided voltage generator 100 includes the fixed resistor unit 110 and the variable resistor unit 120.

The fixed resistor unit 110 includes a first transistor P11, which has a ground terminal VSS connected to a gate thereof, and receives an internal voltage Vint from a source. The fixed resistor unit 110 is connected to the ground terminal VSS of the first transistor P11 and receives an internal voltage Vint from a source to transfer a predetermined amount of current to the variable resistor unit 120. ) Is a constant current source.

The variable resistor unit 120 includes a second transistor P12, and the second transistor P12 receives a negative voltage VBB at a gate thereof and a drain of the first transistor P11 is connected to a source. The ground terminal VSS is connected to the drain.

The turn-on resistance value of the second transistor P12 is changed according to the degree of turn-on according to the level of the negative voltage VBB applied to the gate.

Therefore, the divided voltage generator 100 may divide the divided voltage by the variable resistor value of the second transistor P12 according to the fixed resistance value of the fixed resistor unit 110 and the negative voltage VBB level. V_dv).

As shown in FIG. 4, each of the first to third comparison units 200, 300, and 400 is implemented by a current mirror type comparison circuit. The current mirror type comparison circuit includes third to seventh transistors P21, P22, N21, N22, and N23 so that the voltage level of the first input terminal in1 is higher than the voltage level of the second input terminal in2. Output the output signal out of the level, and output the output signal out of the low level if the voltage level of the first input terminal in1 is lower than the voltage level of the second input terminal in2. In addition, the current mirror type comparison circuit includes a current sink (current_sink) for controlling the amount of current flowing to the ground terminal (VSS) in accordance with the applied voltage level. The current sink unit (current_sink) is implemented by the seventh transistor (N23), the seventh transistor (N23) at the level of the first reference voltage (Vref1) or the second reference voltage (Vref2) applied to the gate. The degree of turn-on is determined accordingly to control the amount of current flowing to the ground terminal VSS in the current mirror type comparison circuit. If it is assumed that the level of the first reference voltage Vref1 is higher than the level of the second reference voltage Vref2, the second reference voltage Vref2 may be applied to the current sink unit current_sink. When the first reference voltage Vref1 is applied to the current sink currnet_sink, the current mirror comparison circuit flows a larger amount of current to the ground terminal VSS.

The current mirror type comparison circuit may be configured to generate the current according to the level difference between the first input terminal in1 and the second input terminal in2 when a larger amount of current is passed to the ground terminal VSS than a small amount of current flows. The speed of generating the output signal out, that is, the response speed, is increased.

The negative voltage sensing circuit of the semiconductor memory device according to the embodiment configured as described above operates as follows.

It is assumed that the first reference voltage Vref1 level is higher than the second reference voltage Vref2 level.

The negative voltage VBB level is increased to increase the resistance value of the variable resistor unit 120.

When the resistance of the variable resistor unit 120 increases, the level of the divided voltage V_dv increases.

In this case, it is assumed that the level of the divided voltage V_dv is higher than the level of the first reference voltage Vref1.

The first comparator 200 enables the first comparison signal com1 to a high level, and the second comparator 300 enables the second comparison signal com2 to a low level.

The third comparator 400 receives the first comparison signal com1 having a high level and the second comparison signal com2 having a low level and enables the preliminary detection signal det_pre to a high level.

The level shifter 500 level-shifts the preliminary sensing signal det_pre enabled to the internal voltage level V_int to the external voltage VDD level and outputs the sensed signal det.

The sense signal det enabled to the high level operates the oscillator, and the charge pump performs a pumping operation in response to the oscillator signal output from the oscillator.

The charge pump performs a pumping operation to lower the negative voltage VBB level.

As the negative voltage VBB level is lowered, the division voltage V_dv level is lower than the first reference voltage Vref1 level.

Assume that the division voltage V_dv level is lower than the first reference voltage Vref1 level and higher than the second reference voltage Vref2 level.

The first comparison signal com1 is disabled from a high level to a low level, and the second comparison signal com2 maintains a low level.

The third comparator 400 receives the first and second comparison signals com1 and com2 that are both low level.

The third comparison unit 400 generates the preliminary detection signal det_pre based on the voltage level difference between the first and second comparison signals com1 and com2, and thus, the first and second comparison signals com1, Even if com2) is at the same low level, the preliminary sensing signal de_pre is generated due to the difference in voltage levels of the two comparison signals. However, since the first and second comparison signals com1 and com2 have the same low level, the voltage level difference between the two comparison signals is not large, so the preliminary detection signal det_pre is larger than when the voltage level difference between the two comparison signals is larger. The transition slows down.

If the preliminary sensing signal det_pre is continuously enabled at a high level, the sensing signal det is continuously enabled at a high level, and thus the negative voltage VBB level is continuously lowered.

A case in which the negative voltage VBB level is lowered and the divided voltage V_dv becomes lower than the second reference voltage Vref2 will be described.

The first comparison signal com1 remains disabled at a low level, and the second comparison signal com2 is enabled at a high level.

The third comparator 400 receives the first comparison signal com1 at a low level and the second comparison signal com2 at a high level, and generates the preliminary detection signal det_pre disabled at a low level. do.

When the preliminary sensing signal det_pre is disabled at a low level, the sensing signal det is also disabled at a low level. When the sense signal det is disabled, the oscillator stops generating the oscillator signal and stops the charge pump and pumping operation so that the negative voltage VBB level is no longer lowered.

The negative voltage generation circuit of the semiconductor memory device according to the present invention sets the level of the first reference voltage and the second reference voltage differently, and compares the divided voltage level according to the negative voltage level with the first and second reference voltage levels, respectively. The division voltage level is compared with the first and second reference voltage levels, respectively, to generate a sensing signal according to the voltage level difference of the first and second comparison signals generated. If the first reference voltage level is set higher than the second reference voltage level, the negative voltage generation circuit according to the present invention enables the sense signal and the divided voltage level is higher when the divided voltage level is higher than the first reference voltage level. If it is lower than the second reference voltage level, the sense signal is disabled. In addition, when the divided voltage level is a voltage between the first reference voltage and the second reference voltage level, the detection signal is generated according to the voltage level difference between the first and second comparison signals.

The present invention can quickly enable or disable the sense signal when the distribution voltage level is higher than the first reference voltage level or when the distribution voltage level is lower than the second reference voltage level (the distribution voltage level is first and second). The voltage level difference between the first and second comparison signals generated by comparing the reference voltage level with each other is large), and when the divided voltage level is the voltage level between the first reference voltage and the second reference voltage level, It may be enabled or disabled slowly (when the voltage level difference between the first and first comparison signals generated by comparing the divided voltage levels with the first and second reference voltage levels, respectively) is small.

As a result, the negative voltage generation circuit of the semiconductor memory device according to the present invention can determine the maximum level and the minimum level of the negative voltage level by setting the levels of the first reference voltage and the second reference voltage differently. It will enable the sense signal sooner than the maximum voltage level and quickly disable the sense signal when the negative voltage level is below the minimum voltage level. Also, when the negative voltage level is between the maximum and minimum levels, the sense signal is slowly enabled or disabled depending on the target level set by the inventor or designer.

The semiconductor memory device according to the present invention not only adjusts the generation speed of the detection signal according to the negative voltage level, but also sets the voltage level applied to the current sink of each comparator, thereby controlling the operation speed of each comparator to sense the detection signal. You can control the rate at which you create them. In addition, the present invention has a structure that prevents current from flowing to the negative voltage terminal, unlike the prior art, the negative voltage level does not increase due to the negative voltage sensing circuit, and detects by comparing the level difference between the distribution voltage and the reference voltage according to the negative voltage level. By generating a signal, the negative voltage level can be detected regardless of changes in process, voltage, or temperature (PVT).

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a detailed configuration diagram of a negative voltage sensing circuit of a semiconductor memory device according to the prior art;

2 is a configuration diagram of a negative voltage sensing circuit of a semiconductor memory device according to an embodiment of the present invention;

3 is a detailed configuration diagram of the divided voltage generation unit of FIG. 2;

4 is a detailed configuration diagram of the first to third comparison units of FIG. 2.

<Description of the symbols for the main parts of the drawings>

100: divided voltage generation unit 200, 300, 400: first to third comparison unit

500: level shifter

Claims (7)

A fixed resistor unit receiving an internal voltage at one end thereof, and a variable resistor unit having one end connected to the other end of the fixed resistor unit and a second end connected to the ground terminal, and having a resistance value changed according to a negative voltage level. A division voltage generator configured to generate a division voltage at a node to which the variable resistor unit is connected; A first comparator configured to generate a first comparison signal by comparing the divided voltage with a level of a first reference voltage; A second comparison unit configured to generate a second comparison signal by comparing the divided voltage with a level of a second reference voltage; And And a third comparator configured to generate a sensing signal by comparing the level of the first comparison signal with the level of the second comparison signal. The method of claim 1, The negative voltage sensing circuit of the semiconductor memory device, wherein the first reference voltage and the second reference voltage level are different from each other. The method of claim 2, And the first comparator, the second comparator, and the third comparator operate by receiving the internal voltage and the ground voltage. The method of claim 3, wherein And a level shifter for level shifting the sense signal to a level between an external voltage and a ground voltage. The method of claim 2, When the first reference voltage level is higher than the second reference voltage level, the first comparator, the second comparator, and the third comparator receive the first reference voltage than when the second reference voltage is applied. A negative voltage sensing circuit of a semiconductor memory device, characterized in that the response speed of each comparator increases when it is applied. The method of claim 5, Each of the first comparator, the second comparator, and the third comparator includes a current sink configured to adjust an amount of current flowing to the ground terminal according to the first reference voltage or the second reference voltage. A negative voltage sensing circuit of a semiconductor memory device. The method of claim 1, The variable resistor unit And a transistor in which the negative voltage is applied to a gate, the fixed resistor unit is connected to a source, and a ground terminal is connected to a drain thereof.
KR1020080136420A 2008-12-30 2008-12-30 Circuit for detecting negative voltage of semiconductor memory apparatus KR20100078223A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110196348A (en) * 2018-02-26 2019-09-03 半导体组件工业公司 Negtive voltage detection and voltage surge protection
CN115309231A (en) * 2021-05-08 2022-11-08 长鑫存储技术有限公司 Comparison circuit and negative voltage generation system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110196348A (en) * 2018-02-26 2019-09-03 半导体组件工业公司 Negtive voltage detection and voltage surge protection
CN115309231A (en) * 2021-05-08 2022-11-08 长鑫存储技术有限公司 Comparison circuit and negative voltage generation system
CN115309231B (en) * 2021-05-08 2024-05-10 长鑫存储技术有限公司 Comparison circuit and negative voltage generation system

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