KR100675899B1 - Internal voltage generating circuit and internal voltage supplying apparatus - Google Patents

Abstract

An internal voltage generating circuit and an internal voltage supplying apparatus are provided to achieve low power consumption by supplying a lower level internal voltage in the self refresh mode rather than in an active mode and a standby mode. An internal voltage generation part(10) operates in response to an enable signal, and generates a first internal voltage using a reference voltage and then supplies the first internal voltage to an output stage. A first driver(P21) drives the output stage with a second internal voltage level during a self refresh operation period in response to a self refresh signal. A second driver(P20) drives the output stage with an external voltage level in response to a first control signal, which is enabled during an initialization period of a semiconductor memory device, a period where the external voltage is below a fixed voltage level, and a predetermined period after self refresh is completed.

Description

Internal Voltage Generating Circuit and Internal Voltage Supplying Apparatus}

1 illustrates an internal voltage supplying apparatus (VPERI) of a semiconductor memory device.

2 illustrates a configuration of an internal voltage generation circuit VPERI according to an embodiment of the present invention.

3 illustrates a configuration of a logic unit that generates a control signal shortb used in the internal voltage generation circuit.

FIG. 4A illustrates a configuration of a control signal generator that generates a control signal ref_ext used in the internal voltage generation circuit.

4B is a timing diagram for describing an operation of the control signal generator.

FIG. 5 illustrates a configuration of a signal generation unit that generates an enable signal used in the internal voltage generation circuit.

The present invention relates to an internal voltage generation circuit and an internal voltage supply device. More particularly, the semiconductor memory device supplies a lower level of internal voltage in the self refresh mode than in the active mode and the standby mode, thereby providing a self refresh mode. The present invention relates to an internal voltage generator and an internal voltage supply device capable of reducing power consumption of the semiconductor memory device to reduce power consumption.

In general, a semiconductor memory device receives an external voltage (VDD) and makes and writes various internal voltages necessary for an internal chip. Among them, the internal voltage VPERI is a voltage which is used for the peripheral circuit region circuit by down converting the external voltage VDD inside the memory device. FIG. 1 illustrates an internal voltage supply device of a semiconductor memory device, and an operation scheme of the internal voltage supply device of a conventional semiconductor memory device will be described below.

As shown in FIG. 1, the internal voltage supplying device (VPERI) includes an active internal voltage generation circuit 100 to 300 and a standby internal voltage generation circuit 400. Here, the active internal voltage generation circuits 100 to 300 are mainly used to supply the internal voltage VPERI in the active mode, and the standby internal voltage generation circuit 400 is mainly used to supply the internal voltage VPERI in the standby mode. To be used. The standby mode refers to an operation standby state in which no substantial operation is performed in the semiconductor memory device. As shown in FIG. 1, the active internal voltage generation circuits 100 to 300 and the standby internal voltage generation circuit 400 are compared with a predetermined reference voltage VREF under the control of control signals. Generates the appropriate level of internal voltage (VPERI).

In the conventional semiconductor memory device, the active internal voltage generation circuits 100 to 300 and the standby internal voltage generation circuit 400 are operated in an active operation mode in which current consumption is relatively high, thereby increasing the driving force of the internal voltage VPERI. . On the other hand, in the standby mode where the current consumption is relatively low, the active internal voltage generation circuits 100 to 300 are turned off and only the standby internal voltage generation circuit 400 is operated. In addition, conventionally, only the standby internal voltage generation circuit 400 is operated in the self refresh mode to generate the internal voltage VPERI, thereby reducing current consumption in the self refresh mode. However, even in the case of the conventional method, the internal voltage VPERI generated by the standby internal voltage generation circuit 400 is not large enough to reduce the current consumption. In other words, although the current consumption in the self-refresh mode was not as large as that of the active mode, the absolute current consumption still greatly affected the overall current consumption of the semiconductor memory device, so improvement was required.

Accordingly, a technical problem of the present invention is to provide a lower level internal voltage in the self-refresh mode than the active mode and the standby mode in the self-refresh mode, thereby reducing the current consumption in the self-refresh mode, An internal voltage generation circuit and an internal voltage supply device capable of achieving low power can be provided.

In order to achieve the above technical problem, the present invention operates in response to a predetermined enable signal, an internal voltage generation unit for generating a first internal voltage using a predetermined reference voltage and supplying to the output terminal; A first driver for driving the output terminal to a level of a second internal voltage during a self refresh operation section in response to a self refresh signal; A second driver configured to drive the output terminal to an external voltage level in response to an initialization section of the semiconductor memory device, a section in which an external voltage is below a predetermined voltage level, and a first control signal enabled for a predetermined section after completion of self refresh. It provides an internal voltage generation circuit configured.

In addition, the present invention includes at least one internal voltage generation circuit for supplying the internal voltage in the active mode and the self refresh mode; And at least one standby internal voltage generation circuit for supplying the internal voltage in the standby mode, wherein the standby internal voltage generation circuit is turned off in the self-refresh mode. do.

In the present invention, the internal voltage generation circuit logically operates an initialization signal of the semiconductor memory device, a second control signal enabled when the external voltage is below a predetermined voltage level, and a third control signal enabled for a predetermined period after the self refresh is completed. And further comprising a first logic unit to generate the first control signal.

In the present invention, the first logic unit preferably performs an AND operation.

In an embodiment of the present invention, the internal voltage generation circuit may further include a control signal generator configured to receive the self refresh signal and generate the third control signal, wherein the control signal generator comprises a first buffer for buffering the self refresh signal, and the self signal. And a delay unit for delaying the refresh signal by a predetermined period, and a second logic unit for performing a logic operation on the output signal of the buffer and the output signal of the delay unit and outputting a result thereof.

In the present invention, the second logic unit preferably performs a negative logical operation.

In the present invention, the internal voltage generation circuit further comprises a signal generation unit for generating the enable signal, wherein the signal generation unit logic operation of the signal buffered the active signal and the third control signal and outputs the result of the third Logic section; A second buffer for buffering the self refresh signal; And a fourth logic unit configured to receive an output signal of the third logic unit, an output signal of the second control signal, and an output signal of the second buffer, and output a result of the logic operation.

In the present invention, it is preferable that the third logic unit performs a negative logical product operation and the fourth logic unit performs a logical product operation.

In the present invention, the internal voltage generation unit is provided between the first node and the second node, the first pull-down unit for driving down the second node in response to the reference voltage, the first node and the third node A second pull-down unit disposed between the nodes and pull-down driving the third node in response to a voltage division signal obtained by voltage-dividing the first internal voltage, and installed between the first node and the ground terminal; A switch operating in response to a signal, a first pull-up unit provided between an external voltage terminal and the second node, a second pull-up unit provided between an external voltage terminal and the third node, and in response to a signal of the third node And a third pull-up part for pull-up driving a fourth node and a fourth pull-up part for pull-up driving the output terminal in response to a signal of the fourth node.

In the present invention, it is preferable that the internal voltage generator further includes a voltage divider disposed between the output terminal and the ground terminal to divide the first internal voltage to output the voltage division signal.

In the present invention, the second internal voltage is lower than the first internal voltage.

In the present invention, the second internal voltage is preferably a core voltage used in the core region of the semiconductor memory device.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

FIG. 2 illustrates a configuration of an internal voltage generation circuit VPERI according to an embodiment of the present invention, and FIG. 3 illustrates a configuration of a logic unit that generates a control signal shortb used in the internal voltage generation circuit. Referring to the configuration of the internal voltage generation circuit according to the present embodiment will be described.

The internal voltage generation circuit according to the present embodiment operates in response to a predetermined enable signal (enable), generates an internal voltage VPERI using the predetermined reference voltage VREF, and generates an internal voltage for supplying the output terminal A. Section 10; A first driver P21 for driving the output terminal A to the level of the core voltage VCORE during the self refresh operation section in response to the self refresh signal ref; The output terminal A is connected to an external voltage VDD in response to an initialization section of the semiconductor memory device, a section in which the external voltage VDD is less than or equal to a predetermined voltage level, and a control signal shortb enabled during a predetermined section after completion of the self refresh. A second driver P20 for driving at a level; The logical AND operation of the initialization signal pwrupb of the semiconductor memory device, the control signal bd25 enabled when the external voltage VDD is lower than the predetermined voltage level, and the control signal ref_ext enabled for a predetermined period after the self refresh is completed. A logic unit 20 for generating a control signal shortb; And a signal generator 40 for generating the enable signal.

In addition, as shown in FIG. 1, the internal voltage supply device according to the present embodiment includes at least one internal voltage generation circuit for supplying an internal voltage in an active mode and a self refresh mode; And at least one standby internal voltage generation circuit for supplying the internal voltage in the standby mode, wherein the standby internal voltage generation circuit is turned off in the self refresh mode.

The operation of the internal voltage generating circuit and the internal voltage supply device according to the present embodiment configured as described above will be described in detail with reference to FIGS. 1 to 5, but will be described for each operation mode of the semiconductor memory device. The internal voltage generation circuit according to the present embodiment corresponds to the active internal voltage generation circuits 100 to 300 in the example of FIG. 1 and not only supplies the internal voltage VPERI in the active mode but also the core voltage VCORE in the self refresh mode. ) It is responsible for supplying the level voltage as the internal voltage VPERI. In addition, the standby internal voltage generation circuit corresponds to the standby internal voltage generation circuit 400 in the example of FIG. 1, and the basic structure thereof is substantially the same as the conventional one, except that the standby internal voltage according to the present embodiment is used. The difference is that the generator circuit is turned on in the standby mode and the active mode, but turned off in the self refresh mode. The internal voltage supply device according to the present embodiment includes at least one internal voltage generation circuit and at least one internal voltage generation circuit for standby.

As shown in FIG. 3, the logic unit 20 receives a control signal bd25, an initialization signal pwrupb, and a control signal sref_ext, and performs an AND operation on the control signal shortb to generate a control signal shortb. The 40 receives an active signal, a control signal sref_ext, a control signal bd25, and a self refresh signal sref to generate an enable signal. Here, the control signal bd25 is a level shifting signal according to the voltage level of the external voltage VDD. When the external voltage VDD is larger than a predetermined voltage level, the control signal bd25 is shifted to a high level and smaller than the voltage level. In this case, it is a signal that transitions to a low level. In addition, the initialization signal pwrupb is an initialization signal of the semiconductor memory device. The initialization signal pwrupb is in a low level during a period in which the semiconductor memory device starts to operate for the first time and the external voltage VDD gradually increases, and then is applied to the external voltage VDD. As a result, internal voltage such as VPERI is generated and the memory device can operate properly. The control signal sref_ext is a signal generated by the control signal generator 30 of FIG. 4A to be described later. The control signal sref_ext is a signal that is normally maintained at a high level and then enabled at a low level for a predetermined period after the self refresh mode is completed. In addition, the cell refresh signal sref is a signal indicating whether or not the semiconductor memory device is in a self-refresh operation and is a low level state before and after the self refresh mode is entered and becomes a high level in the self refresh mode.

First, the PMOS P21 is turned off in response to the high level signal because the cell refresh signal sref is in a low level state before entering the self refresh mode. At this time, when the initialization section, i.e., the initialization signal pwrupb is at a low level or the external voltage VDD is lower than the predetermined voltage level and the control signal bd25 is at a low level, the logic unit 20 controls the low level. Since the signal shortb is output, the PMOS P20 is turned on to output the external voltage VDD to the internal voltage VPERI.

Next, in the active mode in which the external voltage VDD is greater than or equal to the predetermined voltage level, the control signal bd25 and the initialization signal pwrupb become the high level in the active mode before the self refresh mode and after the initialization period. active) also becomes a high level. At this time, the self refresh signal sref is at a low level, and the control signal sref_ext is at a high level. Accordingly, since the logic unit 20 receives three signals of high level and outputs a high level control signal shortb, the PMOS P20 is turned off. The PMOS P21 is also turned off in response to the high level signal from the inverter IV11. On the other hand, in the signal generator 40 of FIG. 5, the NAND gate ND23 outputs a high level signal in response to a low level signal from the inverter IV23, and at this time, the control signal bd25 and the inverter IV24. Since the signal from N is also high level, the logic unit 41 outputs an enable signal of high level.

Accordingly, the internal voltage generation unit 10 of FIG. 2 generates an internal voltage VPERI and outputs the internal voltage VPERI. In detail, as the enable signal is enabled to a high level, the NMOS N13 is turned on, and the PMOS P13, PMOS P15, and PMOS P17 are turned off to thereby internal voltage. The generation unit 10 is enabled. The internal voltage generator 10 supplies the internal voltage of the predetermined level to the output terminal A through a comparison operation between the voltage of the node B, which has divided the voltage of the output terminal A, with the reference voltage VREF.

If the voltage at the output terminal A is lower than the predetermined voltage level, the voltage of the node B that divides the voltage is lower than the reference voltage VREF, so that the NMOS N12 is turned on weaker than the NMOS N11 so that the NMOS The turn-on resistance of N12 is greater than that of NMOS N11. Accordingly, since the potential of the node C rises, the turn-on resistance of the PMOS P16 increases, so that the potential of the node D decreases, and the PMOS P18 and the PMOS P19 respond to the potential of the node D. Since the turn-on resistance of) decreases, the potential of the output terminal A rises and the internal voltage VPERI increases. On the contrary, if the voltage of the output terminal A is higher than the predetermined voltage level, the voltage of the node B that divides the voltage becomes higher than the reference voltage VREF, so that the NMOS N12 turns on more strongly than the NMOS N11. As a result, the turn-on resistance of the NMOS N12 is smaller than that of the NMOS N11. As a result, the potential of the node C decreases, so that the turn-on resistance of the PMOS P16 decreases, so that the potential of the node D rises, and the PMOS P18 and the PMOS respond to the potential of the node D. Since the turn-on resistance of (P19) is increased, the potential of the output terminal (A) is finally lowered and the internal voltage VPERI is lowered. As such, the internal voltage generation unit 10 maintains the voltage of the output terminal A constant through the comparison operation as described above, thereby generating the internal voltage VPERI of a constant level in the active mode. Supply through.

In this case, the standby internal voltage generation circuit is turned on not only in the standby mode but also in the active mode to supply the internal voltage.

Subsequently, when the semiconductor memory device enters the self refresh mode, the self refresh signal sref transitions from the low level to the high level. Accordingly, since the logic unit 20 continuously outputs the high level control signal shortb, the PMOS P20 is turned off. However, in the signal generation unit 40 of FIG. The signal generation unit 10 is disabled in FIG. 2 since the low level signal is input from IV24) and the low level enable signal is output through the logical AND operation. That is, as the PMOS P17 is turned on and the node D is at a high level, the PMOS P18 and the PMOS P19 are turned off.

On the other hand, as the self refresh signal sref transitions from the low level to the high level, the PMOS P21 is turned on in response to the low level signal to supply the core voltage VCORE to the output terminal A. FIG. Here, the core voltage VCORE is an internal voltage generated by down converting the external voltage VDD inside the memory device, and is a voltage used in the core (cell array) region of the memory device. Its magnitude is lower than the internal voltage VPERI. As described above, when the semiconductor memory device enters the cell refresh mode, the internal voltage generation circuit according to the present exemplary embodiment outputs the core voltage VCORE whose potential is lower than the existing internal voltage VPERI to the output terminal A. FIG. At this time, the standby internal voltage generation circuit used to supply the internal voltage VPERI in the standby mode is turned off. Accordingly, the internal voltage supply circuit and the internal voltage supply apparatus using the same according to the present embodiment provide a self-refresh by supplying the core voltage VCORE, which is lower than the internal voltage VPERI, in the self-refresh mode as the internal voltage. The current consumption in the mode can be significantly reduced.

On the other hand, when the semiconductor memory device is out of the cell refresh mode, the self refresh signal sref transitions from the high level to the low level. Accordingly, in FIG. 4A, the output of the inverter IV22 is at the high level and the output of the delay unit 31 is maintained at the previous high level for a predetermined delay period, so that the control signal output from the NAND gate ND22 ( sref_ext) becomes a low level signal for a predetermined period. Then, when the delay section by the delay unit 31 has elapsed, the output of the delay unit 31 transitions to the low level, so that the control signal ref_ext output from the NAND gate ND22 transitions to the high level again. As such, when the self refresh mode is completed, the control signal ref_ext becomes a signal that is enabled at a low level for a predetermined period and then transitions back to a high level.

When the control signal sref_ext transitions to the low level during the predetermined period, the PMOS P20 is turned on in FIG. 2 because the control signal shortb, which is an output signal of the logic unit 20 of FIG. 3, is turned low. The output terminal A is driven by an external voltage VDD. In addition, the NAND gate ND23 outputs a high level signal in the signal generation unit 40 of FIG. 5, and the signals from the control signal bd25 and the inverter IV24 are also high level. 41 outputs an enable signal of a high level and the internal voltage generator 10 also starts to operate again. As such, when the self refresh mode is completed, the PMOS P20 and the internal voltage generator 10 may operate together, whereby the internal voltage VPERI, which has been reduced during the self refresh mode, may be quickly returned to the level before the self refresh mode. Make sure

At this time, the standby internal voltage generation circuit is also turned on to generate and output the internal voltage VPERI.

Lastly, when the delay period elapses and the control signal ref_ext transitions back to the high level, the PMOS P20 is turned off, and then the enable signal is enabled depending on whether it is in active mode or not. This determines whether the internal voltage generator 10 operates. That is, in the active mode, the internal voltage generation circuit according to the present embodiment not only supplies the appropriate level of internal voltage VPERI to the output terminal A but also operates the internal voltage generation circuit for standby to supply the internal voltage VPERI. On the other hand, in the standby mode, only the standby internal voltage generation circuit is turned on to supply the internal voltage VPERI.

As such, the internal voltage generation circuit and the internal voltage supply device according to the present embodiment supply a lower level of internal voltage in the self refresh mode than in the active mode and the standby mode, thereby reducing current consumption in the self refresh mode. It is possible to achieve a low power consumption of the semiconductor memory device.

The internal voltage generating circuit and the internal voltage supply device according to the present invention are applicable to the generation of not only the internal voltage VPERI but also any other type of internal voltage.

As described above, the internal voltage generation circuit and the internal voltage supply device according to the present invention supply a lower level of internal voltage than the active mode and the standby mode in the self refresh mode in the semiconductor memory device, The current consumption is reduced to achieve low power consumption of the semiconductor memory device.

Claims (20)

An internal voltage generator configured to operate in response to a predetermined enable signal and generate a first internal voltage using the predetermined reference voltage and supply the first internal voltage to an output terminal; A first driver for driving the output terminal to a level of a second internal voltage during a self refresh operation section in response to a self refresh signal; A second driver configured to drive the output terminal to an external voltage level in response to an initialization section of the semiconductor memory device, a section in which an external voltage is below a predetermined voltage level, and a first control signal enabled for a predetermined section after completion of self refresh. Internal voltage generation circuit configured. The method of claim 1, Generating a first control signal by performing a logical operation on an initialization signal of a semiconductor memory device, a second control signal enabled when an external voltage is below a predetermined voltage level, and a third control signal enabled for a predetermined period after completion of self refresh; An internal voltage generation circuit further comprising a first logic unit. The method of claim 2, And the first logic unit performs an AND operation. The method of claim 2, Further comprising a control signal generation unit for receiving the self-refresh signal to generate the third control signal, The control signal generation unit A first buffer for buffering the self refresh signal; A delay unit for delaying the self refresh signal by a predetermined period; And a second logic unit configured to perform a logic operation on the output signal of the first buffer and the output signal of the delayer, and output a result thereof. The method of claim 4, wherein And the second logic unit performs a negative logical product operation. The method of claim 4, wherein Further comprising a signal generation unit for generating the enable signal, The signal generation unit A third logic unit for performing a logic operation on the signal buffering the active signal and the third control signal and outputting a result thereof; A second buffer for buffering the self refresh signal; And a fourth logic unit configured to receive an output signal of the third logic unit, an output signal of the second control signal, and an output signal of the second buffer, and output a result of the logic operation. The method of claim 6, And the third logic unit performs a negative logical product operation and the fourth logic unit performs a logical product operation. The method of claim 1, The internal voltage generator A first pull-down unit disposed between the first node and the second node and configured to pull-down the second node in response to the reference voltage; A second pull-down unit disposed between the first node and a third node and pull-down driving the third node in response to a voltage distribution signal obtained by voltage-dividing the first internal voltage; A switch installed between the first node and a ground terminal and operating in response to the enable signal; A first pull-up unit disposed between an external voltage terminal and the second node; A second pull-up unit installed between an external voltage terminal and the third node; A third pull-up unit configured to pull-up the fourth node in response to the signal of the third node; And a fourth pull-up part configured to pull-up the output terminal in response to a signal of the fourth node. The method of claim 8, The internal voltage generation circuit further comprises a voltage divider disposed between the output terminal and the ground terminal to divide the first internal voltage to output the voltage division signal. The method of claim 1, And the second internal voltage is lower than the first internal voltage. The method of claim 10, And the second internal voltage is a core voltage used in a core region of a semiconductor memory device. At least one first internal voltage generation circuit for supplying an internal voltage in the active mode and the self refresh mode; At least one second internal voltage generation circuit for supplying the internal voltage in the standby mode is configured, The first internal voltage generation circuit An internal voltage generator configured to operate in response to a predetermined enable signal and generate a first internal voltage using the predetermined reference voltage and supply the first internal voltage to an output terminal; A first driver for driving the output terminal to a level of a second internal voltage during a self refresh operation section in response to a self refresh signal; A second driver configured to drive the output terminal to an external voltage level in response to an initialization section of the semiconductor memory device, a section in which an external voltage is below a predetermined voltage level, and a first control signal enabled for a predetermined section after completion of self refresh. Composed, And the second internal voltage generation circuit is turned off in the self refresh mode. The method of claim 12, The first internal voltage generation circuit performs a logical operation on an initialization signal of the semiconductor memory device, a second control signal enabled when the external voltage is below a predetermined voltage level, and a third control signal enabled for a predetermined period after the self refresh is completed. And an first logic unit configured to generate the first control signal. The method of claim 13, And the first logic unit performs an AND operation. The method of claim 13, The first internal voltage generation circuit further includes a control signal generation unit receiving the self refresh signal and generating the third control signal, The control signal generation unit A first buffer for buffering the self refresh signal; A delay unit for delaying the self refresh signal by a predetermined period; And a second logic unit configured to perform a logic operation on the output signal of the first buffer and the output signal of the delayer, and output a result thereof. The method of claim 15, And the second logic unit performs a negative logical operation. The method of claim 15, The first internal voltage generation circuit further includes a signal generation unit for generating the enable signal, The signal generation unit A third logic unit for performing a logic operation on the signal buffering the active signal and the third control signal and outputting a result thereof; A second buffer for buffering the self refresh signal; And a fourth logic unit configured to receive an output signal of the third logic unit, an output signal of the second control signal, and an output signal of the second buffer, and output a result of the logic operation. The method of claim 17, And the third logic unit performs a negative logical product operation and the fourth logic unit performs a logical product operation. The method of claim 12, And the second internal voltage is lower than the first internal voltage. The method of claim 19, And the second internal voltage is a core voltage used in a core region of a semiconductor memory device.

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