201007890 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種記憶體的製造方法，更特別的是關 於一種快閃記憶體（flash memory)元件的製造方法。 【先前技術】 隨著半導體製程技術的進步，記憶體元件的製程技術 β 也跨入奈米時代。微縮元件尺寸不僅可提高單位面積的積 體電路密度，亦可同時提升元件本身的電流驅動能力，可 謂一舉兩得，然而事實上並非如此。進入奈米時代所帶來 的短通道效應（Short Channel Effects, SCE)及閘極漏電流， 使得以縮減通道長度及微縮閘極氧化層厚度來提升元件的 效能變得越來越困難。 以輕摻雜汲極（Lightly Doped Drain，LDD)而言，可 提兩元件的崩潰電壓（Breakdown Voltage )、改善臨界電壓 魯 的特性、降低熱載子效應（Hot Carrier Effect) 〇雖然輕摻 雜汲極降低了汲極接面的高電場，有效的提升元件的可靠 度’但是隨著元件尺寸的逐漸縮小，貫透（Punch Througli) 現象卻更加嚴重。因此，口袋型佈植（Pocket Implant)結 構就被提出來改善此貫透現象的短通道效應。然而口袋型 佈植雖改善元件的短通道效應，但因為通道高摻雜的緣 故，因此會有没極電流退化（iDSATDegradation)的現象。 因此如何改良該源極、汲極與口袋型佈植區的摻雜程 度與接面外觀（Junction Profile)，以改善以上缺點及取得 5 201007890 * * / 使該元件獲得最高效率的平衡點就變的相當重要。 【發明内容】 本發明的主要目的在提供一種快閃記憶體元件的製造 方法，使載子的產生較接近源極你極於半導縣底中的接 面處，而可增進載子遷移率及增加汲極電流並可進而降低 汲極讀取電壓改善短通道效應（Sh〇rt channel Effects， SCE)。 A達上述目的，本發明係提供一種快閃記憶體元件的 製造方法’其包含：提供一半導體基底；於該半導艘基底 上方形成二閘極結構；於該二閘極結構之間的該半導體基 底中進行一離子佈植製程形成輕摻雜的一第一汲極區於 該二閘極結構之二外側的該半導趙基底中分別形成一輕推 雜源極區，再進行一離子佈植製程，於該二閉極結構之二 外侧的該半導邇基底中分別形成一第一源極區，其中該二 第一源極區與該第一汲極區的摻雜濃度不相同；於該二閘 極結構之間的該半導體基底中，利用一口袋型佈植 Implant)製程於該第—汲極區兩側形成二摻雜區；於該二 閉極結構之間分別形成一L形間隙壁，該二L形間隙壁係 位於該第-沒極區上方；於該L型間隨上沉積一氧化 層’钱刻該氧化層並形成-接觸孔；於該二閘極結構上與 該第/及極區表面各形成一自動對準金屬發化物層 (salicide);進行一離子佈植以於該第 一沒極區下方形成一 第一汲極區，其中該第一與第二汲極區相較於該第一源極 201007890 區具有-陡靖的接面外觀；於該第一沒極區上形成一位障 插栓（barrier plug )。 藉此，本發明之記憶體元件的製造方法能降低汲極讀 取電麗及利用口袋型佈植來改善短通道效應(sh〇rt channel Effects, SCE)。 【實施方式】 為充分瞭解本發明之目的、特徵及功效，茲藉由下述 β 具體之實施例，並配合所附之圖式，對本發明做一詳細說 明，說明於後。在這些不同的圖式與實施例中，相同的元 件將使用相同的符號。 首先參照第一圓，係本發明快閃記憶體元件的部分剖 面圖。圖中顯示於一半導體基底100上形成有二閘極結構 102’該些閘極結構102分別包含：穿隧氧化層l〇2a(tunnel oxide layer)、浮動閘 102b (floating gate)、介電層 l〇2c、 φ 控制閘l〇2d ( control gate)及形成一區域l〇3。該丰導體 基底100材料可為梦、SiGe、絕緣層上覆梦（silicon on insulator，SOI)、絕緣層上覆矽鍺（silicon germanium on insulator，SGOI)、絕緣層上覆錄（germanium on insulator, GOI);於本實施例中，該半導體基底100係為一矽基底。 接著請參照第二圖，於該半導體基底1〇〇上形成一光 罩202，該二閘極結構102間的區域會被該光罩202所涵 蓋。進行一源極離子佈植製程105,於該二閘極結構102 之二外侧的該半導體基底1〇〇中分別形成一第一源極區 201007890 204。以P型為基底的快閃記憶體元件實施例中，該源極離 子佈植製程105中使用的離子為砷，劑量約為1χ1〇ι4〜8χ 1015(ion/cm2)，能量約為 10〜70(Kev)。 接著請同時參照第三圖，進行一離子佈植製程1〇6， 於該二閘極結構102之間的該半導體基底10〇中利用輕摻 雜汲極（Lightly Doped Drain，LDD)佈植形成一第一没極 區302 ’該些第一源極區204與該第一汲極區302係呈不 對稱狀。以P型為基底的快閃記憶體元件實施例中，該離 子佈植製程中使用的離子為坤，劑量約為1χ 〜1X l〇15(ion/cm2)，能量約為 1〇〜3〇(Kev)。 接著請參照第四圖，首先進行一口袋型離子佈植製程 (Pocket Implant)402’於該第一汲極區3〇2的一側形成一 第一摻雜區406。再進行一 口袋型離子佈植製程4〇4，於該 第-汲極區302的另一侧形成一第二摻雜區4〇8。該口袋 型離子佈植製程402及口袋型離子佈植製程4〇4僅入射方 向不同，其餘離子佈植參數大致上皆相同，且與該半導體 基底1〇〇之間的入射角度約為15°〜60。。該些口袋型離子 :植能限健下來汲_子佈植製財，離子的側向擴 。P型為基底的快閃記憶體元件實施例中，該口袋型離 佈植製程402 ’ 404中使用的離子為删或二氟化蝴（B或 2)’劑量約為5χ1〇12〜5xl0u(i〇n/cm2)，能量約為1〇〜 〇0(Kev) 〇 接著請參照第五圖，形成—第—氧化層壁5gi及一第 —氣切層502,再利用―習知的沉積技術，如：來源氣 201007890 艘包含NH3及SilLj的化學氣相沉積法（CVD)、快速熱退 火化學氣相沉積（rapid thermal chemical vapor deposition, RTCVD )、原子層沉積（at〇mic layer deposition，ALD )，沉 積一氧化層504。該氧化層504的厚度可介於200 A至1500 A，在本實施例中為750 A。 接著請同時參照第五圖及第六圖，利用乾式或濕式蝕 刻進行一蝕刻製程將該氧化層504蝕刻成複數個氧化層間 隔物（Oxide spacer) 602a〜d。再進行另一蝕刻製程，將 .❹ 該第一氣化梦層502蚀刻成二L形間隙壁（L-shape ) 604a、 604b及钱刻該第一氧化層壁501。最後經汲極離子佈植製 程606於該第一汲極區302下形成一第二汲極區608，其 中該第一汲極區302與該第二汲極區608的接面外觀 (junction profile)是陡峭的，且與該些第一源極區204的 平滑接面外觀不同。如此，由於汲極區不具有源極區的平 滑接面外觀，使得載子的產生較接近接面處而可增進載子 參 遷移率及增加汲極電流。 接著請參閱第七囷，於表面形成一由钻（cobalt, Co )、 鈦（titanium，Ti)、錄（nickel, Ni)或麵（molybdenum, Mo) 所構成之金屬矽化物層，並且進行一快速熱退火處理製 程，以形成一自動對準金屬矽化物層702a、702b與702c (salicidelayer)，用以降低寄生電阻提昇元件驅動力。 接著請參閱第八圖，接續上述步驟，於該半導體基底 100上沉積一接觸孔蝕刻停止層802( contact etch stop layer, CESL ) ’其可為siN、氮氧化梦（oxynitride )、氧化發（〇xide ) 9 201007890 等，在本實施例中為SiN。該接觸孔蝕刻停止層8〇2的沉 積厚度為100至1500 A。接著，一層間介電質層8〇4 (inter-layer dielectric，ILD)，如：二氡化矽 si〇2，沉積在 該接觸孔蝕刻停止層802之上。 最後請參閱第九圖，利用習知的光阻光罩製程，將一 接觸孔902從該層間介電質層804非均向性地蝕刻到該接 觸蝕刻停止層802。再沉積一位障插栓9〇4 (barrierplug) 形成一如第六圖所示之快閃記憶體元件。 本發明在上文中已以較佳實施例揭露，然熟習本項技⑩ 術者應理解的是’該實施例僅用於描繪本發明中記憶體單 元的一部分結構，而不應解讀為限制本發明之範園。應注 意的是，舉凡與該實施例等效之變化與置換，均應設為涵 蓋於本發明之範_内。因此，本發明之保護範圍當以下文 之申請專利範圍所界定者為準。 【圓式簡單說明】 第一圖到第九圖係顯示在不同製程步驟時，本發明的❹ 快閃記憶體元件刮面圖。 【主要元件符號說明】 100 半導體基底 102 閘極結構 102a 穿隧氧化層 102b 浮動閘 201007890201007890 IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a memory, and more particularly to a method of manufacturing a flash memory element. [Prior Art] With the advancement of semiconductor process technology, the process technology of memory devices has also entered the nanometer era. The size of the miniature component not only increases the density of the integrated circuit per unit area, but also enhances the current driving capability of the component itself, which is a two-pronged approach, but it is not. The short channel effects (SCE) and gate leakage currents brought into the nanometer era make it increasingly difficult to reduce the channel length and the thickness of the miniature gate oxide layer to improve the performance of the device. In the case of Lightly Doped Drain (LDD), the Breakdown Voltage of the two components can be improved, the characteristics of the threshold voltage can be improved, and the Hot Carrier Effect can be reduced. Although lightly doped The bungee pole reduces the high electric field of the bungee junction and effectively improves the reliability of the component'. However, as the component size shrinks, the Punch Througli phenomenon becomes more serious. Therefore, the Pocket Implant structure has been proposed to improve the short channel effect of this penetration phenomenon. However, pocket-type implants improve the short-channel effect of components, but because of the high doping of the channels, there is a phenomenon of iDSAT degradation. Therefore, how to improve the doping degree and junction appearance of the source, bungee and pocket implant areas to improve the above disadvantages and achieve 5 201007890 * * / The balance point of the highest efficiency of the component is changed Very important. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for manufacturing a flash memory device, such that the carrier is generated closer to the source than the junction in the bottom of the semi-conductor, and the carrier mobility can be improved. And increase the drain current and can further reduce the drain read voltage to improve the short channel effect (SCE). A. The present invention provides a method for fabricating a flash memory device, which includes: providing a semiconductor substrate; forming a two-gate structure over the semiconductor substrate; and between the two gate structures Performing an ion implantation process in the semiconductor substrate to form a lightly doped first drain region, respectively forming a nudged source region in the semiconductor substrate outside the two gate structures, and then performing an ion a first source region is formed in the semiconductor substrate outside the two of the two closed-pole structures, wherein the doping concentrations of the first source region and the first drain region are different In the semiconductor substrate between the two gate structures, a two-doped region is formed on both sides of the first drain region by using a pocket-type implant process; and a second doped region is formed between the two gate structures An L-shaped spacer, the two L-shaped spacers are located above the first-nothotropic region; and an oxide layer is deposited between the L-types to form the oxide layer and form a contact hole; and the two gate structures are formed Forming an automatic alignment metal on the surface of the upper/pole region a salicide layer; performing an ion implantation to form a first drain region under the first non-polar region, wherein the first and second drain regions have a region compared to the first source 201007890 region a steep junction appearance; forming a barrier plug on the first non-polar region. Thereby, the method of manufacturing the memory device of the present invention can reduce the bungee reading and the use of pocket implants to improve the short channel effect (SCE). DETAILED DESCRIPTION OF THE INVENTION In order to fully understand the objects, features, and advantages of the present invention, the present invention will be described in detail by the following specific embodiments, and the accompanying drawings. In these different figures and embodiments, the same elements will use the same symbols. Referring first to the first circle, a partial cross-sectional view of the flash memory component of the present invention is shown. The gate structure 102 includes a tunnel oxide layer, a floating gate 102b, and a dielectric layer. L〇2c, φ control gate l〇2d (control gate) and form an area l〇3. The material of the abundance conductor substrate 100 can be a dream, a SiGe, a silicon on insulator (SOI), a silicon germanium on insulator (SGOI), a germanium on insulator (germanium on insulator, In the present embodiment, the semiconductor substrate 100 is a germanium substrate. Referring to the second figure, a reticle 202 is formed on the semiconductor substrate 1b, and the area between the two gate structures 102 is covered by the reticle 202. A source ion implantation process 105 is performed, and a first source region 201007890 204 is formed in the semiconductor substrate 1 外侧 outside the two of the two gate structures 102, respectively. In the embodiment of the P-type flash memory device, the ion used in the source ion implantation process 105 is arsenic, and the dose is about 1χ1〇ι4~8χ1015 (ion/cm2), and the energy is about 10~ 70 (Kev). Then, referring to the third figure, an ion implantation process 1〇6 is performed, and the light-emitting doped drain (LDD) is implanted in the semiconductor substrate 10〇 between the two gate structures 102. The first source region 204 and the first source region 302 are asymmetric with respect to the first gate region 302. In the embodiment of the P-type flash memory device, the ion used in the ion implantation process is Kun, and the dose is about 1χ~1X l〇15 (ion/cm2), and the energy is about 1〇~3〇. (Kev). Next, referring to the fourth figure, a Pocket Implant 402' is first formed on the side of the first drain region 3〇2 to form a first doping region 406. Further, a pocket type ion implantation process 4〇4 is performed, and a second doping region 4〇8 is formed on the other side of the first drain region 302. The pocket type ion implantation process 402 and the pocket type ion implantation process 4〇4 have different incident directions only, and the remaining ion implantation parameters are substantially the same, and the incident angle with the semiconductor substrate 1〇〇 is about 15°. ~60. . These pocket-type ions: the plant energy limit is healthy 汲 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In the embodiment of the P-type substrate flash memory device, the ion used in the pocket type from the implant process 402 '404 is a deletion or a difluorination butterfly (B or 2) dose of about 5χ1〇12~5x10u ( I〇n/cm2), the energy is about 1 〇~ 〇0 (Kev) 〇 Next, refer to the fifth figure to form the first-oxide layer 5gi and a first gas-cut layer 502, and then use the conventional deposition. Technology, such as: source gas 201007890 Chemical vapor deposition (CVD) including NH3 and SilLj, rapid thermal chemical vapor deposition (RTCVD), atomic layer deposition (ALD) ), an oxide layer 504 is deposited. The oxide layer 504 may have a thickness of between 200 A and 1500 A, and in this embodiment, 750 A. Next, referring to the fifth and sixth figures, the oxide layer 504 is etched into a plurality of Oxide spacers 602a-d by an etching process using dry or wet etching. Another etching process is performed to etch the first vaporized dream layer 502 into two L-shaped spacers (L-shape) 604a, 604b and the first oxide layer wall 501. Finally, a second drain region 608 is formed under the first drain region 302 via the bungee ion implantation process 606, wherein the junction profile of the first drain region 302 and the second drain region 608 (junction profile) ) is steep and has a different appearance from the smooth junction of the first source regions 204. Thus, since the drain region does not have the appearance of the smooth junction of the source region, the generation of the carrier is closer to the junction, which can increase the carrier mobility and increase the gate current. Next, please refer to the seventh layer to form a metal telluride layer composed of diamond (Co), titanium (titanium, Ti), nickel (Ni) or molybdenum (Mo) on the surface, and carry out a The rapid thermal annealing process is performed to form an auto-alignment metal halide layer 702a, 702b and 702c (salicide layer) for reducing the driving force of the parasitic resistance lifting element. Next, referring to the eighth figure, following the above steps, a contact etch stop layer 802 (CESL) is deposited on the semiconductor substrate 100. It can be a siN, an oxynitride, or an oxidized hair. Xide ) 9 201007890 etc., in this embodiment, is SiN. The contact hole etch stop layer 8〇2 has a deposition thickness of 100 to 1500 Å. Next, an inter-layer dielectric (ILD), such as an inter-layer dielectric (ILD), is deposited over the contact hole etch stop layer 802. Finally, referring to the ninth figure, a contact hole 902 is non-uniformly etched from the interlayer dielectric layer 804 to the contact etch stop layer 802 by a conventional photoresist mask process. A barrier plug 9 〇 4 (barrierplug) is deposited to form a flash memory component as shown in FIG. The present invention has been disclosed in the above preferred embodiments, and it should be understood by those skilled in the art that the embodiment is only used to describe a part of the structure of the memory unit in the present invention, and should not be construed as limiting the present invention. The invention of the park. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be within the scope of the invention. Therefore, the scope of the invention is defined by the scope of the following claims. [Circular Simple Description] The first to ninth drawings show the scratched surface of the 快 flash memory device of the present invention at different process steps. [Main component symbol description] 100 Semiconductor substrate 102 Gate structure 102a Tunneling oxide layer 102b Floating gate 201007890
102c 介電層 102d 控制閘 103 區域 105 源極離子佈植製程 106 離子佈植製程 202 光罩 204 第一源極區 302 第一沒極區 402 口袋型離子佈植製程 404 口袋型離子佈植製程 406 第一掺雜區 408 第二摻雜區 501 第一氧化層壁 502 第二氮化矽層 504 氧化層 602a、 -d 氧化層間隔物 604a L 形間隙壁 604b L 形間隙壁 606 汲極離子佈植製程 608 第二汲·極區 702a- -c 自動對準金屬矽化物層 802 接觸孔蝕刻停止層 11102c dielectric layer 102d control gate 103 region 105 source ion implantation process 106 ion implantation process 202 photomask 204 first source region 302 first non-polar region 402 pocket ion implantation process 404 pocket ion implantation process 406 first doped region 408 second doped region 501 first oxide layer wall 502 second tantalum nitride layer 504 oxide layer 602a, -d oxide layer spacer 604a L-shaped spacer 604b L-shaped spacer 606 The implantation process 608 the second electrode region 702a--c automatically aligns the metal germanide layer 802 the contact hole etch stop layer 11