TW201003871A - Package substrate - Google Patents

Package substrate Download PDF

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Publication number
TW201003871A
TW201003871A TW97126240A TW97126240A TW201003871A TW 201003871 A TW201003871 A TW 201003871A TW 97126240 A TW97126240 A TW 97126240A TW 97126240 A TW97126240 A TW 97126240A TW 201003871 A TW201003871 A TW 201003871A
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TW
Taiwan
Prior art keywords
layer
package substrate
dielectric layer
metal plate
gold
Prior art date
Application number
TW97126240A
Other languages
Chinese (zh)
Inventor
Shih-Ping Hsu
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW97126240A priority Critical patent/TW201003871A/en
Priority to US12/495,191 priority patent/US8188379B2/en
Publication of TW201003871A publication Critical patent/TW201003871A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

Provided is a package substrate including a core board and a metal board. The core board has a first surface, a second surface opposing the first surface, and a through hole penetrating the first and second surfaces. The first surface has a plurality of wire-bonding pads formed thereon and flush therewith. The second surface has a plurality of ball-implanting pads formed thereon and flush therewith. The metal board corresponds in position to the through hole, is disposed on the second surface of the core board, is flush with the second surface, and is thicker than the ball-implanting pads. Subsequently, a semiconductor chip can be mounted on the metal board exposed from the through hole, so as to reduce package height and dissipate heat.

Description

201003871 九、發明說明： 【發明所屬之技術領域】 本發明係有關於—種半導體封裝基板，尤指—種具有 開口之封裝基板。 , 【先前技術】 - 目雨業界為滿足半導體封裝件高積集度 (Integi at ion)及微型化（Miniaturizati〇n)的封裝需 求’且為豕提昇單一半導體封裝件之性能（abiUty)與容 ί置（capac ity)以符合電子產品小型化、大容量與高速化之 趨勢，係發展出半導體晶片之堆疊技術。 請參閱第1A圖，一般具有堆疊技術之半導體封裝件 係將一第一半導體晶片u以覆晶式（FlipChip)電性連接 於一基板ίο之一表面10a，且於該基板10之另一表面1〇b 設置供外接其他電子裝置之焊料球丨2，並於該第一半導 體晶片11上接置至少一第二半導體晶片13,且該第二半 ，‘體日日片13以打線式（wi re bond i ng)，即藉由導線14 電性連接至該基板1 〇，並於該基板丨〇上形成包覆該第— 及弟一半導體晶片11，13之封裝材15。 然，因該第一及第二半導體晶片11，13均電性連接同 一基板1 0，若其中一半導體晶片故障，將導致半導體封 裝件整體失效，而浪費成本。 請參閱第1B圖，為解決上述之問題，遂發展堆疊封 裝（Package 〇n Package ’ POP)技術，以提供另一種半 導體封裝件，係包括至少二封裝件16，各該封裝件16之 5 110858 201003871 間籍由導電元件17電性堆疊；其中，該封裝件1 6具有一 基板丨6 0、設於該基板1 6 0上並以打線式電性連接至該基 板160之半導體晶片161、以及覆設於部份之基板160上 且覆蓋該半導體晶片1 61之封裝材162，且該導電元件17 設於該基板160上；另外，於最下層之基板160之相對堆 疊之一側設有供外接其他電子裝置之焊料球1 63。 惟，各該封裝件16的高度係為該基板16 0及封裝材 162的高度總和，俾使堆疊封裝（POP)之半導體封裝件高 ，度過高，不易製成輕薄短小之裝置，因而使電子產品的應 用受限。 因此，如何解決上述習知半導體封裝件的問題，實為 目前亟欲解決的課題。 【發明内容】 鑑於上述習知技術之種種缺失，本發明之一目的在於 提供一種能降低封裝高度之封裝基板。 本發明之另一目的在於提供一種具散熱功能之封裝 I , '基板。 為達上述及其它目的，本發明揭露一種封裝基板，係 包括：核心板，係具有相對之第一表面及第二表面，於該 第一表面上具有複數打線墊並與該第一表面齊平，於該第 二表面具有複數植球墊並與該第二表面齊平，且具有貫穿 該第一及第二表面之開口；以及金屬板，係設於該核心板 之第二表面，並對應該開口，且與該第二表面齊平，該金 屬板之厚度係大於該植球墊之厚度，以供承載之用。 6 110858 201003871 依上述之封裝基板，該核心板係為兩層或多層線路 板；該金屬板係為銅，且該金屬板係顯露在該開口中。 依上述之結構，復包括防焊層，係分別設於該核心板 之第一表面及第二表面上，該第一表面之防焊層具有對應 , 該開口之防焊層開口，且該些防焊層具有複數開孔，以對 應露出各該打線墊、金屬板及植球墊，又於該防焊層開口 中之打線墊上設有表面處理層，該表面處理層係為化鎳/ 金（Ni/Au)、電鍍鎳/金（Ni/Au)、化鎳鈀浸金（ENEPIG)或 f 化錄自催化金（ENAG)。 本發明復提供一種封裝基板，係包括：核心板，係具 有相對之第一表面及第二表面，於該第一表面及第二表面 分別具有介電層，且該第一表面之介電層上具有複數打線 墊，於該第二表面之介電層上具有複數植球墊，且具有貫 穿該介電層、第一表面及第二表面之開口；金屬板，係設 於該核心板之第二表面之介電層上，並對應該開口，該金 屬板之厚度係大於該植球墊之厚度，以供承載之用。 ί 、 依上述之封裝基板，該核心板係為兩層或多層線路 板；該金屬板係為銅，且該開口中之金屬板係為該介電層 所覆蓋。 依上述之結構，復包括防焊層，係分別設於該核心板 之第一表面及第二表面的介電層上，該第一表面之防焊層 具有對應該開口之防焊層開口，且該些防焊層具有複數開 孔，以對應露出各該打線墊、金屬板及植球墊，於該防焊 層開口中之打線墊上設有表面處理層，該表面處理層係為 7 110858 201003871 化鎳/金（Ni/Au)、電鍍鎳/金（Ni/Au)、化鎳鈀浸金（ENEPIG) 或化鎳自催化金（ENAG)。 本發明再提供一種封裝基板，係包括：核心板，係具 有相對之第一表面及第二表面，於該第一表面及第二表面 ,分別具有介電層，且該第一表面之介電層中具有複數打線 墊，該打線墊並與該介電層表面齊平，於該第二表面之介 電層上具有複數植球墊，該植球墊並與該介電層表面齊 平，且具有貫穿該介電層、第一表面及第二表面之開口； 『金屬板，係設於該核心板之第二表面的介電層中並與該介 電層表面齊平，且對應該開口，該金屬板之厚度係大於該 植球墊之厚度，以供承載之用。 依上述之封裝基板，該核心板係為兩層或多層線路 板；該金屬板係為銅，且該開口中之金屬板係為該介電層 所覆蓋。 依上述之結構，復包括防焊層，係設於該核心板之第 一表面及第二表面的介電層上，該防焊層具有對應該開口 ν之防焊層開口，且該些防焊層具有複數開孔，以對應露出 各該打線墊、金屬板及植球塾，於該防焊層開口中之打線 塾上設有表面處理層，該表面處理層係為化錄/金 (Ni/Au)、電鍍鎳/金（Ni/Au)、化鎳鈀浸金（ENEPIG)或化 錄自催化金（ENAG)。 本發明之封裝基板具有開口，並藉由半導體晶片置入 開口中，以降低整體之封裝高度；另外，該金屬板之厚度 係大於該植球塾之厚度，使該半導體晶片穩固設於金屬板 8 110858 201003871 上，且利用金屬材質導熱性佳之特性，俾使半導體晶片藉 .由金屬板散熱’以達到具散熱功能之目的。 . 【實施方式】 以下耩由特定的具體實施例說明本發明之實施方 ^式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 請蒼閱第2A至2C圖，係為本發明之封裝基板之剖面 示意圖。 f 士。第2A圖所示，本發明之封裝基板係包括有核心板 \ 20及金屬板21，該核心板2〇係為兩層或多層線路板並具 有τ目對之第一表面20a及第二表面2〇b，於該第一表面2〇a 上設有複數打線墊201，該打線墊2〇1係設於該第一表面 20a中並與該第一表自2〇a齊平，又於該第二表面挪上 設有複數植球塾202，該植球塾2〇2係設於該第二表面_ 中並與該第二表面2〇b齊平，且具有貫穿該第一表面心 及第二表面20b之開口 200;於該核心板2〇之第二表面 一 τ Η1、之金屬板21，並與該第二表面2〇b :Γ=Τ開口 200之一端，使該金屬板21顯露在該 厂:度，以供4:用金屬板21之厚度大於該植球购之 上又於„玄罘—及第二表面2〇心2仳上設有防焊層U，201003871 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor package substrate, and more particularly to a package substrate having an opening. [Prior Art] - To meet the packaging requirements of semiconductor package high-integration and miniaturization, and to improve the performance (abiUty) and capacity of a single semiconductor package ίCapacity is in line with the trend of miniaturization, large capacity and high speed of electronic products, and the development of stacking technology for semiconductor wafers. Referring to FIG. 1A, a semiconductor package having a stacking technology is electrically connected to a first semiconductor wafer u by a FlipChip to a surface 10a of a substrate, and to the other surface of the substrate 10. 1〇b is provided for soldering the solder balls 2 of other electronic devices, and at least one second semiconductor wafer 13 is attached to the first semiconductor wafer 11, and the second half, the body day 13 is in a wire type ( Wi re bond i ng), which is electrically connected to the substrate 1 by wires 14, and a package 15 covering the first and second semiconductor wafers 11, 13 is formed on the substrate. However, since the first and second semiconductor wafers 11, 13 are electrically connected to the same substrate 10, if one of the semiconductor wafers fails, the semiconductor package is completely failed, which is costly. Referring to FIG. 1B, in order to solve the above problem, a package package (POP) technology is developed to provide another semiconductor package, which includes at least two packages 16, each of which is a package of 5, 110,858. The semiconductor device 161 has a substrate 丨60, a semiconductor wafer 161 disposed on the substrate 160 and electrically connected to the substrate 160, and The package material 162 is disposed on a portion of the substrate 160 and covers the semiconductor wafer 161, and the conductive element 17 is disposed on the substrate 160. In addition, one side of the opposite stack of the lower substrate 160 is provided. Solder balls 1 63 of other electronic devices. However, the height of each of the packages 16 is the sum of the heights of the substrate 160 and the package 162, so that the semiconductor package of the stacked package (POP) is high and too high, and it is not easy to be made into a thin and light device. The use of electronic products is limited. Therefore, how to solve the above problems of the conventional semiconductor package is a problem that is currently being solved. SUMMARY OF THE INVENTION In view of the above various deficiencies of the prior art, it is an object of the present invention to provide a package substrate capable of reducing the package height. Another object of the present invention is to provide a package I, 'substrate with heat dissipation function. To achieve the above and other objects, the present invention discloses a package substrate comprising: a core plate having opposite first and second surfaces, and having a plurality of wire pads on the first surface and flush with the first surface Having a plurality of ball pads on the second surface and being flush with the second surface, and having openings through the first and second surfaces; and a metal plate attached to the second surface of the core plate It should be open and flush with the second surface, the thickness of the metal plate being greater than the thickness of the ball pad for carrying. 6 110858 201003871 According to the above package substrate, the core plate is a two-layer or multi-layer circuit board; the metal plate is copper, and the metal plate is exposed in the opening. According to the above structure, the solder resist layer is respectively disposed on the first surface and the second surface of the core board, the solder resist layer of the first surface has a corresponding, the solder resist layer opening of the opening, and the The solder resist layer has a plurality of openings for exposing each of the wire bonding pads, the metal plate and the ball pad, and a surface treatment layer is disposed on the wire bonding pad in the opening of the soldering layer, the surface treatment layer is nickel/gold (Ni/Au), electroplated nickel/gold (Ni/Au), nickel-palladium immersion gold (ENEPIG) or f-catalyzed gold (ENAG). The present invention further provides a package substrate, comprising: a core plate having opposite first and second surfaces, respectively having a dielectric layer on the first surface and the second surface, and a dielectric layer on the first surface a plurality of wire bonding pads having a plurality of ball-forming pads on the dielectric layer of the second surface and having openings through the dielectric layer, the first surface and the second surface; and a metal plate disposed on the core plate On the dielectric layer of the second surface, the opening should be open, and the thickness of the metal plate is greater than the thickness of the ball pad for carrying. According to the above package substrate, the core plate is a two-layer or multi-layer circuit board; the metal plate is made of copper, and the metal plate in the opening is covered by the dielectric layer. According to the above structure, the solder resist layer is respectively disposed on the dielectric layer of the first surface and the second surface of the core board, and the solder resist layer of the first surface has a solder mask opening corresponding to the opening. And the solder mask has a plurality of openings to correspondingly expose the wire pads, the metal plate and the ball pad, and a surface treatment layer is disposed on the wire pad in the opening of the solder resist layer, the surface treatment layer is 7 110858 201003871 Nickel/gold (Ni/Au), electroplated nickel/gold (Ni/Au), nickel-palladium immersion gold (ENEPIG) or nickel self-catalyzing gold (ENAG). The present invention further provides a package substrate, comprising: a core plate having opposite first and second surfaces, wherein the first surface and the second surface respectively have a dielectric layer, and the first surface is dielectric The layer has a plurality of wire bonding pads, and the wire bonding pad is flush with the surface of the dielectric layer, and has a plurality of ball-forming pads on the dielectric layer of the second surface, and the ball-pads are flush with the surface of the dielectric layer. And having an opening through the dielectric layer, the first surface and the second surface; "a metal plate is disposed in the dielectric layer of the second surface of the core plate and is flush with the surface of the dielectric layer, and corresponds to The opening, the thickness of the metal plate is greater than the thickness of the ball pad for carrying. According to the above package substrate, the core plate is a two-layer or multi-layer circuit board; the metal plate is made of copper, and the metal plate in the opening is covered by the dielectric layer. According to the above structure, the solder resist layer is disposed on the dielectric layer of the first surface and the second surface of the core board, and the solder resist layer has a solder resist opening corresponding to the opening ν, and the anti-solder layer The soldering layer has a plurality of openings for exposing each of the wire bonding pads, the metal plate and the ball raft, and a surface treatment layer is disposed on the wire sill in the opening of the soldering layer, and the surface treatment layer is a chemical recording/gold ( Ni/Au), electroplated nickel/gold (Ni/Au), nickel-palladium immersion gold (ENEPIG) or chemically-catalyzed gold (ENAG). The package substrate of the present invention has an opening and is placed in the opening by the semiconductor wafer to reduce the overall package height; in addition, the thickness of the metal plate is greater than the thickness of the bulb, so that the semiconductor wafer is stably disposed on the metal plate. 8 110858 201003871, and the use of metal materials with good thermal conductivity, so that the semiconductor wafer borrowed from the metal plate to 'heat dissipation' to achieve the purpose of heat dissipation. [Embodiment] The following is a description of the embodiments of the present invention, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. Please refer to Figures 2A to 2C for a cross-sectional view of the package substrate of the present invention. f 士. As shown in FIG. 2A, the package substrate of the present invention comprises a core board 20 and a metal board 21, and the core board 2 is a two-layer or multi-layer circuit board and has a first surface 20a and a second surface opposite to each other. 2〇b, a plurality of wire mats 201 are disposed on the first surface 2〇a, and the wire mats 2〇1 are disposed in the first surface 20a and are flush with the first table from 2〇a, The second surface is provided with a plurality of bulbs 202 disposed in the second surface _ and flush with the second surface 2〇b and having a first surface And an opening 200 of the second surface 20b; a metal plate 21 on the second surface of the core plate 2b, and a metal plate 21 on the second surface 2b: Γ=Τ opening 200, the metal plate 21 is exposed in the factory: degree, for 4: the thickness of the metal plate 21 is greater than that of the plant ball, and the solder mask layer U is provided on the 玄玄罘 and the second surface 2〇2仳,

並具有對應該開’2〇0之防輝層開D ==物2具有複數開孔⑵，以對應露出各該 、'，墊 、孟屬板2]及植球墊2〇2。 110858 9 201003871 另於該打線墊201上設有表面處理層201ei，該表面 - 處理層2 01 a係為化錄/金（N i / Au，係先形成錄，之後再形 ， 成金）、電鍍鎳/金（Ni/Au)、化鎳鈀浸金（Electroless Nickel/Electroless Pal ladium/Immersion Gold，ENEPIG) 或化鎳自催化金（Electroless Nickel Autocatiytic Gold, ENAG)。 如第2B圖所示，該核心板20係為兩層或多層線路 板，且於该核心板2〇之第一表面20a及第二表面2〇b分 別具有介電層204之實施結構，該打線墊2〇1係設於該第 一表面20a之介電層204上，而該植球墊2〇2及金屬板 21係設於該第二表面2〇b之介電層204上，又該金屬板 2—1係對應於封裝基板開口 2〇〇 ,並為該介電層2〇4所覆 益，且於該第一表面20a及第二表面20b的介電層204 上刀別设有防焊層22，而該第一表面2〇a之防焊層22並 具有對應該開口 200之防焊層開口 22〇，該防焊層θ22並 %. K . 具有複數開孔2 21，以對庫露屮久兮4 6 了愿路出各忒打線墊201、金屬板 “ 1及植球墊2 0 2 ，且該今Μ姑？Ί m + mg板21之厚度大於該植球墊 之尽度，以供承載之用。 如第2C圖所示，該核心板係為 板，於該核心板20之第一表面層線路 具有介電層2〇4之另一本 又〇b分別 第-表面20a之介帝二;: 2〇1係設於該 電声2〇4=ί: 中，並與該第-表⑽之介 甸曰204表面背平，而該植球墊 該第二声而—人 及孟屬板21係設於 乐一表面20b之介電層2〇4 τ 且與该弟一表面20b 110858 10 201003871 之介電層2〇4表面齊平，又該金屬板幻係對庫於封壯美 .-開口 _，並為該介電層2〇4所覆蓋，且該金屬板A .之厚度^於該植球墊2〇2之厚度，以供承載之用。 請參閱帛3圖，提供-係如帛2A圖所示之封f .於该核心板20之開口 2〇〇中的金屬板2ι上 土 _ =曰片23’該半導體晶片23具有相對之作用面 :面饥，於該作用面23a上具有複數電極墊231，= =導體晶片23以該非作用面娜藉由黏著 I:…之金屬板21上，並藉由導線25電性連。 核心板之打線墊201 ;因該金屬板21之厚I : 植球墊202之厚度h，使該半 ；δΛ 於該金屬板2 i上，且藉由二=穩固設置 _ ,, 曰甶該金屬板21導熱性佳的特性， 俾=+v體晶片23藉由該金屬板21以達散熱之作用； =該核心板20之第一表面2〇a上的部份防焊㈣上形 紂裝材26，且該封裝材26並填充於該開口 2⑽中，And having an anti-glare layer corresponding to the opening of '2〇0, D == object 2 has a plurality of openings (2) to correspondingly expose each of the ', pad, Meng board 2' and the ball pad 2〇2. 110858 9 201003871 In addition, the surface pad 201 is provided with a surface treatment layer 201ei, which is a recording/gold (N i / Au, which is formed first, then formed, into gold), electroplating Nickel/gold (Ni/Au), Electroless Nickel/Electroless Pal ladium/Immersion Gold (ENEPIG) or Electroless Nickel Autocatiytic Gold (ENAG). As shown in FIG. 2B, the core board 20 is a two-layer or multi-layer circuit board, and the first surface 20a and the second surface 2〇b of the core board 2 have an implementation structure of a dielectric layer 204, respectively. The wire pad 2〇1 is disposed on the dielectric layer 204 of the first surface 20a, and the ball pad 2〇2 and the metal plate 21 are disposed on the dielectric layer 204 of the second surface 2〇b, The metal plate 2-1 corresponds to the opening of the package substrate 2, and is beneficial to the dielectric layer 2〇4, and is disposed on the dielectric layer 204 of the first surface 20a and the second surface 20b. There is a solder resist layer 22, and the solder resist layer 22 of the first surface 2A has a solder resist opening 22 corresponding to the opening 200, and the solder resist layer θ22 and %. K. has a plurality of openings 2 21, With the pair of Kulu 屮 兮 兮 4 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 As shown in FIG. 2C, the core board is a board, and the first surface layer line of the core board 20 has another dielectric layer 2〇4, respectively. The first surface 20a of the Emperor II;: 2〇1 is set in the electroacoustic 2〇4=ί: and is flattened with the surface of the second table of the first table (10), and the ball pad is the second sound and the human and the Meng board 21 The dielectric layer 2〇4 τ is disposed on the surface 20b of the Le-one surface and is flush with the surface of the dielectric layer 2〇4 of the surface 20b 110858 10 201003871 of the first surface, and the metal plate is symmetrical to the library. The opening _ is covered by the dielectric layer 2〇4, and the thickness of the metal plate A is the thickness of the ball pad 2〇2 for carrying. Please refer to 帛3, provide-- The sealing plate shown in FIG. 2A is a metal plate 2 ι in the opening 2 of the core plate 20. The semiconductor wafer 23 has a relative action surface: face hunger, on the action surface. 23a has a plurality of electrode pads 231, = = conductor wafer 23 is adhered to the metal plate 21 of the I:... by the non-acting surface, and is electrically connected by the wires 25. The core pad of the core board 201; Thickness of 21: The thickness h of the ball pad 202 makes the half; δ Λ on the metal plate 2 i, and by the second = stable setting _ , the metal plate 21 has good thermal conductivity characteristics, 俾 = +v body wafer 23 by the gold Plate 21 of the heat-sink; (iv) = upper portion of the solder resist on the first surface of the core board 20 of 2〇a Zhou shaped timber 26 installed, and the encapsulating material 26 is filled in the opening and 2⑽,

I ^包覆該半導體晶片23、導線25及打線塾2Gi ;又於該 亥〜板2G之第二表面2Qb側的防焊層22，於該防焊層μ 之開孔221中的金屬板21及植球塾2〇2上接置焊料球 u27 ’以構成—封裝件，其中接置於該金屬板21上的 知料球27,係供散熱用’而接置於該植球藝2〇2上之焊料 Τ 27係供外接其他電子裝置，例如印刷電路板，該封裝 彳亦可外接另_封裝件，以構成堆疊封裝（)結構。 本發明之封裝基板具有開口，並藉由將半導體晶片容 置於該開口中’以降低整體之封裝高度；另外，該金屬板 110858 11 201003871 之厚度係大於該植球墊之厚度，使該半導體晶片穩固 坌屬板上，且利用金屬材質導熱性佳之特性，俾伸士遂、 晶片藉由金屬板散熱，以達到具散熱功能之目的。版 综上所述，本發明藉由半導體晶片置入核心板之開口 .中，使±要結構高度僅為核心板的高度，而$需考量 ..體晶片高度，有效達到降低高度之目的；另外，藉由 銅且較厚的金屬板作為承載半導體晶片之元件，二堇= %，且達到具散熱功能之目的。 戟 上述實施例係用以例示性說明本發明之原理及 效’而非用於限制本發明。任何熟習此項技藝之人士^可 在不違背本發明之精神及料下，對上述實施例進行修 改。因此本發明之權利保護範 圍所列。 ㈣應如纽之巾請專利範 【圖式簡單説明】 第1Α及1Β圖係為習知车道 — 巧白知+導體封裝件之剖面示意圖； 弟2Α至2C圖係為本發明之封裝基板之剖 以及 弟3圖係為本發明之扭壯 ^. ^ 士衣基板之堆®應用之剖面示 意圖。 【主要元件符號說明】 10 ' 160 基板 1 Oa、1 Ob 表面 Π 第一半導體晶片 12、16 3、2 7、2 7 ’ 焊料球 110858 12 201003871 13 第二半導體 14、25 導線 15 ' 162 ' 26 封裝材 16 封裝件 161 、 23 半導體晶片 17 導電元件 20 核心板 200 開口 201 打線墊 2.01a 表面處理層 202 植球墊 204 介電層 20a 第一表面 20b 第二表面 21 金屬板 22 防焊層 220 防焊層開口 221 開孔 231 電極塾 23a 作用面 23b 非作用面 24 黏著層 h、s 厚度I ^ coating the semiconductor wafer 23, the wires 25 and the wire 塾 2Gi; the solder resist layer 22 on the second surface 2Qb side of the keling plate 2G, and the metal plate 21 in the opening 221 of the solder resist layer μ And the solder ball 272〇2 is connected to the solder ball u27′ to form a package, wherein the spheroidal ball 27 attached to the metal plate 21 is used for heat dissipation and is attached to the ball-fed art 2〇2 The solder Τ 27 is used for external electronic devices, such as printed circuit boards, and the package 外 can also be externally packaged to form a stacked package structure. The package substrate of the present invention has an opening and reduces the overall package height by accommodating the semiconductor wafer in the opening; in addition, the thickness of the metal plate 110858 11 201003871 is greater than the thickness of the ball pad, so that the semiconductor The wafer is stabilized on the slab, and the metal material has good thermal conductivity, and the stencil and the wafer are dissipated by the metal plate to achieve the function of dissipating heat. In summary, the present invention places the semiconductor wafer into the opening of the core board, so that the height of the structure is only the height of the core board, and the height of the body wafer is required to effectively reduce the height; In addition, a copper and a thick metal plate is used as a component for carrying a semiconductor wafer, and has a heat dissipation function. The above embodiments are intended to illustrate the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the protection of the present invention is listed. (4) The patent should be applied to the towel of the New Zealand [simplified description of the drawings] The first and first drawings are the schematic diagrams of the custom lanes - Qiao Baizhi + conductor packages; the brothers 2Α to 2C are the package substrates of the present invention. The section and the diagram of the brother 3 are the torsion of the invention. ^ ^ Schematic diagram of the application of the Shiyi substrate stack®. [Description of main component symbols] 10 '160 Substrate 1 Oa, 1 Ob Surface Π First semiconductor wafer 12, 16 3, 2 7 , 2 7 ' Solder ball 110858 12 201003871 13 Second semiconductor 14, 25 wire 15 ' 162 ' 26 Package 16 Package 161 , 23 Semiconductor wafer 17 Conductive element 20 Core plate 200 Opening 201 Wire pad 2.01a Surface treatment layer 202 Ball pad 204 Dielectric layer 20a First surface 20b Second surface 21 Metal plate 22 Solder mask 220 Solder mask opening 221 Opening 231 Electrode 塾 23a Acting surface 23b Non-active surface 24 Adhesive layer h, s Thickness

Claims (1)

201003871 十、申請專利範圍： 1. 一種封裝基板，係包括： 核心板，係具有相對之第一表面及第二表面，於 該第一表面上具有複數打線墊並與該第一表面齊 平，於該第二表面具有複數植球墊並與該第二表面齊 . 平，且具有貫穿該第一及第二表面之開口；以及 金屬板，係設於該核心板之第二表面，並對應該 開口，且與該第二表面齊平，該金屬板之厚度係大於 f 該植球墊之厚度，以供承載之用。 2. 如申請專利範圍第1項之封裝基板，其中，該核心板 係為兩層或多層線路板。 3. 如申請專利範圍第1項之封裝基板，其中，該金屬板 係為銅。 4. 如申請專利範圍第1項之封裝基板，其中，該金屬板 係顯露在該開口中。 5. 如申請專利範圍第1項之封裝基板，復包括防焊層， f 4 t 係分別設於該核心板之第一表面及第二表面上，該第 一表面之防焊層具有對應該開口之防焊層開口，且該 些防焊層具有複數開孔，以對應露出各該打線墊、金 屬板及植球墊。 6. 如申請專利範圍第5項之封裝基板，復包括表面處理 層，係設於該防焊層開口中之打線墊上。 7. 如申請專利範圍第6項之封裝基板，其中，該表面處 理層係為化錄/金（N i / A u)、電鐘錄/金（N i / A u)、化錄 14 110858 201003871 8. 把浸金（響1G)或化鎳自催化金⑽AG)。 一種封裝基板，係包括： :::及：具有相對之第—表面及第二表面，於 二衣弟二表面分別具有介電層，且該第 ==具有複數打線墊，於該第二表面之4 層上具，複數植球墊， 丨电 面及第二表面之開口；具有貫穿該介電層、第—表 金屬板二係設於該核心板之第二表面之介電層 严：對應綠開口，該金屬板之厚度係大於該植球墊 之厚度’以供承載之用。 9. t申請專利範圍第8項之封裝基板，其中，該核 知為兩層或多層線路板。 1〇.如申請專利範圍第8項 係為銅。 、之封錄板，其巾，該金屬板 V 專利範圍第8項之封裳基板，其中，該開口中 孟屬板係為該介電層所覆蓋。 Ή請專利範圍第8項之^基板，復包括防❹， 刀別設於該核心板之第一表面及第二表面的介電 曰上，該第一表面之防焊層具有對應該開口之防俨= =熱且：Γ焊層具有複數開孔’以對應露出：： 打線墊、金屬板及植球墊。 13. π請t:範圍第12項之封裝基板，復包括表面處 ® 如6又於該防焊層開口中之打線墊上。 14. 如申請專利範圍第13項之封裝基板，其中，該表面 110858 15 201003871 處理層係為化錄/金（N i /Au)、電鍍鏡/金（N i /Au)、化 鎳鈀浸金（ENEPIG)或化鎳自催化金（ENAG)。 .15. —種封裝基板，係包括： 核心板，係具有相對之第一表面及第二表面，於 . 該第一表面及第二表面分別具有介電層，且該第一表 . 面之介電層中具有複數打線墊，該打線墊並與該介電 層表面齊平，於該第二表面之介電層上具有複數植球 墊，該植球墊並與該介電層表面齊平，且具有貫穿該 f 介電層、第一表面及第二表面之開口； 金屬板’係設於該核心板之第二表面的介電層中 並與該介電層表面齊平，且對應該開口，該金屬板之 厚度係大於該植球墊之厚度，以供承載之用。 16.如申請專利範圍第15項之封裝基板，其中，該核心 板係為兩層或多層線路板。 1 7.如申請專利範圍第1 5項之封裝基板，其中，該金屬 板係為銅。 C ~ 1 8.如申請專利範圍第1 5項之封裝基板，其中，該開口 中之金屬板係為該介電層所覆蓋。 19. 如申請專利範圍第15項之封裝基板，復包括防焊層， 係設於該核心板之第一表面及第二表面的介電層 上，該防焊層具有對應該開口之防焊層開口，且該些 防焊層具有複數開孔，以對應露出各該打線塾、金屬 板及植球塾。 20. 如申請專利範圍第1 9項之封裝基板，復包括表面處 16 110858 201003871 理層，係設於該防焊層開口中之打線墊上。 21.如申請專利範圍第20項之封裝基板，其中，該表面 處理層係為化錄/金（N i / Au)、電艘錄/金（N i / Au)、化 鎳鈀浸金（ENEPIG)或化鎳自催化金（ENAG)。201003871 X. Patent application scope: 1. A package substrate, comprising: a core plate having a first surface and a second surface opposite to each other, and having a plurality of wire mats on the first surface and flush with the first surface; Having a plurality of ball pads on the second surface and being flush with the second surface, and having openings through the first and second surfaces; and a metal plate attached to the second surface of the core plate It should be open and flush with the second surface, the thickness of the metal sheet being greater than the thickness of the ball pad for carrying. 2. The package substrate of claim 1, wherein the core board is a two-layer or multi-layer circuit board. 3. The package substrate of claim 1, wherein the metal plate is copper. 4. The package substrate of claim 1, wherein the metal plate is exposed in the opening. 5. The package substrate of claim 1 is further comprising a solder resist layer, wherein f 4 t are respectively disposed on the first surface and the second surface of the core plate, and the solder resist layer of the first surface has a corresponding The open solder resist layer is opened, and the solder resist layers have a plurality of openings to correspondingly expose each of the wire mats, the metal plate and the ball pad. 6. The package substrate of claim 5, further comprising a surface treatment layer disposed on the wire bonding pad in the opening of the solder resist layer. 7. The package substrate of claim 6, wherein the surface treatment layer is a chemical recording/gold (N i / A u), an electric clock recording/gold (N i / A u), and a chemical recording 14 110858 201003871 8. Put gold (1G) or autocatalytic gold (10) AG). A package substrate comprising: ::: and: having a first surface and a second surface, respectively having a dielectric layer on a surface of the second body, and the first == having a plurality of wire pads on the second surface The fourth layer has a plurality of ball pads, a surface of the electric surface and a second surface; and a dielectric layer extending through the dielectric layer and the second metal plate on the second surface of the core plate: Corresponding to the green opening, the thickness of the metal plate is greater than the thickness of the ball pad for carrying. 9. The package substrate of claim 8 of the patent application, wherein the identification is a two-layer or multi-layer circuit board. 1〇. If the scope of patent application is 8th, it is copper. , the seal plate, the towel, the metal plate V patent scope item 8 of the cover substrate, wherein the opening of the Meng board is covered by the dielectric layer. The substrate of the eighth item of the patent scope further includes a tamper-proof, and the knives are disposed on the first surface of the core board and the dielectric layer of the second surface, and the solder resist layer of the first surface has a corresponding opening Anti-mite = = hot and: the solder layer has a plurality of openings 'to correspondingly exposed:: wire pad, metal plate and ball pad. 13. πPlease t: The package substrate of the 12th item of the range, including the surface of the package, such as 6 and the wire pad in the opening of the solder mask. 14. The package substrate of claim 13, wherein the surface 110858 15 201003871 treatment layer is a chemical/gold (N i /Au), a plated mirror/gold (N i /Au), a nickel-palladium dip Gold (ENEPIG) or nickel self-catalyzing gold (ENAG). The package substrate comprises: a core plate having opposite first and second surfaces, wherein the first surface and the second surface respectively have a dielectric layer, and the first surface is The dielectric layer has a plurality of wire bonding pads, and the wire bonding pad is flush with the surface of the dielectric layer, and has a plurality of ball bonding pads on the dielectric layer of the second surface, and the ball bonding pads are flush with the surface of the dielectric layer Flat, and having openings through the dielectric layer, the first surface, and the second surface; the metal plate is disposed in the dielectric layer of the second surface of the core plate and is flush with the surface of the dielectric layer, and Corresponding to the opening, the thickness of the metal plate is greater than the thickness of the ball pad for carrying. 16. The package substrate of claim 15, wherein the core board is a two-layer or multi-layer circuit board. The package substrate of claim 15 wherein the metal plate is copper. C. The package substrate of claim 15 wherein the metal plate in the opening is covered by the dielectric layer. 19. The package substrate of claim 15 , further comprising a solder resist layer disposed on the dielectric layer of the first surface and the second surface of the core board, the solder resist layer having an anti-welding corresponding to the opening The layers are open, and the solder resist layers have a plurality of openings to correspondingly expose the respective wire bonds, metal plates and ball bumps. 20. The package substrate of claim 19, which includes a surface layer, is disposed on a wire pad in the opening of the solder resist layer. 21. The package substrate of claim 20, wherein the surface treatment layer is a chemical/gold (N i / Au), an electric boat/gold (N i / Au), a nickel-palladium immersion gold ( ENEPIG) or nickel self-catalyzing gold (ENAG). 17 11085817 110858
TW97126240A 2008-07-04 2008-07-11 Package substrate TW201003871A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW97126240A TW201003871A (en) 2008-07-11 2008-07-11 Package substrate
US12/495,191 US8188379B2 (en) 2008-07-04 2009-06-30 Package substrate structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW97126240A TW201003871A (en) 2008-07-11 2008-07-11 Package substrate

Publications (1)

Publication Number Publication Date
TW201003871A true TW201003871A (en) 2010-01-16

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