201002168 六、發明說明： 【發明所屬之技術領域】 本發明係關於印刷電路基板的製造方法。 【先前技術】 伴隨電子產業的發達，對於電子零件的高機能性、小 型化、價格競爭力、以及短交貨期的要求變高。為回應如 ，此的動向，封裝基板製造公司，應用半加成法（“如 additive process ; SAp)來對應基板的薄型化及高密度化。 但是’若根據半加成法，雖可實現高密度電路圖樣， 但在形成電路圖樣及通孔（via h〇le)形成時，製程數增加， 發生製造製程的追加費用。另外，為了對基板表面及加工 孔内部進行除膠渣（desmear)處理，來進行化學鍍銅，需 要花費較多的費用與時間。 先前技術中’是先在兩面貼銅積層板形成加工孔，接 '著除膠渣處理加工孔内壁及基板表面，然後進行化學鍍 鋼。然後，在化學鍍銅層上進行電解電鍍，形成電路圖樣 及通孔。亦即’先前，是在形成加工孔後，為了連接層間 而將加工孔内部電鍍。由於如此的加工孔内壁的電鍍過 程’基板表©的電鑛層會變厚，難以形成微細電路。 【發明内容】 [發明所欲解決的問題] 201002168 • 為了解決如此的先前技術的問題點，本發明的目的係 提供一種印刷電路基板的製造方法’可製造出薄型化及高 密度化的基板，且可降低製造製程所花費的時間、費用。 - [解決問題之技術手段] • 若根據本發明之一實施形態，則可提供一種印刷電路 基板的製造方法，其係包含：形成第—電路圖樣的階段； 在第一電路圖樣上形成凸塊的階段；在第一電路圖樣上積 層絕緣材，使第一電路圖樣被埋入絕緣材中，並藉由上述 (凸塊來貫通絕緣材的階段；在絕緣材上形成第二電路圖樣 的階段；以及加壓第二電路圖樣，使第二電路圖樣被埋入 絕緣材的階段。 此處，在第一電路圖樣上形成凸塊的階段，可藉由將 銀墨水印刷在第一電路圖樣上來進行。 形成第一電路圖樣的階段，可包含：提供在其一面已 積層有金屬層之載體的階段；在金屬層上形成電鐘光阻的 I 階段；以及在金屬層上形成導電性物質的階段。 此處，被積層於載體上的金屬層，可由被形成於载體 .上的第-金屬層；以及被形成於第一金屬層上的第二金屬 層所構成。 第一金屬層可包含鋼（㈤，第二金屬層可包含鎳 (Ni)。 在絕緣材上形成第二電路圖樣的階段，可包含：在絕 緣材及凸塊上形成導電層的階段；除去载體的階段；在導 電層上形成钮対光阻的階段；以及㈣導電層及第—金屬 4 201002168 • 層的階段。 在絕緣材及凸塊上形成導電層的階段，可利用壓緊製 程，藉由將導電層加磨於絕緣材上，使導電層與凸塊電性 連接來進行。 另外在开》成第二電路圖樣的階段後，可更包含除去 第二金屬層的階段。 除去第二金屬層的階段，可藉由供給蝕刻溶液，蝕刻 第二金屬層來進行。 另一方面，在絕緣材上形成第二電路圖樣的階段，可 =含.在絕緣材及凸塊上形成種子層的階段；除去載體的 階段，在種子層及金屬層上形成電鍍光阻的階段；在種子 層上形成導電性物質的階段；除去電鑛光阻的階段；以及 钮刻種子層及金屬層的階段。 此處，在絕緣材及凸塊上形成種子層的階段，可利用 壓緊製程，藉由將種子層加壓於絕緣材上，使種子層與凸 塊電性連接來進行。 、 而且，形成第一電路圖樣的階段，可包含：提供在其 -面已積層有金屬層之載體的階段；在金屬層上積層感： 生物質的階段，，藉由使感光性物質選擇性地曝光、顯像， 來形成蚀刻光阻的階段；以及姓刻金屬層的階段。 在絕緣材上形成第二電路圖樣的階段，彳包含：在絕 緣材及凸塊上形成導電層的階段；除去載體的階段；在導 、層及第1：路圖樣上形成钱刻光阻的階段；以及餘刻導 電層的階段。 201002168 而且，在絕緣材及凸塊上形成導電層的階段，可利用 壓緊製程’藉由將導電層加麗於絕緣材上，使導電層與凸 塊電性連接來進行。 〃 [功效] 若根據本發明的實施例，可得到微細電路圖樣及高密 度電路圖樣，且可降低製造製程所花費的費用及時間，並 可提高圖樣間的絕緣可靠性。 【實施方式】 本發明可作多樣的變換，可有各式各樣的實施例，因 此在本案中，於圖式例示並詳細地說明特定實施例。但是， 這並不是將本發明限定於特定的實施例，而是應被理解為 包括：被包含在本發明的思想以及技術範圍中的所有的變 換、均等物、以及代替物者。說明本發日㈣，被判斷為對 於相關的習知技術的具體說明，&而會造成本發明的要旨 不明確的情況時，則省略其詳細的說明。 、 第一」、「第二」等的用語，僅為用以說明多樣的構 成要素，上述構成要素並非藉由上述用語而被限定。上述 用語係僅被用於區別-構成要素與其他的構成要素的目 的0 必須理解地，本案争所用的用語係僅為說明特定的實 施例而採用者，並非限定本發明者。單一數的表現，只要 在文句之中未明確表現的前提下，包含複數的表現。本案 6 201002168 匕3」或具有」等的用語’係用來指定被記載於說 曰上的特徵、數字、階段、動作、構成要素、構件、或 組合這些者的存在’而並非預先排除一個或一個以上的其 他的特徵、數字、階段、動作、 _. ^ 乍構成要素、構件、或組合 這些者的存在或是附加可能性。 以下，基於添附圖式，沒& 孑、、、田地說明本發明之印刷電路 二板？、製造方法的實施例’使用添附圖式來進行說明 :=同且對應的構成要素’係標記相同的符號而省 略對此的重複說明。 第1圖係表示依據本發明的篦 ^ .. y, 第一實施例之印刷電路基 板的製xe方法的流程圖，第2 明的第—實⑽之㈣電職板^ ^係表不依據本發 銮昭 土板的製以方法的製程圖。若 樣：圖〜第11 I則第-電路圖㈣、第二電路圖 =凸：3。、絕緣材40、载體5。、金屬層52、第一金 屬層54、弟二金屬層56、電 _ „ 鲅九阻（Plating resist)6〇、導 電層62、以及蝕刻光阻64係被表示。 本發明的弟一實施例，在階與ς η Λ Λ SU〇中，如第2圖〜第 圖所不’於載體50上形成第-電路圖樣10。 首先，在階段S111中，如第 -面P接鹿士人. 弟2圓所不’提供-種在其 已積層有金屬層52之載體ςη 電路圖媒μ 之載體50。载體係作為可使第- ΐ路圖樣10形成的支持體。载 Γ^ , 執髖，係支持第一電路圖樣， 乂使在形成第一電路圖樣後， 了進仃絕緣材40的積層製 往而且，在本實施例中，第—人s „ 56 MM ^ 至屬層54及第二金屬層 破積層於载體上。第一令厘 戰體上帛金屬層54係被形成於載體上， 201002168 第 金屬層56係可藉由 上 電解電鍛而被形成於第^一金屬層 、 '金屬層54及第二金屬層56,係可由相異的材質形 成第金屬層54，可於後述的第二電路圖樣20的形成 ，程:’、在餘刻導電層62時，藉由银刻溶液而被除去。亦 P形成第金屬層54的材質，係能以可用與第二電路圖 樣20相同的蝕刻溶液來進行蝕刻的材質。在本實施例中， 第一金屬層係可與第二電路圖樣同樣地包含鋼（Cu)。 而且’本實施例中的第二金屬層56，係於第一電路圖 ，W的形成時，擔任種子屬（SeedLayer)的角色。另外， =成第二電路圖樣2()的製程中，作為用以遮斷第一電路 圖樣10被餘刻溶液餘刻的角色。因此，第 以與第二電路圖婵Μ α β 母曰：>0係 樣20及第一金屬層54相異的材質來形 :’广、不會被餘刻第一金屬層54的餘刻溶液 ^叫的㈣溶液所㈣。本實施例中 ; 可包含鎳（Ni)。 層6 在階段 S112 Φ，μ , ;載體0上，亦即，於載體的第二 、， ，積層感光性物質。然後，在階段S113申，使 ::罩等’選擇性地曝光、顯像感光性物質，來除去其一 二二亦即’如第3圖所示，以微影方式，於第二金屬層 層上!^光阻60。電鑛光阻係對應要被形成於第二金屬 第-電路圖揭1路圖樣1〇的形狀而被形成。亦即，對應 :::樣的部分之第二金屬層，沒有被電鍍 盍而露出外部。 復 201002168 在階段S114中’於第二金屬層56上形成導電性物質。 如第3圖所示’在已形成有選擇性地覆蓋第二金屬層兄之 電鍍光阻60的狀態下，進行電解電鍍。利用電解電鍍製 程導電性物質可被形成於未被電鍍光阻覆蓋的第二金屬 層56上。 藉由電解電鍍，導電性物質被形成於第二金屬層56上 之後’剝離電鍍光阻60。如第4圖所示，藉由除去電鐘光 阻，第—電路圖樣10可被形成於第二金屬層56上。本實 施例中的導電性物質，可使用銅（Cu)。 在階段S120中，如第5圖所示，於第一電路圖樣⑺ 上形成凸塊30。凸塊係使第—電路圖樣與後述的第二電路 圖樣20的兩層間導通M乍為電性導通的角色的凸塊，可由 導電性物質所形成。在本實施例中，力第一電路圖樣上形 成凸塊30的製程’係可藉由在第—電路圖樣^上印刷銀 …價’· Ag)墨水而被進行。於被設計成可層間導通的 第一電路圖樣的—部分，亦即於要被形成凸塊30之電極墊 上’印刷銀墨水。如第5圖所示，藉由銀墨水被硬化，導 電性凸塊3〇可被形成於第-電路圖樣上。在本實施例中， 雖然舉出銀墨水為例，但可使料油墨㈣如 的導電性材質》 ； ^ 在階段S130中，如第6圖邮_ 圖所不，於第一電路圖樣1C 上積層絕緣材40。藉由絕緣材 4刊被:積層，第一電路圖樣 被埋入絕緣材中。第一電路薗 M 4n Μ 一 I路圖樣1G的各圖樣間，可被絕緣 材40填滿。本實施例的絕 何’係可於半硬化狀態下 201002168 積層。因此，第一電路圖樣可被埋入絕緣材中。而且，雖 然絕緣材被積層，可是絕緣材會被導電性凸塊貫通。如 第6圖所示’絕緣材40被凸塊30貫通，凸塊30的上端露 在絕緣材的外部。 在階段S140中，如第7圖〜第9圖所示，於絕緣材4〇 上形成第二電路圖樣20。在階段S 141中，如第7圖所示， 於絕緣材及凸塊30上，積層導電層62。導電層62係被形 成可覆蓋絕緣材及露出絕緣材的外部的凸塊。此導電層係 成為第二電路圖樣20的金屬層。本實施例中，導電層62 可為銅材質的鋼箔層。導電層’可根據以高溫高壓將銅箔 層屋緊在絕緣層40上的製程而被形成。導電層，在被加壓 於絕緣層上的過程中，導電層與導電性凸塊可電性連接。 本實施例中的壓緊製程，可由5〜3〇kgf/cm2的壓力及 150C以上的溫度來進行。與第一金屬層接合的載體，利用 高溫高壓的壓緊製程’可從第-金屬層54分離。亦即，在 階段S 142中’於導電層62的積層製程後，載體5〇會被除 去。 在階段S143中’如第8圖所示，於導電層以上形成 姓刻光阻（etChingresist)64。㈣光阻，可藉由對於感光性 絕緣材進行微影製程而形成。蝕刻光阻64係選擇性地覆蓋 導電層62。 在階段S144_ ’如第9圖所示，勉刻未被餘刻光阻64 覆蓋的導電層62及第一金屬層54。本實施例中，導電層 62及第-金屬| 54係以鋼（Cu)形成。藉由供給能蝕亥: 201002168 銅（Cu )金屬層的姓刻溶液， J蝕刻導電層62及第一金屬 層54。在蚀刻製程中，可選遲卜 费觉, 擇性地蝕刻未被蝕刻光阻64 覆羞的¥電層62,並可除去第—金屬層 在此，能餘刻銅（Cu)金屬層的㈣溶液，無法㈣ 由娜）形成的第二金屬^ 56。即使第-金屬層54被 除去，弟二金屬層56亦不會被㈣溶液㈣。因此，第一 電路圖樣10，利用第二金屬> 萄增56而不會被蝕刻。 —如第9圖所示，姓刻製程後，藉由剝離银刻光阻64, 第二電路圖樣20可被形成於絕緣材4〇上。 接著在P白& S150中，如第1〇圖所示，加壓第二電 路圖樣20’使第二電路圖樣被埋入絕緣材4〇。如第9圖所 示，第二電路圖樣係從絕緣材露出。若以第二電路圖樣露 出的狀態來進行壓平製程，使第二電路圖樣被埋入絕緣 材，則可k而圖樣間的絕緣可靠性。 接著’在階段S160中’如第11圖所示，除去覆蓋第 i 一電路圖樣10的第二金屬層56。由與第一金屬;！ 54相異 的材質所形成的第二金屬層56，於第二電路圖樣2〇的形 成過程中未被蝕刻，保護第一電路圖樣。 若根據本實施例，鎳（Ni)材質的第二金屬層56，可 利用不會蝕刻銅（Cu)材質的第一電路圖樣1〇及第二電路 圖樣20的蝕刻溶液而被除去。如第u圖所示，可使用僅 選擇1±地蝕刻第二金屬層56的蝕刻溶液，來除去第二金屬 層0 若根據本發明的第一實施例，第一電路圖樣1〇，可利 11 201002168 用半加成法來實現10/10〜15/15/zm (線寬/線間距； Line/ Space )的高密度形狀’第二電路圖樣2〇可藉由消 減（Subtractive )法來實現 20/ 20〜25/ 25 // m (線寬 / 線間距；Line/ Space )。對於必須作成微細電路圖樣的電 子元件的構裝面’可使用第一電路圖樣10的微細圖樣，對 於用以與外部連接的凸塊或銲錫球的接合面，可使用第二 電路圖樣20。 若根據本發明的第一實施例，對應印刷電路基板要被 適用的部分’可用半加成法或消減法分別形成電路圖樣。 因此’可實現微細電路圖樣及高密度電路圖樣，並且，可 減少在半加成法中所要求的昂貴的除膠渣及化學鍍鋼工 時。另外，可減少在電解電鍍製程中所要求的製程時間。 另外，如第11圖所示，藉由第一電路圖樣及第二 電路圖樣20被埋入絕緣材4〇，可提供被薄型化、已提高 絕緣可靠性的印刷電路基板。 以下，基於第12圖〜第22圖，說明依據本發明的負 二實施例之印刷電路基板的製造方法。 第12圓係表示依據本發明的第二實施例之印刷電路邁 板的製造方法的流程圖’第13圖〜第22圖係表示依據4 發明的第二實施例之印刷電路基板的製造方法的製程圖。 若參照第13圖〜第22圖，則第一電路圖樣10、第二電與 圖樣20、凸塊30、絕緣材4〇、載體5〇、金屬層W、電袭 光阻60、種子層7〇、以及電鍍光阻72係被表示。 12 201002168 本發明的第二實施例，在階段S21〇中，如第i3圖〜 第15圖所示，於載體5〇上形成第一電路圖樣1〇。 首先’在階段S2U中，如第13圖所示，提供一種在 其-面已積層有金屬層52之載冑5〇。载體，根據第一實 施例的說明’係作為可使第—電路圖樣1〇形成的支持體， 用以支持第一電路圖樣，以使在形成第一電路圖樣後，可 進行絕緣材40的積層製程。 接著，在階段S212中，於载體5〇上，亦即，於載體 的金屬層52上，積層感光性物質。然後，在階段S213中， 使用光罩等，選擇性地曝光、顯像感光性物質，來除去其 -部分。亦即’如第14圖所示，以微影方式，於載體的金 屬層52上形成電鍍光阻6〇。電鍍光阻，係對應欲形成於 金屬層52上的第一電路圖樣1〇的形狀而被形成。亦即， 對應第一電路圖樣的部分之金屬層52，沒有被電鍍光阻6〇 覆蓋而露出外部。 在階段S214中，於金屬層52上形成導電性物質。如 第14圖所示，在已形成有選擇性地覆蓋金屬層52之電鍍 光阻60的狀態下，進行電解電鍍。利用電解電鍍製程，導 電性物質可被形成於未被電鍍光阻覆蓋的金屬層上。 藉由電解電鍍，導電性物質被形成於金屬層52上之 後，剝離電鍍光阻60。如第15圖所示，藉由除去電鍍光 阻，第一電路圖樣1〇可被形成於金屬層上。本實施例的導 電性物質中，係可由銅（Cu )形成。 在階段S220中，如第16圖所示，於第一電路圖樣1〇 13 201002168 上形成凸塊30。然後，在階 於牮_ 牡1白奴S23〇中，如第17圖所示， 於弟一電路圖樣10上積； 埋入絕^ 使第—電路圖樣被 邾 凸塊3 〇貝通絕緣材而露出於外 » 。在本實施例中第一 S220及在Μ 一 路圖樣上形成凸塊30的階段 路圖樣上積層絕緣材的階段S230，可藉由 ::發明的第-實施例相同製程來進行。導電性凸塊30及 、、緣材的材質’亦可使用與第一實施例相同者。 f 接著，在階段U40中’如第18圖〜第21圖所示，於201002168 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of manufacturing a printed circuit board. [Prior Art] With the development of the electronics industry, the requirements for high functionality, miniaturization, price competitiveness, and short lead time of electronic components have increased. In response to this trend, the package substrate manufacturing company applies semi-additive methods (such as additive process; SAp) to reduce the thickness and density of the substrate. However, if it is semi-additive, it can be realized. Density circuit pattern, but when the circuit pattern and the via hole are formed, the number of processes increases, and the manufacturing process costs additional. In addition, in order to perform desmear processing on the substrate surface and the inside of the processing hole. In order to carry out electroless copper plating, it takes a lot of cost and time. In the prior art, the processing holes were formed on the two-sided copper laminated board, and the inner wall of the processing hole and the surface of the substrate were processed by the desmear processing, and then electroless plating was performed. Then, electroplating is performed on the electroless copper plating layer to form a circuit pattern and a through hole. That is, 'previously, after forming the processing hole, the inside of the processing hole is plated in order to connect the layers. Because of this, the inner wall of the hole is machined. In the electroplating process, the electric ore layer of the substrate table © becomes thick, and it is difficult to form a fine circuit. [Summary of the Invention] [Problems to be Solved by the Invention] 201002168 • To understand In view of the problems of the prior art, an object of the present invention is to provide a method for manufacturing a printed circuit board that can reduce the thickness and cost of the manufacturing process, and can reduce the time and cost of the manufacturing process. Technical Solution] According to an embodiment of the present invention, a method of manufacturing a printed circuit board comprising: a stage of forming a first circuit pattern; a stage of forming a bump on the first circuit pattern; Laminating an insulating material on the first circuit pattern, so that the first circuit pattern is buried in the insulating material, and by the above (the stage of the bump passing through the insulating material; the stage of forming the second circuit pattern on the insulating material; and pressurizing The second circuit pattern is such that the second circuit pattern is buried in the insulating material. Here, the stage of forming the bump on the first circuit pattern can be performed by printing the silver ink on the first circuit pattern. a phase of a circuit pattern, comprising: providing a stage of a carrier having a metal layer laminated on one side thereof; and forming an I stage of an electric clock photoresist on the metal layer; And a stage of forming a conductive substance on the metal layer. Here, the metal layer laminated on the carrier may be a first metal layer formed on the carrier; and a second layer formed on the first metal layer The first metal layer may comprise steel ((5), and the second metal layer may comprise nickel (Ni). The stage of forming the second circuit pattern on the insulating material may include: forming conductive on the insulating material and the bump The stage of the layer; the stage of removing the carrier; the stage of forming the button photoresist on the conductive layer; and (4) the stage of the conductive layer and the first metal 4 201002168 • layer. The stage of forming the conductive layer on the insulating material and the bump, The pressing process can be performed by grinding the conductive layer on the insulating material to electrically connect the conductive layer and the bump. Further, after the step of forming the second circuit pattern, the second metal can be further removed. The stage of the layer. The stage of removing the second metal layer can be performed by supplying an etching solution to etch the second metal layer. On the other hand, the stage of forming the second circuit pattern on the insulating material can include: a stage of forming a seed layer on the insulating material and the bump; and a stage of removing the carrier, forming a plating resist on the seed layer and the metal layer. Stage; a stage of forming a conductive substance on the seed layer; a stage of removing the electro-mineral photoresist; and a stage of engraving the seed layer and the metal layer. Here, the step of forming the seed layer on the insulating material and the bump can be carried out by pressing the seed layer against the insulating material and electrically connecting the seed layer and the bump by a pressing process. And, the stage of forming the first circuit pattern may include: providing a stage in which the carrier has a metal layer laminated thereon; forming a layer on the metal layer: a stage of biomass, by making the photosensitive material selective Exposure, development, to form the stage of etching photoresist; and the stage of surnamed metal layer. a stage of forming a second circuit pattern on the insulating material, comprising: a stage of forming a conductive layer on the insulating material and the bump; a stage of removing the carrier; and forming a photoresist on the conductive layer, the layer, and the first: road pattern Stage; and the stage of the remaining conductive layer. 201002168 Moreover, in the stage of forming a conductive layer on the insulating material and the bump, the pressing process can be performed by electrically attaching the conductive layer to the insulating material and electrically connecting the conductive layer to the bump.功效 [Effect] According to the embodiment of the present invention, a fine circuit pattern and a high-density circuit pattern can be obtained, and the cost and time required for the manufacturing process can be reduced, and the insulation reliability between the patterns can be improved. [Embodiment] The present invention can be variously modified, and various embodiments can be made. Therefore, in the present invention, specific embodiments are illustrated and described in detail in the drawings. However, the present invention is not limited to the specific embodiments, but is intended to include all modifications, equivalents, and substitutes that are included in the scope of the inventions. In the case of the present invention (4), it is judged that the detailed description of the related art, and if the gist of the present invention is unclear, the detailed description thereof will be omitted. The terms "first" and "second" are used merely to describe various constituent elements, and the above constituent elements are not limited by the above terms. The above-mentioned terms are used only for the purpose of distinguishing between the constituent elements and the other constituent elements. It is to be understood that the terminology used in the present invention is intended to be used only for the purpose of describing specific embodiments, and is not intended to limit the invention. The performance of a single number includes the performance of plurals as long as it is not clearly expressed in the sentence. The case 6 201002168 匕 3" or the phrase "and" is used to designate the existence of features, numbers, stages, actions, components, components, or combinations of those described in the statement, and does not preclude one or More than one other feature, number, stage, action, _. ^ 乍 component, component, or combination of these existence or additional possibilities. Hereinafter, based on the accompanying drawings, the printed circuit board of the present invention will be described without the & The embodiment of the manufacturing method will be described with reference to the drawings. The same components are denoted by the same reference numerals, and the repeated description thereof will be omitted. 1 is a flow chart showing the method of manufacturing the printed circuit board according to the first embodiment of the present invention, and the second (10) (4) electric board is not based on The process chart of the method of making the 銮 銮 土 板 。. If so: Figure ~ 11 I, the first circuit diagram (four), the second circuit diagram = convex: 3. , insulating material 40, carrier 5. The metal layer 52, the first metal layer 54, the second metal layer 56, the electric plating layer 6 , the conductive layer 62, and the etching photoresist 64 are shown. In the order and η Λ Λ 〇 SU〇, as shown in Fig. 2 to Fig. 2, the first circuit pattern 10 is formed on the carrier 50. First, in the stage S111, the first face P is connected to the deer. The 2nd circle does not provide a carrier 50 for the carrier ς 电路 图 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体 载体The first circuit pattern is supported, so that after the first circuit pattern is formed, the laminated insulating material 40 is laminated and, in this embodiment, the first person s „ 56 MM ^ to the genus layer 54 and the second The metal layer is deposited on the carrier. The first metal layer 54 is formed on the carrier, and the 201002168 metal layer 56 can be formed on the first metal layer, the metal layer 54 and the second metal layer by electrolytic forging. 56, the first metal layer 54 may be formed of a different material, and the second circuit pattern 20, which will be described later, may be formed by removing the conductive layer 62 by a silver etching solution. Further, P is formed of a material of the metal layer 54, and is made of a material which can be etched by the same etching solution as that of the second circuit pattern 20. In the present embodiment, the first metal layer may contain steel (Cu) in the same manner as the second circuit pattern. Further, the second metal layer 56 in the present embodiment is in the form of a seed layer (SeedLayer) when the first circuit diagram is formed. Further, in the process of = second circuit pattern 2 (), as a function for interrupting the first circuit pattern 10 by the remaining solution. Therefore, the first shape is different from the material of the second circuit diagram β α β 曰: > 0 swatch 20 and the first metal layer 54: 'wide, no residue of the first metal layer 54 Solution ^ (4) solution (four). In this embodiment; nickel (Ni) may be included. Layer 6 is laminated on the substrate S112 Φ, μ, ; carrier 0, i.e., the second, , and photosensitive material of the carrier. Then, in step S113, a :: cover or the like 'selectively exposes, develops a photosensitive substance, and removes one or two, that is, as shown in FIG. 3, in a lithographic manner, on the second metal layer. On the layer! ^ Light resistance 60. The electro-mineral resist is formed in accordance with a shape to be formed in the first metal pattern of the second metal. That is, the second metal layer corresponding to the :::-like portion is not plated and exposed to the outside. The compound 201002168 forms a conductive material on the second metal layer 56 in the step S114. As shown in Fig. 3, electrolytic plating is performed in a state in which the plating resist 60 of the second metal layer is selectively covered. The conductive material can be formed on the second metal layer 56 which is not covered by the plating resist by the electrolytic plating process. The electroconductive material is formed on the second metal layer 56 by electrolytic plating, and then the plating resist 60 is peeled off. As shown in Fig. 4, the first circuit pattern 10 can be formed on the second metal layer 56 by removing the electric clock photoresist. Copper (Cu) can be used as the conductive material in the present embodiment. In stage S120, as shown in Fig. 5, bumps 30 are formed on the first circuit pattern (7). The bumps are bumps in which the first circuit pattern and the second circuit pattern 20 of the second circuit pattern 20 described later are electrically connected to each other, and can be formed of a conductive material. In the present embodiment, the process of forming the bumps 30 on the first circuit pattern of the force can be performed by printing silver ink on the first circuit pattern. The silver ink is printed on the portion of the first circuit pattern that is designed to be electrically conductive between the layers, that is, on the electrode pads on which the bumps 30 are to be formed. As shown in Fig. 5, by the silver ink being hardened, the conductive bumps 3 can be formed on the first circuit pattern. In the present embodiment, although the silver ink is exemplified, the conductive material (4) such as the conductive material can be made; ^ In the step S130, as shown in the sixth figure, the first circuit pattern 1C is used. A laminated insulating material 40. By the insulating material 4 is laminated: the first circuit pattern is buried in the insulating material. The first circuit 薗 M 4n Μ an I-way pattern 1G can be filled with the insulating material 40. The "existence" of this embodiment can be laminated in a semi-hardened state at 201002168. Therefore, the first circuit pattern can be buried in the insulating material. Further, although the insulating material is laminated, the insulating material is penetrated by the conductive bumps. As shown in Fig. 6, the insulating material 40 is penetrated by the bumps 30, and the upper end of the bumps 30 is exposed to the outside of the insulating material. In the step S140, as shown in Figs. 7 to 9, a second circuit pattern 20 is formed on the insulating material 4?. In the step S 141, as shown in Fig. 7, a conductive layer 62 is laminated on the insulating material and the bumps 30. The conductive layer 62 is formed as a bump that covers the insulating material and exposes the outside of the insulating material. This conductive layer is the metal layer of the second circuit pattern 20. In this embodiment, the conductive layer 62 may be a steel foil layer of copper. The conductive layer ' can be formed according to a process of ironing the copper foil layer on the insulating layer 40 at a high temperature and a high pressure. The conductive layer is electrically connected to the conductive bumps during being pressed onto the insulating layer. The pressing process in this embodiment can be carried out by a pressure of 5 to 3 〇 kgf/cm 2 and a temperature of 150 C or more. The carrier bonded to the first metal layer can be separated from the first metal layer 54 by a high temperature and high pressure pressing process. That is, after the lamination process of the conductive layer 62 in the stage S 142, the carrier 5 is removed. In the step S143, as shown in Fig. 8, an etChing resistor 64 is formed over the conductive layer. (4) The photoresist can be formed by performing a lithography process on the photosensitive insulating material. The etch photoresist 64 selectively covers the conductive layer 62. In the stage S144_' as shown in Fig. 9, the conductive layer 62 and the first metal layer 54 which are not covered by the residual photoresist 64 are engraved. In the present embodiment, the conductive layer 62 and the -metal|54 are formed of steel (Cu). The conductive layer 62 and the first metal layer 54 are etched by supplying a solution of the copper (Cu) metal layer by the energy source: 201002168. In the etching process, it is optional to etch the electric layer 62 which is not shattered by the etching photoresist 64, and the first metal layer can be removed, and the copper (Cu) metal layer can be left. (d) solution, can not (four) formed by the second metal ^ 56. Even if the first metal layer 54 is removed, the second metal layer 56 is not affected by the (iv) solution (four). Therefore, the first circuit pattern 10 is grown by the second metal > 56 without being etched. - As shown in Fig. 9, after the surname process, the second circuit pattern 20 can be formed on the insulating material 4 by stripping the silver engraved photoresist 64. Next, in P white & S150, as shown in Fig. 1, the second circuit pattern 20' is pressed to cause the second circuit pattern to be buried in the insulating material 4''. As shown in Fig. 9, the second circuit pattern is exposed from the insulating material. If the flattening process is performed in the state in which the second circuit pattern is exposed, and the second circuit pattern is buried in the insulating material, the insulation reliability between the patterns can be made. Next, in step S160, as shown in Fig. 11, the second metal layer 56 covering the i-th circuit pattern 10 is removed. By with the first metal;! The second metal layer 56 formed by the 54 different materials is not etched during the formation of the second circuit pattern 2, protecting the first circuit pattern. According to the present embodiment, the second metal layer 56 made of nickel (Ni) can be removed by etching the first circuit pattern of the copper (Cu) material and the etching solution of the second circuit pattern 20. As shown in FIG. 5, the second metal layer can be removed using an etching solution that etches only the second metal layer 56 by 1±. If the first circuit pattern is in accordance with the first embodiment of the present invention, 11 201002168 Semi-additive method to achieve high-density shape of 10/10~15/15/zm (line width/line spacing; Line/Space) 'The second circuit pattern 2〇 can be realized by Subtractive method 20/ 20 to 25/ 25 // m (line width/line spacing; Line/Space). The second circuit pattern 20 can be used for the bonding surface of the electronic component to which the fine circuit pattern must be formed, using the fine pattern of the first circuit pattern 10, and for the bonding surface of the bump or the solder ball to be connected to the outside. According to the first embodiment of the present invention, the portions to be applied corresponding to the printed circuit board can be respectively formed into circuit patterns by semi-additive or subtractive methods. Therefore, it is possible to realize a fine circuit pattern and a high-density circuit pattern, and it is possible to reduce the expensive desmear and electroless steel plating labor required in the semi-additive method. In addition, the process time required in the electrolytic plating process can be reduced. Further, as shown in Fig. 11, by embedding the insulating material 4 in the first circuit pattern and the second circuit pattern 20, it is possible to provide a printed circuit board which is thinned and has improved insulation reliability. Hereinafter, a method of manufacturing a printed circuit board according to a negative second embodiment of the present invention will be described based on Figs. 12 to 22 . 12th circle diagram showing a manufacturing method of a printed circuit board according to a second embodiment of the present invention. FIG. 13 to FIG. 22 are views showing a method of manufacturing a printed circuit board according to a second embodiment of the fourth invention. Process map. Referring to FIG. 13 to FIG. 22, the first circuit pattern 10, the second electric and pattern 20, the bump 30, the insulating material 4, the carrier 5, the metal layer W, the lightning resistance 60, and the seed layer 7 〇 and plating photoresist 72 are shown. 12 201002168 In the second embodiment of the present invention, in the stage S21, as shown in the i3th to the 15th, the first circuit pattern 1〇 is formed on the carrier 5〇. First, in the stage S2U, as shown in Fig. 13, a carrier 5 having a metal layer 52 laminated on its side is provided. The carrier, according to the description of the first embodiment, serves as a support for forming the first circuit pattern 1 to support the first circuit pattern so that the insulating material 40 can be formed after the first circuit pattern is formed. Laminated process. Next, in step S212, a photosensitive material is laminated on the carrier 5, i.e., on the metal layer 52 of the carrier. Then, in step S213, a photosensitive material is selectively exposed and developed using a photomask or the like to remove a portion thereof. That is, as shown in Fig. 14, a plating resist 6 is formed on the metal layer 52 of the carrier by lithography. The plating resist is formed in accordance with the shape of the first circuit pattern to be formed on the metal layer 52. That is, the metal layer 52 corresponding to the portion of the first circuit pattern is not covered by the plating photoresist 6 而 to expose the outside. In step S214, a conductive substance is formed on the metal layer 52. As shown in Fig. 14, electrolytic plating is performed in a state in which the plating resist 60 of the metal layer 52 is selectively covered. With the electrolytic plating process, a conductive substance can be formed on the metal layer not covered by the plating photoresist. After the electroconductive plating is performed on the metal layer 52, the electroplating photoresist 60 is peeled off. As shown in Fig. 15, by removing the plating resist, the first circuit pattern 1 can be formed on the metal layer. In the conductive material of the present embodiment, it may be formed of copper (Cu). In the step S220, as shown in Fig. 16, the bump 30 is formed on the first circuit pattern 1〇 13 201002168. Then, in the order of 牮_ 11白奴 S23〇, as shown in Figure 17, on the circuit pattern 10 of the younger brother; buried in the ^ circuit pattern by the 邾 bump 3 〇 贝通绝缘And exposed outside ». In the present embodiment, the first S220 and the stage S230 of laminating the insulating material on the stage pattern of the bump 30 are formed by the same process as the first embodiment of the invention. The material of the conductive bumps 30 and the edge material can be the same as in the first embodiment. f, then, in stage U40, as shown in Fig. 18 to Fig. 21,
絕緣材4 0卜# j·、# - & A 形成第一電路圖樣20。本實施例中的第二電 路圖樣，可藉由半加成法來形成。 3在階段S24i中，如第18圖所示，於絕緣材4〇及凸塊 30上，形成種子層70〇種子層係被形成可覆蓋絕緣材及露 出絕緣材的外部之凸塊。另外，種子層與凸塊係電性連接。 種子層70係在電解電鍵過程巾，第二電路圖# 2〇要被形 成的基盤層。本發明的第二實施例中的種子層7〇,係為可 1 根據電解電鍍過程來形成銅（Cu)材質的第二電路圖樣2〇 之薄板的銅箔層（約本實施例中的種子層7〇， 係如第一實施例的說明，可將銅箔層以高溫高壓壓緊在絕 緣材上的製程來形成。 另外’若根據第一實施例的說明，與金屬層52接合的 栽體50，可利用高溫高壓的壓緊製程，從金屬層分離。 亦即，在階段S242中，於種子層70的積層製程後，載體 50係可被除去。 然後’在階段S243中，如第19圖所示，於種子層7〇 14 201002168 及金屬層52上，形成電鍍光阻72。電鐘光阻72可藉由對 於感光性絕㈣進行微㈣㈣形成。钱綠，係整體 地覆蓋金屬層52,並選擇性地覆蓋種子層。 電鍍光阻72,係被形成可使種子層^對應第二電路圖 樣20的形狀而被開放。在階段S244中，進行電解電鍍， 於未被電鍍紐覆蓋的種子層7G上，形成導電性物質。被 形成於種子層上的導電性物質，係成為第二電路圖樣2〇。 因此’導電性物質可為鋼（CU )。 / 'ΐ. 電解電鍍過程之後，在階段8245中，如第2〇圖所示， 除去電鍍光阻72。藉由電鍍光阻被剝離，種子層7〇及金 屬層52被露出外部。 在1¾ #又S246中，如第21圖所示，姓刻被露出在外部 的種子層70及金屬層快速蝕刻（Flashetching)被形 成於第二電路圖樣20的圖樣間的種子層7〇。並且，蝕刻 覆蓋第一電路圖樣1〇的金屬層52。若根據本發明的第二 實施例，可供給蝕刻溶液，蝕刻金屬性物質的種子層7〇及 金屬層52。若種子層及金屬層被蝕刻，則第一電路圖樣係 被埋入絕緣材40中，而第二電路圖樣2〇則被形成於絕緣 材40上。 接著，在階段S250中，如第22圖所示，加壓被形成 於絕緣材4 0上的第二電路圖樣2 0，使第二電路圖樣被埋 入絕緣材。如第21圖所示，第二電路圖樣係從絕緣材4〇 上絡出。以第二電路圖樣被露出的狀態，來進行壓平製程。 藉由第二電路圖樣被埋入絕緣材，圖樣間的絕緣可靠性可 15 201002168 被提高。 若根據本發明的第二實施例，第—電路圖樣！〇及第二 電路圖樣20,係可藉由半加成法，形成μα, # m (線寬/線間距；u / bpace )的尚密度微細圖樣。 藉由形成微細電路圓樣’成為可實現料電子元件的構裝 及導線接合有利的微細間距。 另外’如第22圖所示，藉由第-電路圖樣1〇及第二 電路圖樣20被埋人絕緣材4Q，可提供被薄型化、已提言 絕緣可靠性的印刷電路基板。 门 以下’基於第23圖〜第u阁始。口〜上 弟32圖，說明依據本發明的第 三實施例的印刷電路基版的製造方法。 第23圖係表示依據本發明的第三實施例之印刷電路基 ㈣製造方法圖〜第32圖係表示依據本 發明的第三實施例之印刷電路基板的製造方法的製程圖。 若參照第24圖〜第32圖’則第一電路圖樣1〇、第二電路 圖樣20、凸塊30、絕緣材4〇、載體5〇、金屬層η、㈣ 光阻8〇、導電層82、以及蝕刻光阻84係被表示。 本發明的第三實施例，在階段S310中，如第24圖〜 第26圖所示’於载體上形成第一電路圖樣1〇。 b若根據本實施例，在階段训中，如第24圖所示， 提供-種在其一面已積層有金屬層52之載體％。載體係 如第一實施例的說明，作為可使第—電路圖樣1(>形成的支 夺體支持帛電路圖樣，以使在形成第—電路圖樣後， 16 201002168 可進行絕緣材4〇的積層製程。 在又S312中’於載體5〇上，亦即於載體的金屬層 2上，積層感光性物質。然後，在階段s3u中，使用光 罩專，選擇性地曝光、顯像感光性物質，來除去其一部分。 亦即’如第25圖所*，以微影方式，於載體金屬層”上， 形成姓刻綠80。㈣光阻8Q係覆蓋對應第—電路圖樣 10的部分之金屬層。 本發明的第三實施例中’藉由選擇性地钱刻金屬層 52，第一電路圖樣1〇被形成。在階段幻14中，以蝕刻光 阻已被形成於金屬層52上的狀態，供給蝕刻溶液：選 擇性地蝕刻金屬層。被蝕刻光阻8〇覆蓋的金屬層沒有被蝕 刻，而保留於載體50上。因此’如第26圖所示，藉由除 去蝕刻光阻80,第一電路圖樣1〇會被形成於載體5〇上。 然後，在階段S320中，如第27圖所示，於第一電路 圖樣1〇上形成導電性凸塊3〇。接著，在階段S33〇中，如 第28圖所示，於第一電路圖樣1〇上積層絕緣材4〇，使第 一電路圖樣被埋入絕緣材40中。並且，凸塊3〇貫通絕緣 材而露在外部。本實施例中的在第一電路圖樣上形成凸塊 30的階段S320及在第一電路圖樣上積層絕緣材4〇的階段 S330，可利用與本發明的第一實施例相同的製程來進行p 導電性凸塊及絕緣材40的材質，亦可使用與第—實施例才 同者。 在階段S340中’如第29圖〜第31圖所示，於絕緣材 40上形成第二電路圖樣20。在階段S341中，如第29圖所 17 201002168 示，於絕緣材及凸塊30上，積層 腐 .,, 層82。導電層82係 被形成可覆蓋絕緣材及露出絕緣 爲尨Ο·、ν» „ 何幻外部的凸塊。此導電 層係成為第二電路圖樣20的金屬声。 s 本只施例的導電層可 為銅材質的銅箔層。導電層82，俜 .^ 係如本發明的第一實施例 的說明，可根據以高溫高壓將銅箱 自層壓緊在絕緣層上的製 程而被形成。利用壓緊製程， •i電f生連接導電層與凸塊。 本發明的第三實施例中的壓緊製 2 系取釭，可由5〜30kgf/ cm的壓力及i5(rc以上的The insulating material 40b#j·, #- & A forms the first circuit pattern 20. The second circuit pattern in this embodiment can be formed by a semi-additive method. 3 In the step S24i, as shown in Fig. 18, a seed layer 70 is formed on the insulating material 4 and the bump 30, and the seed layer is formed to cover the outer surface of the insulating material and the exposed insulating material. In addition, the seed layer is electrically connected to the bump. The seed layer 70 is in the electrolytic key process towel, and the second circuit diagram #2 is formed into a base layer. The seed layer 7〇 in the second embodiment of the present invention is a copper foil layer of a second circuit pattern of a copper (Cu) material according to an electrolytic plating process (about the seed in this embodiment) The layer 7 is formed by a process of pressing the copper foil layer on the insulating material at a high temperature and high pressure as described in the first embodiment. Further, if the metal layer 52 is bonded according to the description of the first embodiment, The body 50 can be separated from the metal layer by a high temperature and high pressure pressing process. That is, in the step S242, after the layering process of the seed layer 70, the carrier 50 can be removed. Then, in the step S243, As shown in Fig. 19, on the seed layer 7〇14 201002168 and the metal layer 52, a plating resist 72 is formed. The electric clock photoresist 72 can be formed by micro (four) (four) for the photosensitive (four). The green color is integrally covered with the metal layer 52. And selectively covering the seed layer. The electroplating photoresist 72 is formed such that the seed layer is opened corresponding to the shape of the second circuit pattern 20. In the step S244, electrolytic plating is performed, which is not covered by the plating Conductive substance is formed on the seed layer 7G The conductive material formed on the seed layer is the second circuit pattern. Therefore, the conductive material may be steel (CU). / 'ΐ. After the electrolytic plating process, in stage 8245, as in the second layer As shown in the figure, the plating resist 72 is removed. The plating resist is peeled off, and the seed layer 7 and the metal layer 52 are exposed to the outside. In the 13⁄4 #又S246, as shown in Fig. 21, the surname is exposed to the outside. The seed layer 70 and the metal layer are flashetched by the seed layer 7 形成 between the patterns of the second circuit pattern 20. And, the metal layer 52 covering the first circuit pattern 1 蚀刻 is etched. In the second embodiment, the etching solution can be supplied to etch the seed layer 7 of the metallic substance and the metal layer 52. If the seed layer and the metal layer are etched, the first circuit pattern is buried in the insulating material 40, and the second circuit The pattern 2 is formed on the insulating material 40. Next, in step S250, as shown in Fig. 22, the second circuit pattern 20 formed on the insulating material 40 is pressurized, so that the second circuit pattern is Buried insulation material. As shown in Figure 21, the second circuit diagram It is connected from the insulating material 4, and the flattening process is performed in a state where the second circuit pattern is exposed. By the second circuit pattern being buried in the insulating material, the insulation reliability between the patterns can be improved by 15 201002168. According to the second embodiment of the present invention, the first circuit pattern 〇 and the second circuit pattern 20 can be formed by a semi-additive method to form μα, # m (line width/line spacing; u / bpace ) Density fine pattern. By forming a microcircuit circle', it becomes an advantageous fine pitch for the construction of the electronic component and wire bonding. In addition, as shown in Fig. 22, the first circuit pattern and the second circuit are shown. The pattern 20 is buried in the insulating material 4Q, and a printed circuit board which is thinned and has an insulation reliability has been provided. The following is based on the 23rd figure ~ the first u. Port-upper 32 shows a method of manufacturing a printed circuit board according to a third embodiment of the present invention. Fig. 23 is a view showing a manufacturing method of a printed circuit board according to a third embodiment of the present invention. Fig. 32 is a process chart showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention. Referring to FIGS. 24 to 32, the first circuit pattern 1 〇, the second circuit pattern 20, the bump 30, the insulating material 4 〇, the carrier 5 〇, the metal layer η, the (4) photoresist 8 〇, the conductive layer 82 And the etching photoresist 84 is shown. In the third embodiment of the present invention, in the step S310, as shown in Figs. 24 to 26, the first circuit pattern 1 is formed on the carrier. b According to the present embodiment, in the stage training, as shown in Fig. 24, a carrier % having a metal layer 52 laminated on one side thereof is provided. The carrier is as described in the first embodiment, as the circuit pattern 1 (> formed by the supporting body is supported by the circuit pattern so that after the formation of the first circuit pattern, 16 201002168 can be made of the insulating material. In addition, in S312, a photosensitive material is laminated on the carrier 5, that is, on the metal layer 2 of the carrier. Then, in the stage s3u, a photomask is used to selectively expose and develop photosensitivity. Substance, to remove a part of it. That is, as shown in Fig. 25, in the form of lithography, on the carrier metal layer, the formation of the surname green 80. (4) The photoresist 8Q covers the portion corresponding to the first circuit pattern 10. Metal layer. In the third embodiment of the present invention, the first circuit pattern 1 is formed by selectively etching the metal layer 52. In the stage 12, an etching photoresist has been formed on the metal layer 52. a state in which an etching solution is supplied: the metal layer is selectively etched. The metal layer covered by the etched photoresist 8 没有 is not etched but remains on the carrier 50. Therefore, as shown in Fig. 26, by removing the etching photoresist 80, the first circuit pattern 1〇 will be formed in Then, in step S320, as shown in Fig. 27, a conductive bump 3 is formed on the first circuit pattern 1〇. Then, in step S33, as shown in Fig. 28, The first circuit pattern is buried in the insulating material 40 on the first circuit pattern 1 。, and the bump 3 〇 penetrates the insulating material to be exposed to the outside. In the first circuit in the embodiment The step S320 of forming the bumps 30 on the pattern and the step S330 of laminating the insulating material 4〇 on the first circuit pattern can be performed by using the same process as the first embodiment of the present invention to perform the p-conductive bumps and the insulating material 40. The material may be the same as that of the first embodiment. In the step S340, as shown in Fig. 29 to Fig. 31, the second circuit pattern 20 is formed on the insulating material 40. In the step S341, as in the 29th Fig. 17 201002168 shows that on the insulating material and the bumps 30, a layer of rot., layer 82 is formed. The conductive layer 82 is formed to cover the insulating material and expose the insulating material as a bump of 尨Ο·, ν» „ The conductive layer is the metal sound of the second circuit pattern 20. s The conductive layer of the embodiment can be The copper foil layer of the copper material. The conductive layer 82, which is described in the first embodiment of the present invention, can be formed according to a process of laminating the copper box to the insulating layer at a high temperature and high pressure. The pressing process, the electric conductive layer and the bump are connected. The pressing system 2 in the third embodiment of the present invention can take a pressure of 5 to 30 kgf/cm and an i5 (rc or more).
戾來進仃。與絕緣材40及第 -電路圖樣1〇接合的載體5〇，可利用高溫高屋的歷緊製 程’從絕緣材及第一電路圖樣1〇分離。亦即，在階段⑽ 中’於導電層82的積層製程後，载體5〇會被除去。 在階段S343中’如第30圖所示，於導電層82及第一 電路圖樣1G上形成㈣光@ 84。若根據第—實施例的說 月钕刻光阻84可藉由對於被積層於導電層82上的感光 f生、’€緣材進行微影製程來形成。並且，第一電路圖樣1〇及 絕緣材40係被蝕刻光阻84覆蓋。另一方面，蝕刻光阻84 係部分地覆蓋導電層82。亦即，蝕刻光阻84僅覆蓋對應 第一第路圖樣20的導電層82的一部分。 在1¾奴S344中，如第3〇圖所示，以形成有蝕刻光阻 84的狀態，供給蝕刻溶液，選擇性地蝕刻導電層82。被蝕 刻光阻84覆蓋的第—電路圖樣10、絕緣材40、以及導電 層82的一部分，不會被蝕刻。如第31圖所示，蝕刻製程 之後，若除去蝕刻光阻84，則第二電路圖樣2〇被形成於 絕緣材40上。 18 201002168 然後在階段S350中，如第32圖所示，加壓第二 路圖樣2 0，伟楚一布 尤乐—電路圖樣被埋入絕緣材40。如第31圖 " 電路圖樣係露出絕緣材上，於第二電路圖樣露 出的狀心下，進行壓平製程。藉由第二電路圖樣被埋入絕 緣材_樣間的絕緣可靠性可被提高。 右根據本發明的第三實施例，藉由以消減法來形成第 圖樣10及弟二電路圖樣2〇，可減少在半加成法中 所要求的叩貴的除膠渣及化學鍍銅工時。另外，亦可減少 在電解電链製程中所要求的製程時間。 ，本發明的第三實施例中的第一電路圖樣10 ,係藉由蝕 刻製程破形成。因此，㈣製程特性上，冑tb外部的圖樣 上°卩的寬度，係被形成較被埋入絕緣材40中的圖樣下部的 寬度大。亦即，藉由側面蝕刻’電路圖樣的剖面成為梯形。 藉由第一電路圖樣10的上部的寬度被形成較寬，導線接合 夺導線接合的接合面積可較寬。因此，可提高導線接合 的可靠性。 另外，如第32圖所示，藉由第一電路圖樣及第二 電路圖樣20被埋入絕緣材4〇，可提供被薄型化、已提高 絕緣可靠性的印刷電路基板。 以上，已參照本發明的較佳實施例作說明，但請理解， 只要是該技術領域中具有通常知識者，便可於不脫離被記 载於申請專利範圍中的本發明的思想及領域的範圍内，將 本發明作多樣地修正及變更。 19 201002168 【圖式簡單說明】 第1圖係表示依據本發明的第一實施例之印刷電路基 板的製造方法的流程圖。 第2圖係表示依據本發明的第一實施例之印刷電路基 板的製造方法的製程圖。 第3圖係表示依據本發明的第—實施例之印刷電路基 板的製造方法的製程圖。 帛4圖係表不依據本發明的第-實施例之印刷電路基 板的製造方法的製程圖。 第5圖係表示依據本發明的第一實施例之印 板的製造方法的製程圖。 土 第6圖係表示依據本發 板的製造方法的製程圖。 第7圖係表示依據本發 板的製造方法的製程圖。 第8圖係表示依據本發 板的製造方法的製程圖。 第9圖係表示依據本發 板的製造方法的製程圖。 第1〇圖係表示依據本發 板的製造方法的製程圖。 第11圖係表示依據本發 板的製造方法的製程圖。 明的第一實施例之印刷電路基 明的第一實施例之印刷電路基 明的第一實施例之印刷電路基 月的第一實施例之印刷電路基 月的第一實施例之印刷電路基 月的第一實施例之印刷電路基 20 201002168 第12圖係表千# i τ衣不依據本發明的第二實施例之印刷電路基 板的製造方法的流程圖。 第1圖係表示依據本發明的第二實施例之印刷電路基 板的製造方法的製程圖。 第1圖係表不依據本發明的第二實施例之印刷電路基 板的製造方法的製程圖。 第15圖係表不依據本發明的第二實施例之印刷電路基 板的製造方法的製程圖。 第16圖係表示依據本發明的第二實施例之印刷電路基 板的製造方法的製程圖。 第17圖係表示依據本發明的第二實施例之印刷電路基 板的製造方法的製程圖。 第1 8圖係表示依據本發明的第二實施例之印刷電路基 板的製造方法的製程圖。 第19圖係表示依據本發明的第二實施例之印刷電路基 板的製造方法的製程圖。 第2〇圖係表示依據本發明的第二實施例之印刷電路基 板的製造方法的製程圖。 第21圖係表示依據本發明的第二實施例之印刷電路基 板的製造方法的製程圖。 第22圖係表示依據本發明的第二實施例之印刷電路基 板的製造方法的製程圖。 第23圖係表示依據本發明的第三實施例之印刷電路基 板的製造方法的流程圖。 21 201002168 第24圖係表千# I & '、依據本發明的第三實施例之印刷電路基 板的製造方法的释程圖。 第25圖係表不依據本發明的第三實施例之印刷電路基 .板的製造方法的製程圖。 第2目係表不依據本發明的第三實施例之印刷電路基 板的製造方法的製程圖。 第27圖係表示依據本發明㈣三實施例之印刷電路基 板的製造方法的製程圖。 土 第28圖係表示依據本發明的第三實施例之印刷電路基 板的製造方法的製程圖。 第29圖係表示依據本發明的第三實施例之印刷電路美 板的製造方法的製程圖。 土 第3〇圖係表示依據本發明的第三實施例之印刷電路灵 板的製造方法的製程圖。 土 第31圖係表示依據本發明的第三實施例之印刷電路基 板的製造方法的製程圖。 第32圖係表不依據本發明的第三實施例之印刷電路基 板的製造方法的製程圖。 土 22 201002168 【主要元件符號說明】 1 〇:第一電路圖樣 3 0 :凸塊 50 :載體 54 :第一金屬層 60 :電鍍光阻 64 :蝕刻光阻 72 :電鍍光阻 82 :導電層 20 :第二電路圖樣 40 :絕緣材 5 2 :金屬層 56 :第二金屬層 62 :導電層 70 :種子層 80 :蝕刻光阻 84 :蝕刻光阻 23Come and enter. The carrier 5, which is joined to the insulating material 40 and the first-circuit pattern, can be separated from the insulating material and the first circuit pattern by the high-temperature high-rise process. That is, after the layering process of the conductive layer 82 in the stage (10), the carrier 5 is removed. In the step S343, as shown in Fig. 30, (4) light @84 is formed on the conductive layer 82 and the first circuit pattern 1G. According to the first embodiment, the moon-shaped photoresist 84 can be formed by performing a lithography process on the photosensitive material deposited on the conductive layer 82. Further, the first circuit pattern 1 and the insulating material 40 are covered by the etching photoresist 84. On the other hand, the etch photoresist 84 partially covers the conductive layer 82. That is, the etch photoresist 84 covers only a portion of the conductive layer 82 corresponding to the first first pass pattern 20. In the Slave S344, as shown in Fig. 3, an etching solution is supplied in a state where the etching resist 84 is formed, and the conductive layer 82 is selectively etched. The first circuit pattern 10, the insulating material 40, and a portion of the conductive layer 82 covered by the etched photoresist 84 are not etched. As shown in Fig. 31, after the etching process, if the etching photoresist 84 is removed, the second circuit pattern 2 is formed on the insulating material 40. 18 201002168 Then in stage S350, as shown in Fig. 32, the second pattern 20 is pressurized, and the circuit pattern is buried in the insulating material 40. As shown in Figure 31, the circuit pattern is exposed on the insulating material, and the flattening process is performed under the shape of the second circuit pattern. The insulation reliability by embedding the insulating material in the second circuit pattern can be improved. According to the third embodiment of the present invention, by forming the pattern 10 and the second circuit pattern 2 by the subtraction method, the expensive desmear and electroless copper plating required in the semi-additive method can be reduced. Time. In addition, the process time required in the electrolytic chain process can be reduced. The first circuit pattern 10 in the third embodiment of the present invention is formed by an etching process. Therefore, in the (four) process characteristics, the width of the pattern on the outer portion of the 胄tb is formed to be larger than the width of the lower portion of the pattern buried in the insulating material 40. That is, the cross section of the circuit pattern by the side etching is trapezoidal. By the width of the upper portion of the first circuit pattern 10 being formed wider, the bonding area of the wire bonding wire bonding can be made wider. Therefore, the reliability of wire bonding can be improved. Further, as shown in Fig. 32, by embedding the insulating material 4 in the first circuit pattern and the second circuit pattern 20, it is possible to provide a printed circuit board which is thinned and has improved insulation reliability. The above has been described with reference to the preferred embodiments of the present invention, but it should be understood that those skilled in the art can devise without departing from the spirit and scope of the invention as described in the appended claims. The present invention has been variously modified and changed within the scope. 19 201002168 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing a method of manufacturing a printed circuit board according to a first embodiment of the present invention. Fig. 2 is a process view showing a method of manufacturing a printed circuit board according to the first embodiment of the present invention. Fig. 3 is a process diagram showing a method of manufacturing a printed circuit board according to a first embodiment of the present invention. Fig. 4 is a process diagram showing a method of manufacturing a printed circuit board according to the first embodiment of the present invention. Fig. 5 is a process view showing a method of manufacturing a printing plate according to the first embodiment of the present invention. Fig. 6 is a process diagram showing the manufacturing method according to the present invention. Fig. 7 is a view showing a process chart according to the manufacturing method of the present board. Fig. 8 is a view showing a process chart according to the manufacturing method of the present board. Fig. 9 is a view showing a process chart according to the manufacturing method of the present board. The first drawing shows a process chart according to the manufacturing method of the present board. Fig. 11 is a view showing a process chart according to the manufacturing method of the present board. The printed circuit of the first embodiment of the printed circuit of the first embodiment of the present invention is the printed circuit of the first embodiment of the printed circuit of the first embodiment of the base of the printed circuit. Printed circuit base 20 of the first embodiment of the month 201002168 Fig. 12 is a flow chart showing a method of manufacturing a printed circuit board according to the second embodiment of the present invention. Fig. 1 is a process view showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention. Fig. 1 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention. Fig. 15 is a process chart showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention. Figure 16 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention. Figure 17 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention. Fig. 18 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention. Figure 19 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention. Fig. 2 is a process view showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention. Figure 21 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention. Figure 22 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention. Figure 23 is a flow chart showing a method of manufacturing a printed circuit board in accordance with a third embodiment of the present invention. 21 201002168 Fig. 24 is a release diagram of a method of manufacturing a printed circuit board according to a third embodiment of the present invention. Figure 25 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention. The second item is a process chart showing a method of manufacturing a printed circuit board according to the third embodiment of the present invention. Figure 27 is a process diagram showing a method of manufacturing a printed circuit board according to the third embodiment of the present invention. Fig. 28 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention. Figure 29 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention. Fig. 3 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention. Fig. 31 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention. Figure 32 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention. Earth 22 201002168 [Description of main components] 1 〇: First circuit pattern 3 0 : Bump 50 : Carrier 54 : First metal layer 60 : Plating photoresist 64 : Etching photoresist 72 : Plating photoresist 82 : Conductive layer 20 : second circuit pattern 40 : insulating material 5 2 : metal layer 56 : second metal layer 62 : conductive layer 70 : seed layer 80 : etching photoresist 84 : etching photoresist 23