200938022 〜-A|說明： •【發明所屬之技術領域】 -本發明係有關於-種電路板及其製法，尤指一種 電凸塊結構之電路板及其製法。 【先前技術】 隨著電子產業的蓬勃發展，電子產品之外型趨向輕薄 在功能上則逐漸邁人高性能、高功能、高速度化的 I…。而覆晶式(FUP Chip)半導體封裝技術為一種 ^先進之半導體封裝技術，在現行覆晶式⑺^半導 體封裝技術中，係於半導體晶片上設有電極焊塾，並於該 ^焊塾上形成焊錫凸塊，且在—具有電性連接墊之封裝 形成位於電性連接墊表面之料凸塊，俾藉由該兩 者之導電凸塊電性連接，以提供該半導體晶片與該 板電性連接。 、土 处由於越來越多的產品設計趨向於小型化、高速度、多 力月b因此，覆晶技術的應用範圍將不斷擴大，成爲一 β標準的晶片封裝技術，相較於打線接合（he如⑹技 術’覆晶技術之特徵在於半導體晶片與封裝基板間的電性 :接係透過焊錫凸塊而非一般之金線，而該種覆晶技術之 優點在於其可提高封裝密度以降低封裝元件尺寸’同時， 該種覆晶技術不需使用長度較長之金線，故可提高電性性 ^。再者’後續為提供該封裝基板與外界電子裝置電性連 接，通常必彡I於該封裝基板底面植設複數矩陣式排列焊 110647 5 200938022 .塾上電：=AilF圖’係為習知於電路板之電性連接 .墊上$卿切電凸柱 u生運接 1A圖所示，係於一夺…：成谇錫材料之製法。如第 路板本體10上形成絕緣保護 之笔 中形成複數對應之開孔uo以露出H邑緣保護層U 第1B圖所示，接著於該電㈣⑼1接塾1〇1;如 表面及其開孔m中形成導==_保護層I】 於該導雷屛月多閲第1C圖’復 於”“電層12上形成阻層13，且該阻層 二 ❹ 口 130’以露出形成於該電性連接塾汗 請參閱第Π)圖，接著藉由該導電層12進行之電於 該電性連接墊101上形成導電凸塊14;請參閱鍍第 =於 之後移除該阻層13及其所覆蓋 •圖’ =4 閱第1F圖，最後以印刷方式，於該4 凸塊14上形成係如焊錫之結合材料15。 导電 e 或如第^2B圖所示，係顯示以電鍍方式於該 14上電鍍形成結合材料15之製程。如第^圖所 提供-係如第iD圖所示之結構，接著再進行電鍍製程，’ 以於該導電凸塊14上電鍍形成結合材料15;請參閱 圖’之後再移除該阻層13及其所覆蓋之導電層12，以· 出該導電凸塊14及其上之結合材料15。 路 惟，採用模板印刷亦或電鍍方式於該導電凸塊14上 形成結合材料15，當該電性連接墊m之間的間距持芦 縮減時，由於該導電凸塊14凸出形成於該絕緣保護層二 表面上，並且具有位於該絕緣保護層1 1上之環圈1 4 1， 110647 6 200938022 ..”^叮塊14之環圈141佔用絕緣保護層n表面上 .伤空間’使該些導電凸塊14之間的間距受環圈ΐ4ι .之限制’而無法縮小；且該環目141之間的過於接近，容 易=該結合材料15於迴焊（^㈣製程受熱炫融時 有溫流現象，使該此社人从少丨，r 二、σ材料1 5之間於迴焊製程中發 橋接而產生短路。 因此，鑒於上述之問題，如何避免習知技術中導電凸 塊之間的間距過大，不易提供細間距，而造成後續结200938022~-A|Description: • Technical field to which the invention pertains - The present invention relates to a circuit board and a method of manufacturing the same, and more particularly to a circuit board of an electric bump structure and a method of fabricating the same. [Prior Art] With the booming development of the electronics industry, the appearance of electronic products tends to be thin and light. In terms of functions, it is gradually becoming high-performance, high-function, and high-speed. The flip chip (FUP Chip) semiconductor package technology is an advanced semiconductor package technology. In the current flip chip (7) semiconductor package technology, an electrode pad is provided on a semiconductor wafer, and the solder pad is mounted on the solder pad. Forming a solder bump, and forming a bump on the surface of the electrical connection pad in the package having the electrical connection pad, and electrically connecting the conductive bumps of the two to provide the semiconductor wafer and the board Sexual connection. As more and more product designs tend to be miniaturized, high-speed, and more powerful, the application range of flip chip technology will continue to expand, becoming a β-standard chip packaging technology compared to wire bonding ( He (6) Technology 'Flip-chip technology is characterized by electrical properties between the semiconductor wafer and the package substrate: the connection is through the solder bumps instead of the general gold wire, and the flip chip technology has the advantage that it can increase the package density to reduce Package element size 'At the same time, this kind of flip chip technology does not need to use a long length of gold wire, so it can improve the electrical properties ^. In addition, to provide the package substrate and the external electronic device to provide electrical connection, usually must A plurality of matrix arrangement weldings 110647 5 200938022 are implanted on the bottom surface of the package substrate. The power supply: = AilF diagram is a conventional electrical connection of the circuit board. The pad is placed on the pad. The method is as follows: a method for forming a tin-tin material. For example, a plurality of corresponding openings uo are formed in the pen forming the insulation protection on the body plate 10 to expose the H-edge protective layer U as shown in FIG. 1B, and then Connected to the electricity (4) (9) 1〇1; if the surface and its opening m form a guide == _ protective layer I] in the guide 屛 多 多 第 第 第 第 第 第 第 第 第 第 第 “ “ “ “ 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电The second port 130' is exposed to be formed in the electrical connection, and the second embodiment is formed on the electrical connection pad 101. The conductive bumps 14 are formed on the electrical connection pad 101; After the resist layer 13 is removed and its coverage is shown in FIG. 1 = 4, the first FF is read. Finally, a bonding material 15 such as solder is formed on the 4 bumps 14 by printing. Conductive e or as shown in Fig. 2B shows a process of electroplating the bonding material 15 on the 14 to form the bonding material 15. As shown in FIG. 4, the structure is as shown in the i-th diagram, and then an electroplating process is performed, to form a bonding material 15 on the conductive bumps 14; please refer to FIG. And the conductive layer 12 covered by the conductive layer 14 and the bonding material 15 thereon. Lu Wei, the stencil printing or electroplating is used to form the bonding material 15 on the conductive bumps 14. When the spacing between the electrical connection pads m is reduced, the conductive bumps 14 are convexly formed on the insulation. On the surface of the protective layer 2, and having the ring 1 4 1, 110647 6 200938022 on the insulating protective layer 1 , the ring 141 of the block 14 occupies the surface of the insulating protective layer n. The spacing between the conductive bumps 14 is limited by the ring ring '4', and cannot be reduced; and the ring eyes 141 are too close to each other, and it is easy to = the bonding material 15 is reflowed (^(4) process is heated and smelt The phenomenon of warm current causes the company to short-circuit between the second sputum, r 2 and σ material 15 in the reflow process. Therefore, in view of the above problems, how to avoid the conductive bumps in the prior art The spacing between the two is too large to provide fine pitch, resulting in subsequent knots
料受熱炫融容易因溢流造成短路等問題，實 解決的課題。 人 【發明内容】 鑒於上述習知技術之缺點，本發明之主要目的係提供 一種具導電凸塊結構之電路板及其製法，能縮小導電凸塊 之間距’以提供細間距。 本心明之再一目的係提供一種具導電凸塊結構之電 路板及其衣法，此提供導電凸塊細間距以避免後續結合材 β料熱融而溢流，發生結合材料橋接而產生短路。 本發明之另一目的係提供一種具導電凸塊結構之電 路板及其衣法，能提昇結合材料於迴焊後，接著於導電凸 塊表面之抗推拉應力強度。 為達上述及其他目的，本發明揭露一種具導電凸塊結 構之電路板，係包括：電路板本體，其至少-表面具有複 數電性連接墊，且該電路板本體上具有絕緣保護層，於該 絕緣保護層中具有對應該電性連接塾之開孔，以外露出該 7 ]10647 200938022 包·二< π t;以及導電凸塊’係設於該電性連接墊上，該 •導電凸塊上具有一凸柱，該凸柱橫切面面積尺寸小於該導 、電凸塊橫切面面積尺寸，並凸出於該絕緣保護層上表面。 依上述結構，該導電凸塊及其上之凸柱係由錫（Sn)、 鉛（Pb)、銀（Ag)、銅（Cu)、鋅（Zn)、鉍（Bi)、鎳（Ni)、鈀 (Pd)及金（Au)所組成群組之其中一者所製成。該電路板復 包括有第一導電層，係設於該電性連接墊與導電凸塊之 間、以及絕緣保護層開孔與導電凸塊之間；另於該導電凸 ❹塊及其上之凸柱上設有結合材料，其中，該結合材料係由 錫(Sn)、鉛⑽、銀(Ag)、銅(Cu)、鋅(Zn)、鉍⑻）、鎳 (N!)、紅⑽及金（Au)所組成群組之其中一者所製成。該 電路板又復包括有第二導電層，係設於該導電凸塊及其上 包括^ 種具導電凸塊結構之電路板製法，係 參 邮日〃至夕一表面形成有複數電性連接墊之電路板本 租’且於該電路板本體上形成—絕緣保護層，㈣ =中對應該電性連接塾的位置處形成有開孔^外露出 ”電性連接墊;於該電性連接墊、 面上形成—第—導電層隻層及-開孔表 哕镇π “ 这導电層上形成-第-阻層， 之Π π ΠΤ 尺寸小於該絕緣保護層 成於該絕緣保護層開孔之電性連接整上電鐘形 導電凸塊上之且::·㈣一阻層之第一開口中形成位於該 塊上之凸柱，以及移除該第-阻層及其所覆蓋之 110647 8 200938022 v m，以露出該導電凸塊及其上之凸柱，且該凸柱 南於絕緣保護層之上表面。 •上述製法復包括於該導電凸塊及其上之凸柱以印刷 或電鏟形成結合材料。於該導電凸塊上電鍵形成結合材料 之製法，係包括：於該絕緣保護層、導電凸塊及其上之凸 柱上形成一第二導電層；於該第二導電層上形成-第二 阻層，且於該第二阻層中形成有對應該導電凸塊及凸柱之 弟二開口，以露出該第二導電層之部份表面；於該第二開 口中之第一導電層上電鍍形成該結合材料；以及移除該 第二阻層及其所覆蓋之第 二導電層。 又依上述之製法，該導電凸塊及其上之凸柱係由錫 (Sn)^^(Pb)^(Ag)>^(Cu)^#(Zn).^(Bi)^(Ni) ^ 鈀⑽及金（Au)所組成群組之其中一者所製成。該結合材 料係由錫⑽、錯⑽'銀㈤'銅(Cu)、_(zn)、鉍㈤、 鎳⑼！）、鈀（Pd)及金（Au)所組成群組之其中一者所製成。 該第一阻層例如為乾膜。 ❹ 目此，本發明之具導電凸塊結構之電路板及其製法， 主要係在導電凸塊上形成較小橫切面面積尺寸之凸柱，而 不佔用絕緣保護層上表面之空間，俾能縮小該些導電凸塊 之間的間距，以提供細間距之導電凸塊；並使形成於該導 =及凸柱上之結合材料避免於迴焊製程中發生溢流 仏接產生短路，且可提升結合材料導電凸塊表面之抗推拉 應力強度。 【實施方式】 110647 9 200938022 …，4由特定的具體實施例說明本發明之實施方 式，熟悉此技蟄之人士可由本說明書所揭示之内容輕易地 •瞭解本發明之其他優點及功效。 二 [第一實施例] 第3A至3G圖，係為詳細説明本發明具導電凸塊結構 之電路板製法的第一實施例剖面示意圖。 請蒼閱第3A圖，首先係在一表面形成有複數電性連 接墊201之電路板本體2〇上形成一絕緣保護層且於 ❹H緣保”蒦層21中形成複數開孔21()以對應露出該電性 連接塾2 01之部份表面。 請參閱第3B圖，於該電性連接替2(n、絕緣保護層 21及其開孔210表面上形成第一導電層22a，該第一導電 層22a主要作為後述電鍍金屬材料所需之電流傳導路 徑，其可由金屬或沉積數層金屬層所構成，如選自銅、錫、 鎳、鉻、鈦等單層金屬、或銅_鉻或錫_鉛等多層金屬結構， 或可使用例如聚乙炔、聚苯胺或有機硫聚合物等導電高分 φ子材料。 請參閱第3C圖，於該第一導電層22a上形成一第一 阻層23a，該第一阻層23a係為乾膜之光阻層 (Photoresist)，其係利用例如貼合等方式形成於該第一 導電層22a表面。 δ月參閱第3D圖，再藉由曝光、顯影等方式加以圖案 化，以使該第一阻層23a形成複數個第一開口 23〇a，以 對應露出該電性連接墊201上之第一導電層22a，且該第 110647 10 200938022 叫Μ 6…a尺寸小於該絕緣保護層Μ之開孔MO尺寸。 . 請參閱第3E圖，進行電鍍（Electroplating)製程， 藉由該第一導電層22a具導電特性，俾在進行電鍍時作為 電流傳導路徑，以在該絕緣保護層21之開孔21〇中的電 性連接墊201上電鍍形成導電凸塊24，且位於該第一阻 層23a之第一開口 230a中形成位於該導電凸塊24上之凸 柱241 ’而該凸柱241橫切面面積尺寸係小於該導電凸塊 24橫切面面積尺寸，該導電凸塊24及其上之凸柱241係 ❹由錫（Sn)、鉛（Pb)、銀（Ag)、銅（Cu)、鋅（Zn)、鉍（Bi)、 鎳（Νι)、鈀（Pd)及金（Au)所組成群組之其中一者所製成。 請參閱第3F圖，接著即可移除該第一阻層23a以及 該第一阻層23a所覆蓋之第一導電層22a，以露出該導電 凸塊24及其上之凸柱241，且該凸柱241高於該絕緣保 護層21之上表面；其中，移除該第一阻層23a及第一導 電層22a之製程係屬習知者，故於此不再為文贅述。由於 該凸柱241橫切面面積尺寸係小於該導電凸塊24橫切面 〇面積尺寸，使該凸柱241未接觸該絕緣保護層21表面， 而無須佔用凸柱於絕緣保護層21上表面之面積，俾得縮 小導電凸塊24之間的間距，以達細間距之使用所需。 請參閱第3G圖，最後，於該導電凸塊24及其上之凸 柱241以印刷方式形成例如為錫金屬之結合材料託。 [第二實施例] 第4A至4C圖，係為詳細説明本發明具導電凸塊結構 之電路板製法的第二實施例剖面示意圖，與前一實施例之 110647 11 200938022 ... π q該導電凸塊上係以電鍍方式形成結合材料。 ‘ 如第4A圖所示，首先，提供一係如第3F圖所示之結 .構，並於該絕緣保護層2卜導電凸塊24及其上之凸柱241 上形成一第二導電層22b;該第二導電層2如主要作為後 述電鍍金屬材料所需之電流傳導路徑，其可由金屬或沉積 數層金屬層所構成，如選自銅、錫、鎳、鉻、鈥等單層金 屬、或銅-鉻或錫-鉛等多層金屬結構，或可使用例如聚乙 炔、聚苯胺或有機硫聚合物等導電高分子材料。 〇 接著’於該第二導電層22b上形成一第二阻層23b， 且於該第二阻層23b中形成有對應該導電凸塊24及凸柱 241之第二開口 23Gb’以露出該第二導電層22b之部份表 面。 如第4B圖所示’於該第二開口 23〇b中之第二導電層 22b上電鍍形成結合材料25。 θ 如IMC圖所示，移除該第二阻層咖及其所覆蓋之 第二導電層22b。The problem that the material is heated and condensed is likely to cause a short circuit due to overflow, and the problem is solved. SUMMARY OF THE INVENTION In view of the above disadvantages of the prior art, the main object of the present invention is to provide a circuit board having a conductive bump structure and a method of fabricating the same, which can reduce the distance between the conductive bumps to provide a fine pitch. A further object of the present invention is to provide a circuit board having a conductive bump structure and a clothing method thereof, which provides a fine pitch of the conductive bumps to prevent the subsequent bonding material from being thermally melted and overflowed, and a bridging of the bonding materials occurs to cause a short circuit. Another object of the present invention is to provide a circuit board having a conductive bump structure and a method of coating the same, which can improve the tensile stress resistance of the bonding material after reflow and then on the surface of the conductive bump. To achieve the above and other objects, the present invention discloses a circuit board having a conductive bump structure, comprising: a circuit board body having at least a surface having a plurality of electrical connection pads, and the circuit board body having an insulating protective layer thereon The insulating protective layer has an opening corresponding to the electrical connection, and the exposed surface is exposed to the 7] 10647 200938022 package · two < π t; and the conductive bump ' is disposed on the electrical connection pad, the conductive bump The upper portion has a convex column, and the cross-sectional area of the protruding column is smaller than the cross-sectional area of the conductive and electric bumps, and protrudes from the upper surface of the insulating protective layer. According to the above structure, the conductive bump and the pillar thereon are made of tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni). Made of one of a group consisting of palladium (Pd) and gold (Au). The circuit board further includes a first conductive layer disposed between the electrical connection pad and the conductive bump, and between the opening of the insulating protective layer and the conductive bump; and the conductive bump block and the conductive bump A bonding material is disposed on the stud, wherein the bonding material is made of tin (Sn), lead (10), silver (Ag), copper (Cu), zinc (Zn), bismuth (8), nickel (N!), red (10) And one of the groups consisting of gold (Au). The circuit board further includes a second conductive layer, and is disposed on the conductive bump and the circuit board method including the conductive bump structure thereon, and the plurality of electrical connections are formed on the surface of the day after the day The circuit board of the pad is rented and formed on the body of the circuit board - an insulating protective layer, (4) = an opening is formed at a position corresponding to the electrical connection port, and an electrical connection pad is formed; the electrical connection is Forming on the pad, the surface - the first layer of the conductive layer and the opening of the surface π π "The conductive layer is formed with a - first resist layer, and then the π ΠΤ dimension is smaller than the insulating protective layer is formed in the insulating protective layer The hole is electrically connected to the upper electric bell-shaped conductive bump: and: (4) forming a stud on the block in the first opening of the resistive layer, and removing the first resistive layer and covering the same 110647 8 200938022 vm to expose the conductive bump and the stud thereon, and the stud is south of the upper surface of the insulating protective layer. • The above method is included in the conductive bump and the stud thereon to form a bonding material by printing or a shovel. Forming a bonding material on the conductive bumps, comprising: forming a second conductive layer on the insulating protective layer, the conductive bumps, and the bumps thereon; forming a second on the second conductive layer a resist layer, and a second opening corresponding to the conductive bump and the pillar is formed in the second resist layer to expose a portion of the surface of the second conductive layer; on the first conductive layer in the second opening Electroplating forms the bonding material; and removing the second resist layer and the second conductive layer covered thereby. According to the above method, the conductive bump and the pillar thereon are made of tin (Sn)^(Pb)^(Ag)>^(Cu)^#(Zn).^(Bi)^(Ni ^ ^ One of the groups consisting of palladium (10) and gold (Au). The bonding material is tin (10), wrong (10) 'silver (five) 'copper (Cu), _ (zn), bismuth (five), nickel (9)! ), one of a group consisting of palladium (Pd) and gold (Au). The first resist layer is, for example, a dry film. In view of the above, the circuit board with the conductive bump structure of the present invention and the manufacturing method thereof are mainly formed on the conductive bumps to form the pillars having the small cross-sectional area size without occupying the space on the upper surface of the insulating protective layer, Reducing the spacing between the conductive bumps to provide fine pitch conductive bumps; and forming the bonding material formed on the conductive and protruding pillars to avoid a short circuit caused by overflow bridging in the reflow process, and Improve the tensile and tensile stress strength of the surface of the conductive bump of the bonding material. [Embodiment] 110647 9 200938022 ..., 4 The embodiment of the present invention is described by a specific embodiment, and those skilled in the art can easily understand the other advantages and effects of the present invention from the contents disclosed in the present specification. [First Embodiment] Figs. 3A to 3G are cross-sectional views showing a first embodiment of a method of manufacturing a circuit board having a conductive bump structure of the present invention in detail. Please refer to FIG. 3A, firstly, an insulating protective layer is formed on a circuit board body 2 on which a plurality of electrical connecting pads 201 are formed, and a plurality of openings 21 are formed in the ❹H edge protection layer 21 to Corresponding to the surface of the portion of the electrical connection 塾201. Referring to FIG. 3B, the first conductive layer 22a is formed on the surface of the electrical connection 2 (n, the insulating protective layer 21 and the opening 210 thereof). A conductive layer 22a is mainly used as a current conduction path required for a plating metal material to be described later, and may be composed of a metal or a plurality of deposited metal layers, such as a single layer metal selected from copper, tin, nickel, chromium, titanium, or copper-chromium. Or a multilayer metal structure such as tin-lead, or a conductive high-score φ sub-material such as polyacetylene, polyaniline or organic sulfur polymer may be used. Referring to FIG. 3C, a first resistance is formed on the first conductive layer 22a. The layer 23a is a photoresist layer of a dry film formed on the surface of the first conductive layer 22a by, for example, bonding. Δ月 Refer to the 3D image, and then expose Patterning, developing, etc., so that the first resist layer 23a forms a plurality The first opening 23〇a is opposite to expose the first conductive layer 22a on the electrical connection pad 201, and the size of the 110647 10 200938022 is 小于6...a is smaller than the size of the opening MO of the insulating protective layer 。. Referring to FIG. 3E, an electroplating process is performed, wherein the first conductive layer 22a has a conductive property, and the iridium serves as a current conduction path during electroplating to have electrical properties in the opening 21 of the insulating protective layer 21. The connecting pad 201 is plated to form a conductive bump 24, and the first opening 230a of the first resistive layer 23a forms a stud 241' on the conductive bump 24, and the cross-sectional area of the stud 241 is smaller than the The conductive bump 24 has a cross-sectional area dimension, and the conductive bump 24 and the protrusion 241 thereon are made of tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn), germanium. (Bi), nickel (Νι), palladium (Pd), and gold (Au) are formed by one of the groups. Referring to Figure 3F, the first resist layer 23a and the first layer can be removed. a first conductive layer 22a covered by a resist layer 23a to expose the conductive bump 24 and the stud 241 thereon, and the stud 24 1 is higher than the upper surface of the insulating protective layer 21; wherein the process of removing the first resistive layer 23a and the first conductive layer 22a is a conventional one, and therefore will not be described herein. The cross-sectional area is smaller than the cross-sectional area of the conductive bump 24, so that the stud 241 does not contact the surface of the insulating protective layer 21, and does not need to occupy the area of the upper surface of the insulating protective layer 21, so that the conductive is reduced. The spacing between the bumps 24 is required to achieve the fine pitch. Referring to FIG. 3G, finally, the conductive bumps 24 and the studs 241 thereon are formed by printing to form a bonding material such as tin metal. . [Second Embodiment] Figs. 4A to 4C are cross-sectional views showing a second embodiment of a circuit board manufacturing method having a conductive bump structure according to the present invention, and 110647 11 200938022 ... π q of the previous embodiment. The bonding material is formed by electroplating on the conductive bumps. As shown in FIG. 4A, first, a structure as shown in FIG. 3F is provided, and a second conductive layer is formed on the insulating protective layer 2 and the conductive bumps 24 and the bumps 241 thereon. 22b; the second conductive layer 2 is mainly used as a current conduction path required for electroplating metal materials described later, and may be composed of metal or a plurality of deposited metal layers, such as a single layer of metal selected from the group consisting of copper, tin, nickel, chromium, and antimony. Or a multilayer metal structure such as copper-chromium or tin-lead, or a conductive polymer material such as polyacetylene, polyaniline or organic sulfur polymer. Then, a second resist layer 23b is formed on the second conductive layer 22b, and a second opening 23Gb' corresponding to the conductive bump 24 and the pillar 241 is formed in the second resist layer 23b to expose the first Part of the surface of the second conductive layer 22b. Bonding material 25 is formed on the second conductive layer 22b in the second opening 23'b as shown in Fig. 4B. θ removes the second resist layer and the second conductive layer 22b covered by it as shown in the IMC diagram.
透過前述製法’本發明復提供一種具導電凸塊結構之 電路板，係包括：電路板本體2〇，其至少一表面具有複 f性連㈣’且該電路板本體2()上具有絕緣保護 層21’該絕緣保護層21中具有對應該電性連接墊之 =孔训’以外露出該電性連接㈣i之部份表面’·以及 導電凸塊24，係設於該電性連接墊2〇1上，其 具有—凸柱241，該凸柱241橫^面面獻 寸小於心電凸塊24橫切面面積尺寸’並凸出於該絕緣 110647 12 200938022 α ,曰。丄 Jl I 1¾ 〇 ‘依上述結構，該導電凸塊24及其上之凸柱241係由 -錫（Sn)、鉛（Pb)、銀（Ag)、銅（Cu)、鋅（Ζη)、鉍（Bi)、鎳 (NO、鈀（Pd)及金（Au)所組成群組之其中一者所製成。該 電路板復包括有第一導電層22a，係設於該電性連接墊 201與導電凸塊24之間、以及絕緣保護層開孔21〇與導 電凸塊24之間，.以及於該導電凸塊24及其上之凸柱 上設有結合材料25。該電路板又包括有第二導電層22b， ❹係設於該導電凸塊24及凸柱241上。 因此，本發明之具導電凸塊結構之電路板及其製法， 主要係在電路板本體之絕緣保護層及電性連接墊上形成 第-導電層及第-阻層，且該第—阻層形成有小於該絕緣 保㈣開孔之第-開口，以於該電性連接塾上電鍵形成導 電凸塊，及於讀第-阻層之第一開口中形成尺寸小於該導 電凸塊之凸柱’俾以縮小該些導電凸塊之間的間距；並使 形成於該導電凸塊上之結合材料避免於迴焊製程中發生 ❹溢流橋接產生短路，且可提升結合材料導電凸 推拉應力強度。 【圖式簡單説明】 凸塊結構之電路板製法 第1Α至1F圖係為習知具導電 之剖面示意圖； 第2A及2B圖係為習知於 料之製法剖面示意圖； 第3A至3G圖係為本發明 導電凸塊上電鍍形成結合材 具導電凸塊結構之電路板製 110647 13 200938022 ^ 〜π 只施例的剖面示思圖，以及 第4Α至4C圖係為本發明具導電凸塊結構之電路板製 法之第二實施例的剖面示意圖。 【主要元件符號說明】 10、20 電路板本體 101 、 201 電性連接墊 11' 21 絕緣保護層 110 、 210 開孔 12 導電層 ❹13 阻層 130 開口 14 ' 24 導電凸塊 141 環圈 15、25 結合材料 22a 第一導電層 22b 第二導電層 @ 230a 第一開口 230b 第二開口 23a 第一阻層 23b 第二阻層 241 凸柱 14 110647According to the foregoing method, the present invention provides a circuit board having a conductive bump structure, comprising: a circuit board body 2, at least one surface having a complex f-connection (four)' and insulation protection on the circuit board body 2 () The layer 21' has a portion of the surface of the insulating protective layer 21 corresponding to the electrical connection pad, and the conductive bump 24 is disposed on the electrical connection pad. 1 , which has a stud 241 which is smaller than the cross-sectional area dimension of the electrocardiographic bump 24 and protrudes from the insulation 110647 12 200938022 α , 曰.丄Jl I 13⁄4 〇' According to the above structure, the conductive bump 24 and the pillar 241 thereon are made of -tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (?n), Manufactured by one of a group consisting of bismuth (Bi) and nickel (NO, palladium (Pd), and gold (Au). The circuit board includes a first conductive layer 22a, and is disposed on the electrical connection pad. A bonding material 25 is disposed between the 201 and the conductive bumps 24, and between the insulating protective layer openings 21 and the conductive bumps 24, and on the conductive bumps 24 and the studs thereon. The second conductive layer 22b is disposed on the conductive bump 24 and the protruding pillar 241. Therefore, the circuit board with the conductive bump structure of the present invention and the manufacturing method thereof are mainly used for the insulating protective layer of the circuit board body. Forming a first conductive layer and a first resistive layer on the electrical connection pad, and the first resistive layer is formed with a first opening smaller than the insulating (four) opening, so that the electrical connection is electrically connected to form a conductive bump, And forming a protrusion smaller than the conductive bumps in the first opening of the read-resist layer to reduce the spacing between the conductive bumps; The bonding material on the conductive bump avoids a short circuit caused by the overflow bridge in the reflow process, and can improve the tensile stress of the conductive material of the bonding material. [Simplified Schematic] Circuit board manufacturing method of the bump structure 1F is a schematic cross-sectional view of a conventional conductive structure; 2A and 2B are schematic cross-sectional views of a conventional method; 3A to 3G are electroconductive bumps on a conductive bump of the present invention to form a bonding material with a conductive bump structure The circuit board system 110647 13 200938022 ^ π The cross-sectional view of only the embodiment, and the 4th to 4th drawings are schematic cross-sectional views of the second embodiment of the circuit board manufacturing method with the conductive bump structure of the present invention. DESCRIPTION OF SYMBOLS 10, 20 Circuit board body 101, 201 Electrical connection pad 11' 21 Insulation protection layer 110, 210 Opening 12 Conductive layer ❹ 13 Resistive layer 130 Opening 14 ' 24 Conductive bump 141 Ring 15, 25 Bonding material 22a First conductive layer 22b second conductive layer @ 230a first opening 230b second opening 23a first resist layer 23b second resist layer 241 stud 14 110647