200931598 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電晶體結構、其製造方法以及具 有此電晶體結構的動態隨機存取記憶體及其製造方法，且 特別是有關於一種薄型電晶體結構、其製造方法以及具有 此薄型電晶體結構之動態隨機存取記憶體及其製造方法。 【先前技術】 ® 動態隨機存取記憶體（DRAM)是覌在半導體及電腦 工業上，最重要且主要的記憶體元件。雖然基於某些技術 上與應用上的因素’使得其他種類的記憶體在整個資訊工 業上的應用亦相當廣泛’但是由於DRAM的高功能與低成 本優勢’所以到目前為止，dram還一直是甩量最大、應 用最廣、售價最低且製造技術上亦最舉足輕重的一種記憶 體。 提供更多記憶容量和更快速的記憶體晶片是1C產業 © 技術發展的原動力之一，隨著大容量記憶體的需求增加， DRAM中單位面積所包含的基本記憶體單位的數量勢必愈 來愈高’因此如何在不增加DRAM面積的情況下，提高記 憶體容量便是諸多半導體製造者所欲積極尋求解決的問 題。 一般來說，有採用位元線折疊法（Folded Bit Line) 的排列方式，來減少位元線接觸窗（BC )的數量，可進而 省下一個BC的空間’來縮減DRAM的大小，但是其能省 200931598 下的空間有限。 【發明内容】 卜止本發月的目的之一是在提供一種薄型電晶體結構、其 ,/ i、'、八有薄型電晶體結構之動態隨機存取記憶體及 丨裝广方法肖以縮小動態隨機存取記憶體中之電晶體結 構，進而在相同單位面積的情況下，提供較大的記憶容量。 I &照本發明的—較佳實施例，-種具有薄型電晶體結 構之動態隨機存取記憶體，其包含複數個薄型電晶體以及 -深埋層連接區。每一電晶體皆位於主動區中，並包含一 鋪區、一源極區以及—閘極區，其中汲極區與源極區位 於閘極區之同-侧，兩者為上下關係配置，且源極區位於 一大傾角佈植區中。其中深埋層連接區設於主動區中，每 一電晶體之汲極區透過此深埋層連接區相互連接，形成一 位元線。 依據本發明之具有薄型電晶體結構之動態隨機存取 S己憶體的製造方法，係於基材的主動區形成一深埋層連接 區’其中深埋層連接區位於基材表面下方之較深處，再於 基材之表面下方形成一大傾角佈植區，接著進行離子植入 製程，於大傾角佈植區中形成複數個薄型電晶體的源極 區’然後進行蝕刻製程，於主動區形成複數個深凹槽，深 凹槽之蝕刻深度達深埋層連接區，以於鄰靠於深凹槽侧面 的深埋層連接區，分別形成一汲極區，其中位於同一深凹 槽同一側的源極區與汲極區為上下關係配置。 200931598 依照本發明的另一較隹實施例，一種薄型電晶體結 構’係形成於一基材之主動區中’並包含一閘極區、一源 極區以及一汲極區。閘極區設於主動區中，並具有一侧 邊。源極區設於主動區的一大傾角佈植區中並位於閘極區 之側邊。汲極區設於主動區中並位於閘極區之側邊且與源 極區同一側。其中源極區與汲極區兩者為上下關係配置。 依據本發明之薄型電晶體結構的製造方法，係於基材 的主動區形成一深埋層’其中深埋層位於基材表面下方之 w 較深處，再於基材之表面下方形成一大傾角佈植區，接著 進行離子植入製程，於大傾角佈植區中形成薄型電晶體的 源極區，然後進行蝕刻製程，於主動區形成一深凹槽，深 凹槽之蝕刻深度達深埋層，以於鄰靠於深凹槽侧面的深埋 層形成一汲極區，且汲極區與源極區位於深凹槽之同一 側，其中位於同一側的源極區與汲極區為上下關係配置。 【實施方式】 © 一般而言，動態隨機存取記憶體（DRAM)的基本記 憶體單位是由一個金屬半場效電晶體和一個電容器所構 成。在DRAM中，由許多的基本記憶體單位組成記憶體陣 列（Memory Array )，並由相對應的字元線（Word Line ) 與位元線（Bit Line)所控制。雖然可瞭解有各種其他的元 件也包括於動態隨機存取記憶體中，然而，為了方便說明 及描述，在此未顯示及說明其他元件。 請參照第1圖，係繪示為本發明一較佳實施例之一種 200931598 具有薄型電晶體結構之動態隨機存取記憶體之剖面示意 •圖。在本實施例中，為了簡化說明，僅採用其中一位元線 上相互連接的四個電晶體結構為例，加以說明。 動態隨機存取記憶體包含有複數個薄型電晶體210, 每一電晶體包含有一閘極區211、一汲極區212以及一源 極區213。在本實施例中，閘極區211係為一嵌壁式閘極 ( Recess Gate)結構，且與基材20之間包含有一閘極氧 化層215。汲極區212與源極區213位於閘極區211之同 β —側’且源極區213垂直於汲極區212之上方，其中源極 區213位於一大傾角佈植區214中。 在本實施例中，動態隨機存取記憶體形成於一基材2〇 之主動區21中，其中主動區21包含一深埋層連接區22, 此深埋層連接區22位於主動區21中，且於基材20表面 下方較深處。 每一電晶體210的汲極區212位於深埋層連接區22 中’經由相接觸而連接在一起。此深埋層連接區22位於 〇 閘極區211下方’且為每一電晶體210所共享的汲極區， 並作為共同的位元線接觸窗（BC)之用，在同一位元線上 之電晶體210共用一條位元線230。藉此可節省許多位元 線接觸窗（BC)之空間，來縮小動態隨機存取記憶體之面 積。 請參照第2圖’其繪示為在本發明一較佳實施例中一 種具有薄型電晶體結構之動態隨機存取記憶體形成深埋 層連接區後之剖面圖。提供一基材20，於基材20中形成 200931598 一主動區21。在本實施例中，基材2G可為P财基材或 N型石夕基材，其材質可以是半導體製造技術中常見的材 質，但卻不限定於此。 接著對主動區21進行掺雜製程，於主動區21中植入 掺雜物，形成-深埋層連接區22位於主動區21中，且位 於基材20表面下方之較深處。在本實施例中，當基材2〇 為P财基材時，貞㈣用N型掺雜物，#基材⑽為凡型 梦基材’則採甩p型掺雜物。 .請參照第3圖’其繪示為在本發明一較佳實施例中一 種薄型電晶體結構之動態隨機存取記憶體形成大傾角佈 植區後之剖面圖。於基材20表面上沉積一光阻層，利用 光罩進行微影製程’將光罩上大傾角佈植區圖案轉移到光 阻上，形成一圖案化光阻層2〇1。 接著對主動區21進行大傾角佈植（Halo Implant)，於 主動區21中，且於基材2〇表面下形成一大傾角佈植區 大傾角佈植區23係用以抑制當源極與沒極的空乏區 域受到閘極的偏壓和源/汲極偏壓的影響而互相短路時發 生接面擊穿效應。 請參照第4圖，其繪示為在本發明一較佳實施例中一 種具有薄型電晶體結構之動態隨機存取記憶體形成源極 區之剖面圖。移除圖案化光阻層2〇1，進行微影製程，形 成另一圖案化光阻層202於基材20上，用以於基材20上 定義出源極圖案，接著進行離子植入製程，於大傾角佈植 區23中形成源極區213。在本實施例中，植入N型掺雜物， 200931598 如磷或坤離子，形成N通道。 • 請參照第5圖，其繪示為在本發明一較佳實施例中一 種具有薄塑電晶體結構之動態隨機存取記憶體形成嵌壁 式閘極之剖面圖。移除圖案化光阻層202,進行微影製程， 形成一圖案化光阻層203於基材20上，在基材20的主動 區21上定義出嵌壁式閘極（Recess Gate)圖案。對基材 20進行蝕刻，以於基材20的主動區21中形成複數個深凹 槽207，作為後續製程完成閘極電極之閘極區211，其中深 ® 凹槽207之蝕刻深度達深埋層連接區22中。 因此，每一電晶體於深埋層連接區22且鄰靠深凹槽 207側面，形成一汲極區212，而且於源極區213之周圍 形成一大傾角佈植區214。其中汲極區212垂直位於淼極 區213之下方，每一電晶體210之汲極區212經由深埋層 連接區22相互連接。 請參照第6圖，其繪示為第5圖中之具有薄型電晶體 結構之動態隨機存取記憶體形成電晶體通道之剖面圖。在 Ο 本實施例中，以氣相沉積法沉積一屏蔽層（screen oxide)， 作為後續之離子佈植掺雜製程時，防止離子在單晶矽基材 中特定晶格面所產生的通道效應。接著進行離子植入，在 主動區21鄰靠深凹槽207側面之源極區213與汲極區212 之間的區域形成一電晶體通道208,用以調整嵌壁式閘極 電晶體之臨界電壓值（Vth)。 進行熱處理製程，如快速退火（RTA)，使植入顯露於 深凹槽207的基材20之電晶體通道之離子活化 200931598 • (activate)’再移除屏蔽層。接著採用一般製程於深凹槽 . 2G7中形成閘極f極，並於源極區213之表面形成源極電 極。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 ❹ 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂’所附圖式之詳細說明如下： 第1圖係繪示為本發明一較佳實施例之一種具有薄型 電晶體結樣之動態隨機存取記憶體之剖面示意圖。 第2圖係繪示為在本發明一較佳實施例中一種具有薄 型電晶體結構之動態隨機存取記憶體形成深埋層連接區 後之剖面圖。 © 第3圖係繪示為第2圖中之具有薄型電晶體結構之動 態隨機存取記憶體形成大傾角佈植區後之剖面圖。 第4圖係繪示為第3圖中之具有薄型電晶體結構之動 態隨機存取記憶體形成源極區之剖面圖。 第5圖係繪示為第4圖中之具有薄型電晶體結構之動 態隨機存取記憶體形成嵌壁式閘極之剖面圖。 第6圖係繪示為第5圖中之具有薄型電晶體結構之動 態隨機存取記憶體形成電晶體通道之剖面圖。 11200931598 IX. Description of the Invention: [Technical Field] The present invention relates to a transistor structure, a method of fabricating the same, a dynamic random access memory having the same, and a method of fabricating the same, and more particularly to A thin transistor structure, a method of fabricating the same, and a dynamic random access memory having the thin transistor structure and a method of fabricating the same. [Prior Art] ® Dynamic Random Access Memory (DRAM) is the most important and important memory component in the semiconductor and computer industries. Although based on certain technical and application factors, other types of memory are widely used in the information industry, but due to the high functionality and low cost of DRAM, dram has been One of the largest, most widely used, lowest-priced, and most technically important memory. Providing more memory capacity and faster memory chips is one of the driving forces behind the 1C industry © technology development. As the demand for large-capacity memory increases, the number of basic memory units per unit area in DRAM is bound to increase. High's way, therefore, how to increase the memory capacity without increasing the DRAM area is a problem that many semiconductor manufacturers are actively seeking to solve. In general, there is a layout of the Folded Bit Line to reduce the number of bit line contact windows (BC), which in turn saves a BC space to reduce the size of the DRAM, but Can save space under 200931598. SUMMARY OF THE INVENTION One of the purposes of the present invention is to provide a thin transistor structure, which has a dynamic random access memory and a wide-area structure with a thin transistor structure. The structure of the transistor in the DRAM, which in turn provides a larger memory capacity in the same unit area. I & preferred embodiment of the invention - a dynamic random access memory having a thin transistor structure comprising a plurality of thin transistors and a deep buried junction region. Each of the transistors is located in the active area, and includes a paving area, a source area, and a gate region, wherein the drain region and the source region are located on the same side of the gate region, and the two are arranged in an upper and lower relationship. And the source region is located in a large dip planting area. The deep buried connection region is disposed in the active region, and the drain regions of each of the transistors are connected to each other through the deep buried connection region to form a bit line. The method for manufacturing a dynamic random access S memory having a thin transistor structure according to the present invention is to form a deep buried connection region in the active region of the substrate, wherein the deep buried junction region is located below the surface of the substrate In the depth, a large dip implanting area is formed under the surface of the substrate, and then an ion implantation process is performed to form a source region of a plurality of thin transistors in the large dip implanting region, and then an etching process is performed to actively A plurality of deep grooves are formed in the region, and the deep grooves are etched to a deep buried connection region to form a drain region adjacent to the deep buried layer connection side of the deep groove, wherein the same deep groove is formed The source region and the drain region on the same side are arranged in an up and down relationship. 200931598 In accordance with another embodiment of the present invention, a thin transistor structure is formed in an active region of a substrate and includes a gate region, a source region, and a drain region. The gate region is located in the active region and has one side. The source region is located in a large dip planting area of the active area and is located on the side of the gate region. The drain region is disposed in the active region and is located on the side of the gate region and on the same side as the source region. The source region and the bungee region are both configured in an up and down relationship. According to the manufacturing method of the thin transistor structure of the present invention, a deep buried layer is formed in the active region of the substrate, wherein the deep buried layer is located deeper below the surface of the substrate, and then forms a large layer below the surface of the substrate. The dip implanting area is followed by an ion implantation process to form a source region of the thin transistor in the large dip implanting area, and then an etching process is performed to form a deep groove in the active region, and the depth of the deep groove is deep. The buried layer forms a drain region adjacent to the deep buried layer on the side of the deep groove, and the drain region and the source region are located on the same side of the deep groove, wherein the source region and the drain region are located on the same side Configure for the context. [Embodiment] In general, a basic memory unit of a dynamic random access memory (DRAM) is composed of a metal half field effect transistor and a capacitor. In DRAM, a memory array is composed of a plurality of basic memory units, and is controlled by a corresponding word line (Word Line) and a bit line (Bit Line). Although various other elements are also included in the dynamic random access memory, other elements are not shown and described herein for the convenience of description and description. Please refer to FIG. 1 , which is a schematic cross-sectional view of a dynamic random access memory having a thin transistor structure of 200931598 according to a preferred embodiment of the present invention. In the present embodiment, in order to simplify the description, only four transistor structures in which one bit line is connected to each other are taken as an example for explanation. The DRAM includes a plurality of thin transistors 210, each of which includes a gate region 211, a drain region 212, and a source region 213. In the present embodiment, the gate region 211 is a recessed gate structure and includes a gate oxide layer 215 between the substrate and the substrate 20. The drain region 212 and the source region 213 are located at the same β side of the gate region 211 and the source region 213 is perpendicular to the drain region 212, wherein the source region 213 is located in the large tilt implant region 214. In this embodiment, the dynamic random access memory is formed in the active region 21 of the substrate 2, wherein the active region 21 includes a deep buried connection region 22, and the deep buried connection region 22 is located in the active region 21. And deeper below the surface of the substrate 20. The drain regions 212 of each of the transistors 210 are located in the deep buried connection regions 22 and are connected together via phase contacts. The deep buried connection region 22 is located below the germanium gate region 211 and is a drain region shared by each of the transistors 210, and serves as a common bit line contact window (BC) for use on the same bit line. The transistor 210 shares a bit line 230. This saves a lot of space in the bit line contact window (BC) to reduce the area of the dynamic random access memory. Referring to FIG. 2, a cross-sectional view showing a deep buried layer connection region of a dynamic random access memory having a thin transistor structure in a preferred embodiment of the present invention is shown. A substrate 20 is provided to form an active region 21 in the substrate 20. In the present embodiment, the substrate 2G may be a P-base material or an N-type stone substrate, and the material thereof may be a material commonly used in semiconductor manufacturing technology, but is not limited thereto. The active region 21 is then doped, and dopants are implanted in the active region 21 to form a deep buried junction region 22 in the active region 21 and deeper below the surface of the substrate 20. In the present embodiment, when the substrate 2 is a P-based substrate, the ruthenium (4) is an N-type dopant, and the # substrate (10) is a ruthenium-based substrate. Referring to Figure 3, there is shown a cross-sectional view of a dynamic random access memory of a thin transistor structure in the form of a large dip implant region in accordance with a preferred embodiment of the present invention. A photoresist layer is deposited on the surface of the substrate 20, and a lithography process is performed by the photomask to transfer the pattern of the large dip implant region on the photomask to the photoresist to form a patterned photoresist layer 2〇1. Then, the active area 21 is subjected to a large dip implant (Halo Implant), and in the active area 21, a large dip planting area is formed under the surface of the substrate 2, and a large dip angle planting area 23 is used to suppress the source and The junctional breakdown effect occurs when the vacant depletion region is short-circuited by the bias of the gate and the source/drain bias. Referring to Figure 4, there is shown a cross-sectional view of a source region of a dynamic random access memory having a thin transistor structure in accordance with a preferred embodiment of the present invention. The patterned photoresist layer 2〇1 is removed, and a lithography process is performed to form another patterned photoresist layer 202 on the substrate 20 for defining a source pattern on the substrate 20, followed by an ion implantation process. The source region 213 is formed in the large dip implant region 23. In this embodiment, an N-type dopant, 200931598 such as phosphorus or a quenched ion, is implanted to form an N-channel. • Referring to Figure 5, there is shown a cross-sectional view of a dynamic random access memory having a thin plastic transistor structure forming a recessed gate in accordance with a preferred embodiment of the present invention. The patterned photoresist layer 202 is removed, and a lithography process is performed to form a patterned photoresist layer 203 on the substrate 20. A recessed gate pattern is defined on the active region 21 of the substrate 20. The substrate 20 is etched to form a plurality of deep grooves 207 in the active region 21 of the substrate 20, and the gate region 211 of the gate electrode is completed as a subsequent process, wherein the deep etch 207 is deeply buried. The layer is connected to the area 22. Therefore, each of the transistors is formed in the deep buried connection region 22 and adjacent to the side of the deep trench 207 to form a drain region 212, and a large dip implant region 214 is formed around the source region 213. The drain region 212 is vertically below the drain region 213, and the drain regions 212 of each of the transistors 210 are connected to each other via the deep buried connection region 22. Referring to Fig. 6, there is shown a cross-sectional view of a transistor formed by a dynamic random access memory having a thin transistor structure in Fig. 5. In the present embodiment, a screen oxide is deposited by vapor deposition as a subsequent ion implantation doping process to prevent channeling effects of ions on a specific lattice plane in a single crystal germanium substrate. . Then, ion implantation is performed, and a transistor channel 208 is formed in a region between the source region 213 and the drain region 212 of the active region 21 adjacent to the side of the deep groove 207 for adjusting the critical value of the embedded gate transistor. Voltage value (Vth). A heat treatment process, such as rapid annealing (RTA), is performed to ionize the ion channel of the substrate 20 exposed to the deep recess 207. 200931598 • (activate)' then remove the shield. Then, a general process is used in the deep trench. In the 2G7, a gate f-pole is formed, and a source electrode is formed on the surface of the source region 213. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; A schematic cross-sectional view of a dynamic random access memory having a thin transistor junction. Figure 2 is a cross-sectional view showing a deep random interconnect region formed by a dynamic random access memory having a thin transistor structure in a preferred embodiment of the present invention. © Fig. 3 is a cross-sectional view showing the dynamic random access memory having a thin transistor structure in Fig. 2 after forming a large dip implanting area. Fig. 4 is a cross-sectional view showing the source region of the dynamic random access memory having a thin transistor structure in Fig. 3. Fig. 5 is a cross-sectional view showing the formation of a recessed gate by a dynamic random access memory having a thin transistor structure in Fig. 4. Fig. 6 is a cross-sectional view showing the formation of a transistor channel by a dynamic random access memory having a thin transistor structure in Fig. 5. 11
200931598 【主要元件符號說明】 20 :基材 22 :深埋層連接區 201〜203 ··圖案化光阻層 208 :電晶體通道 211 :閘極區 213 :源極區 215 :閘極氧化層 ❹ 21 :主動區 23 :大傾角佈植區 207 :深凹槽 210 :電晶體 212 .没極區 214 :大傾角佈植區 230 :位元線 12200931598 [Description of main component symbols] 20: Substrate 22: Deep buried connection region 201 to 203 · Patterned photoresist layer 208: Transistor channel 211: Gate region 213: Source region 215: Gate oxide layer ❹ 21: active zone 23: large dip planting zone 207: deep groove 210: transistor 212. non-polar zone 214: large dip planting zone 230: bit line 12