200929328 九、發明說明： 相關申請案之對照參考資料 主張在2007年12月28日及2008年5月28日所分別 提出之韓國專利申請案第10-2007-0140859及10-2008-49895 號之優先權，將其全文倂入以供參考。 【發明所屬之技術領域】 本發明係有關於一種用以使用一間隔物圖案化技術 (SPT)製造一半導體元件之方法。 〇 【先前技術】 當增加半導體元件之整合度時，減少構成電路之圖案 的尺寸及間距。爲了在該半導體元件中形成一精細圖案， 已提出各種製造設備及製程方法。 光微影製程（亦稱爲光學微影）係一用於微製造以選擇 性地移除一薄膜之部分（或一基板之本體）的製程。它使用 光以將一幾何圖案從一光罩轉移至在該基板上之感光化學 物（光阻（photo-resist或簡稱"resist"))。依據瑞立方程式， ® 在一半導體元件中之一精細圖案的尺寸與在該光微影製程 中所使用之光的波長成正比及與在此一製程中所使用之透 鏡的尺寸成反比。結果，減少在該曝光製程中所使用之光 的波長或增加該透鏡之尺寸’以便獲得一精細圖案。然而’ 這些方法需要新的製造設備之開發，因而在設備管理上造 成困難；以及因此，增加製造成本。 爲了克服上述問題，已提出藉由使用傳統設備（不是新 的製造設備）以形成高度整合之精細圖案的其它方法。一種 200929328 方法係一雙重圖案化技術’它實施一以不同罩幕而圖案化 一光阻薄膜兩次以印刷電路圖案之曝光製程，以及另一種 方法係一使用間隔物做爲一蝕刻罩幕以獲得一精細圖案之 間隔物圖案化技術（SPT)。以下，將詳細描述該SPT。 第la至le圖係描述一傳統半導體元件之一 SPT(特別 是一用以形成一快閃記憶體元件之一控制閘極的方法）的 剖面圖。通常’該快閃記憶體元件包括一連接至複數個（1 6 或32個）控制閘極之單元串（cell string)及一用以連接位於 〇 該單元串之兩端的一源極選擇線（SSL)及一汲極選擇線 (DSL)之切換電晶體。 參考第la圖，在一半導體基板100上方形成一蝕刻目 標層110，以及在該蝕刻目標層110上方形成一犧牲膜 120。該蝕刻目標層110具有一種包括一多晶矽110a及一 氮化膜110b之沉積結構。該犧牲膜120a包括一四乙基正 矽酸鹽（TEOS)氧化膜。該犧牲膜120a之沉積厚度決定一在 該SPT中所使用之間隔物的高度。 ® 在該犧牲膜120a上方形成一硬罩幕層160、一底部抗 反射塗佈（B ARC)膜170及一第一光阻膜。然而，當實施一 曝光製程時，因在一光阻膜與在該光阻膜之底部所形成之 硬罩幕間之折射率的差異，而很難形成一在一罩幕中所界 定之第一精細光阻圖案。結果’使用該B ARC膜170 ’以防 止因該光阻膜與該硬罩幕間之折射率的差異所反射之光毀 損該光阻膜180。 通常，在一半導體微影製程中已使用一抗反射膜做爲 200929328 一用以穩定地形成一精細電路之薄吸光光阻材料層。在該 抗反射膜中，需要接觸界面及光特性與在一傳統製程中所 使用之一具有高解析度之光阻材料相配。該抗反射膜在一 對應波長範圍內調整一基板反射率，以獲得一不具有駐波 (standing wave)或切口（notching)之光阻圖案。並且，該抗 反射膜改善臨界尺寸（CD)均勻性及該光阻圖案與該基板之 黏著性。結果，該抗反射膜在一 DUV製程中扮演一重要角 色。該抗反射膜包括一在該光阻膜上所形成之頂部抗反射 © 塗佈（TARC)膜及一在該光阻膜之底部所形成之BARC膜。 該B ARC膜已廣泛地用以獲得一精細電路圖案。 參考第la圖，以該第一光阻圖案180做爲一罩幕蝕刻 該BARC膜170及該硬罩幕層160。使用該圖案化硬罩幕層 160來蝕刻該犧牲膜120a，以形成一犧牲圖案120。在形成 該犧牲圖案120後，移除該第一光阻圖案180、該抗反射膜 170及該硬罩幕層160。 參考第lb圖，在形成的結構（包括該犧牲圖案120)上 W 方形成一間隔物材料層。實施蝕刻製程，以在該犧牲圖案 1 20之側壁上形成一間隔物1 30。該間隔物1 30包括一多晶 矽及界定該控制閘極。 參考第lc圖，實施一濕式蝕刻製程，以移除該犧牲圖 案120’以便只保留該間隔物no。 參考Id圖’在一周邊區域中（不是在具有該半導體基 板1 00中所形成之複數控制閘極的中間區域中）形成一用以 界定一切換電晶體之閘極的第二光阻圖案140。 200929328 在該周邊區域中連接至該SSL及DSL的該切換電晶體 通常係配置在該單元串之兩端。在該曝光製程中，該切換 電晶體而不是在該中間區域中所形成之控制閘極可能具有 缺陷聚焦（defective focus)。當該周邊區域之失焦變得更厳 重時，聚焦深度（D OF)之製造邊限係不足的。並且，用以連 接該等選擇線SSL及DSL之切換電晶體係有關於一通道之 導通，以致於在位置之CD及圖案之尺寸方面需要有準確 控制。再者，該切換電晶體及該等選擇線之尺寸（寬度）大 © 於在該單元串中所包括之控制閘極的尺寸，以致於很難使 用該間隔物130形成一精細圖案。結果，在該周邊區域中 需要一額外第二光阻圖案140。 參考第le圖，使用該間隔物130及該第二光阻圖案140 做爲一罩幕來蝕刻該蝕刻目標層110,以形成用以界定複數 個控制閘極及在該單元串之兩端所配置之切換電晶體的閘 極之蝕刻目標圖案155a及155b。 形成一第三光阻圖案（未顯示），以暴露形成有該等蝕 ® 刻目標圖案155a及155b之該半導體基板的外邊緣。該第 三光阻圖案（未顯示）係一用以分割在該間隔物材料層之沉 積中所產生之一線端區域的間隔物部分之切割罩幕。使用 該第三光阻圖案（未顯示）做爲一罩幕移除在該線端上所配 置之蝕刻目標圖案155a及155b之一部分，以分割每一條 線，以及移除該第三光阻圖案（未顯示）。 在該SPT中，當形成具有一用以界定該切換電晶體之 閘極的墊型之光阻圖案140時，在形成該光阻圖案140前， 200929328 形成一 BARC膜，藉以防止該光阻圖案140受毀損。然而， 因先前所形成之間隔物130而不能形成該BARC膜。如第 Id圖所示，當在形成該間隔物130時而不能形成該BARC 膜時，該光阻圖案140可能具有一缺陷輪廓及其它缺陷。 雖然當在形成該間隔物130時沉積該抗反射膜時，該 抗反射膜可以沉積成在不具有間隔物130之周邊區域中具 有一既定厚度，但是該抗反射膜沒有形成於該等間隔物1 3 0 間之精細區域，而是沉積成具有大的厚度。在此情況中， 〇 該抗反射膜係沉積用以改善該光阻圖案140之輪廓及CD 均勻特性。然而，當在形成具有墊型之光阻圖案140後， 蝕刻該蝕刻目標層1 1 〇時，需要該方法包括使用該光阻圖 案140做爲一罩幕以移除該抗反射膜。又，需要增加該光 阻圖案140之厚度，以致於不可能確保一製造邊限。 當以一包括CF<爲基礎之蝕刻氣體移除該抗反射膜 時，侵蝕該間隔物130而減少它的高度。結果，在蝕刻該 蝕刻目標層110中蝕刻選擇性係不足的。 ® 如以上所述’在用以製造一半導體元件之傳統方法 中’很難在具有墊型之光阻圖案140的形成中施加一抗反 射膜，此導致因光之反射所造成之切口、在該周邊區域中 所形成之光阻圖案的缺陷、在圖案間之窄區塊中的渣垢及 因與該基板之黏著性的降低所造成之圖案拔起。 【發明內容】 本發明之各種實施例係有關於提供一種用以製造一半 導體元件之方法，該方法包括藉由以一單元罩幕製程在形 200929328 成一蝕刻目標圖案前施加一抗反射膜來形成一用於墊之圖 案，以改善該用於墊之圖案的輪廓及CD均勻性及防止光 阻圖案之渣垢及圖案拔起，藉以改善該元件之特性。 依據本發明之一實施例，一種用以製造一半導體元件 之方法包括：形成一第一罩幕圖案於一蝕刻目標層上方； 形成一第二罩幕圖案於該蝕刻目標層上方；形成間隔物於 該第一罩幕圖案及該第二罩幕圖案之側壁上；以及以一已 移除該第二罩幕圖案之蝕刻罩幕來蝕刻該蝕刻目標層。在 〇 此，該第二罩幕圖案之材料及尺寸不同於該第一罩幕圖案 之材料及尺寸。 最好，使用該第一罩幕圖案及在該第一罩幕圖案之側 壁上所形成之間隔物做爲用以形成一切換電晶體之一閘極 圖案的該蝕刻罩幕，其中該切換電晶體連接一源極選擇線 及一汲極選擇線至一單元串之兩端。並且，使用在該第二 罩幕圖案之側壁上所形成之間隔物做爲用以形成在該單元 串中之複數個控制閘極圖案的該蝕刻罩幕。 . 依據本發明之一實施例，一種用以製造一半導體元件 之方法包括：連續形成一用以形成一切換電晶體之一聞極 圖案的粗罩幕圖案及一用以形成在一單元串中之一控制閘 案的細罩幕圖案；以及形成間隔物於該粗罩幕圖案及 該細罩幕圖案之側壁上，以實施—STI製程。 依據本發明之一實施例，一種用以製造一半導體元# &力法包栝：形成一蝕刻目標層於一半導體基板上方；形 $ —楚圖案於在該半導體基板之邊緣上所配置之該蝕刻目 -10- 200929328 標層上；形成一平坦化犧牲膜於該形成的結構（包括該墊圖 案）上方；蝕刻該犧牲膜，以形成一犧牲圖案，而不蝕刻該 墊圖案；形成間隔物於該犧牲圖案及該墊圖案上；移除該 犧牲圖案，以保留該等間隔物；以及以該等間隔物及具有 該等間隔物之該墊圖案做爲一罩幕來蝕刻該蝕刻目標層。 【實施方式】 第2a至2g圖係描述一用以依據本發明之一實施例製 造一半導體元件之方法的剖面圖。在該實施例中，該半導 © 體元件包括一連接至複數個控制閘極之單元串及一用以在 該單元串之兩端連接一源極選擇線（SSL)及一汲極選擇線 (DSL)之切換電晶體。 參考第2a圖，在一半導體基板200上方形成一蝕刻目 標層210。在該蝕刻目標層210上方形成一多晶矽層220a 及一第一 BARC膜250a。在該第一BARC膜25 0a上方形成 —界定一用於墊之圖案的第一光阻圖案260a。該蝕刻目標 層210具有一種包括一多晶矽210a及一氮化膜210b之沉 ®積結構。 參考第2b圖，以該第一光阻圖案2 60a做爲一罩幕來 蝕刻該多晶矽層220a，以形成一用於墊之圖案220，其中 該圖案220界定用以連接SSL或DSL之該切換電晶體的閘 極。經由一隨後間隔物形成製程，在該圖案220之側壁上 形成一間隔物。結果，該圖案220係形成比該切換電晶體 之閘極小（有該間隔物之厚度）。 在形成該第一 BARC膜250a後，實施一曝光製程，以 200929328 防止該第一光阻圖案2 60a之缺陷或切口。亦即，在一蝕刻 目標層上方形成一 B ARC膜後，形成一光阻圖案，以減少 該蝕刻目標層之反射能力，藉以防止該用於墊之圖案的缺 陷及該光阻圖案之渣垢及拔起。 參考第2c圖，實施一化學機械硏磨（CMP)製程，以平 坦化一在該圖案220及該蝕刻目標層2 1 0上方所形成之犧 牲膜230。 該犧牲膜230包括一 TEOS膜。並且，因爲該犧牲膜 〇 230在一 SPT製程中決定該間隔物之高度，所以該犧牲膜 230係形成具有超過一既定高度。當該犧牲膜230係形成具 有一小的高度，很難經由隨後製程形成具有期望高度及厚 度之間隔物。例如：可一次以約30nm之厚度沉積一在一罩 幕圖案之側面上所形成之間隔物。然而，當該罩幕圖案不 高於30nm時，該間隔物係形成具有較薄厚度。 當該犧牲膜23 0係沉積成具有一既定厚度時，因該圖 案220而產生一階差。該階差在一隨後製程中可能造成失 ® 焦，以使在一單元串中之複數個精細控制閘極圖案變差。 結果，實施該CMP製程，以移除該階差。 在該平坦化犧牲膜230上方形成一硬罩幕240及一第 二抗反射膜250b。該硬罩幕240包括一多晶矽，因爲它具 有不足的蝕刻選擇性而以該光阻圖案蝕刻位於底部之犧牲 膜 230。 在該第二抗反射膜2 5 0b上方形成一用以界定一字元線 之第二光阻圖案260b。 -12- 200929328 該第二光阻圖案260b係形成具有一線/間隔型態。線： 間隔之比率係1 : 3。 參考第2d圖，以該第二光阻圖案2 6 0b做爲一罩幕以 蝕刻該第二抗反射膜250b及該硬罩幕240。 以該第二光阻圖案260b、該第二抗反射膜250b及該硬 罩幕240做爲一罩幕以蝕刻該底部犧牲膜230。 不蝕刻而是保留該圖案220，因爲該犧牲膜230與該 TEOS膜及該圖案220具有一蝕刻選擇性差異，其中該圖案 〇 220係一多晶矽。 如第2c及2d圖所示，當藉由該曝光製程形成該第二 光阻圖案260b時，該第二抗反射膜250b防止因該硬罩幕 240之折射率差異所可能產生之缺陷圖案。 . 移除該第二光阻圖案260、該第二抗反射膜250及該硬 罩幕240。 參考第2e圖，在該形成的結構（包括一犧牲圖案230a 及該圖案220)上方沉積一爲間隔物形成材料之多晶矽層。 ❹ ... 實施—回蝕刻製程，直到暴露該犧牲圖案230a爲止， 以在該犧牲圖案230a及該圖案220之側壁上形成一間隔物 270 〇 該間隔物270係形成於該圖案220之側壁上，以增加 該圖案220之CD，以便可以形成一大於該圖案220之閘極 圖案。 參考第2f圖，移除該犧牲圖案2 3 0a，以便可以保留用 以在該單元串中形成複數個控制閘極圖案之間隔物27〇。 -13- 200929328 該犧牲圖案230a係藉由一使用HF之濕式鈾刻法來移 除。由於在該HF溶液中之抗性而沒有移除做爲下面材料之 氮化膜210b。亦沒有移除具有相同於該間隔物270之蝕刻 選擇性的圖案220。 參考第2g圖，以該間隔物270及側壁上形成有該間物 270之圖案220做爲一罩幕來蝕刻該蝕刻目標層210。連續 蝕刻該氮化膜210b及該多晶矽210a。 用以做爲一罩幕之圖案2 20包括一多晶矽，該多晶矽 © 相較於用以做爲一罩幕之其它材料改善蝕刻均勻性，因爲 該圖案220會蝕刻該相同下面材料。 移除該間隔物270及該圖案220,以形成蝕刻目標圖案 215a及215b’其中該等蝕刻目標圖案215a及215b界定複 數個控制閘極圖案及用以連接該SSL或DSL之切換電晶體 的閘極。 形成一暴露具有該等蝕刻目標圖案215a及215b之該 半導體基板200的外邊緣之第三光阻圖案（未顯示）。該第三 ® 光阻圖案（未顯示）係一用以分割在該間隔物材料層之沉積 中所產生之一線端區域上所配置之一間隔物部分的切割罩 幕。 •ΤΪΤ*· 以該第二光阻圖案（未顯不）做爲一罩幕移除在該線端 上所配置之該蝕刻目標圖案2 1 5之一部分，以分割每一條 線，以及移除該第二光阻圖案（未顯示）》 相較於該傳統方法，在本發明之實施例中先形成一多 晶矽膜（該多晶矽膜係一用以形成一粗閘極圖案之蝕刻罩 -14- 200929328 幕）及形成一用以形成一細閘極圖案之間隔物，同時先形成 —間隔物（該間隔物係一用以形成一細閘極圖案之蝕刻罩 幕）及形成一用以形成一粗閘極圖案之光阻圖案。藉由一雙 重曝光製程，可以在一半導體元件中形成具有不同尺寸之 閘極圖案，藉以減少該製程之複雜度。再者，在形成一 B ARC 膜後，實施每一曝光製程，藉以增加每一具有不同尺寸之 光阻圖案的形成之準確性。 如以上所述，在一用以依據本發明之一實施例製造一 © 半導體元件之方法中，在藉由一單元罩幕製程形成一蝕刻 目標圖案前，施加一抗反射膜，以形成一用於墊之圖案， 藉此改善該用於墊之圖案的輪廓與CD均勻性及防止光阻 圖案之渣垢及圖案拔起，以改善該元件之特性。 本發明之上述實施例係描述用而非限定用。各種替代 及均等物係可能的。本發明並非受沉積之型態、蝕刻硏磨 及在此所述之圖案化步驟所限制。本發明亦不侷限於半導 體元件之任何特定型態。例如：可以在動態隨機存取記憶 ® 體（DRAM)或非揮發性記憶體元件中實施本發明。其它添 加、刪減或修改對於本揭露而言係明顯易知的且意欲落在 所附申請專利範圍之範圍內。 【圖式簡單說明】 第la至le圖係描述一用以製造一半導體元件之傳統 方法的剖面圖。 第2a至2g圖係描述一用以依據本發明之一實施例製 造一半導體元件之方法的剖面圖。 -15- 200929328 【主要元件符號說明】 200 半導體基板 2 10 蝕刻目標層 220 圖案 220a 多晶砂層 230 犧牲膜 240 硬罩幕 25 0a 第一 BARC膜 25 0b 第二抗反射膜 260b 第二光阻圖案 270 間隔物200929328 IX. INSTRUCTIONS: The Korean Patent Application Nos. 10-2007-0140859 and 10-2008-49895, respectively, were filed on December 28, 2007 and May 28, 2008. Priority is given to the full text for reference. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method for fabricating a semiconductor component using a spacer patterning technique (SPT). 〇 [Prior Art] When the degree of integration of semiconductor elements is increased, the size and pitch of the patterns constituting the circuit are reduced. In order to form a fine pattern in the semiconductor element, various manufacturing apparatuses and process methods have been proposed. Photolithography (also known as optical lithography) is a process for microfabrication to selectively remove a portion of a film (or a body of a substrate). It uses light to transfer a geometric pattern from a reticle to a photochemical (photo-resist or "resist") on the substrate. According to the rui cube program, the size of a fine pattern in a semiconductor component is proportional to the wavelength of the light used in the photolithography process and inversely proportional to the size of the lens used in the process. As a result, the wavelength of the light used in the exposure process or the size of the lens is reduced to obtain a fine pattern. However, these methods require the development of new manufacturing equipment, which makes it difficult to manage equipment; and, therefore, increases manufacturing costs. In order to overcome the above problems, other methods of forming a highly integrated fine pattern by using a conventional device (not a new manufacturing device) have been proposed. A 200929328 method is a double patterning technique that implements an exposure process in which a photoresist film is patterned twice with different masks to print a circuit pattern, and another method uses a spacer as an etching mask. A fine pattern spacer patterning technique (SPT) is obtained. Hereinafter, the SPT will be described in detail. The first to third drawings depict a cross-sectional view of one of the conventional semiconductor elements, SPT (particularly a method for forming a gate for controlling a gate of a flash memory element). Typically, the flash memory component includes a cell string connected to a plurality of (16 or 32) control gates and a source select line for connecting to both ends of the cell string ( SSL) and a switching transistor (DSL) switching transistor. Referring to FIG. 1a, an etch target layer 110 is formed over a semiconductor substrate 100, and a sacrificial film 120 is formed over the etch target layer 110. The etch target layer 110 has a deposition structure including a polysilicon 110a and a nitride film 110b. The sacrificial film 120a includes a tetraethyl orthosilicate (TEOS) oxide film. The deposited thickness of the sacrificial film 120a determines the height of a spacer used in the SPT. A hard mask layer 160, a bottom anti-reflective coating (B ARC) film 170 and a first photoresist film are formed over the sacrificial film 120a. However, when an exposure process is performed, it is difficult to form a first one defined in a mask due to the difference in refractive index between a photoresist film and a hard mask formed at the bottom of the photoresist film. Fine photoresist pattern. As a result, the B ARC film 170 is used to prevent the light reflected by the difference in refractive index between the photoresist film and the hard mask from damaging the photoresist film 180. Generally, an anti-reflection film has been used in a semiconductor lithography process as a layer of thin light-absorbing photoresist material for stably forming a fine circuit. In the antireflection film, the contact interface and optical characteristics are required to match a photoresist material having high resolution used in a conventional process. The anti-reflection film adjusts a substrate reflectance in a corresponding wavelength range to obtain a resist pattern having no standing wave or notching. Further, the anti-reflection film improves the critical dimension (CD) uniformity and the adhesion of the photoresist pattern to the substrate. As a result, the antireflection film plays an important role in a DUV process. The anti-reflection film comprises a top anti-reflection coating (TARC) film formed on the photoresist film and a BARC film formed on the bottom of the photoresist film. The B ARC film has been widely used to obtain a fine circuit pattern. Referring to FIG. 1a, the BARC film 170 and the hard mask layer 160 are etched by the first photoresist pattern 180 as a mask. The sacrificial film 120a is etched using the patterned hard mask layer 160 to form a sacrificial pattern 120. After the sacrificial pattern 120 is formed, the first photoresist pattern 180, the anti-reflection film 170, and the hard mask layer 160 are removed. Referring to Figure lb, a spacer material layer is formed on the W side of the formed structure (including the sacrificial pattern 120). An etching process is performed to form a spacer 1 30 on the sidewall of the sacrificial pattern 120. The spacer 1 30 includes a polysilicon and defines the control gate. Referring to Figure lc, a wet etch process is performed to remove the sacrificial pattern 120' to retain only the spacer no. Referring to the Id diagram, a second photoresist pattern 140 for defining a gate of a switching transistor is formed in a peripheral region (not in an intermediate region having a plurality of control gates formed in the semiconductor substrate 100) . 200929328 The switching transistor connected to the SSL and DSL in the peripheral area is usually disposed at both ends of the cell string. In the exposure process, the switching transistor, rather than the control gate formed in the intermediate region, may have a defective focus. When the out-of-focus of the peripheral region becomes more severe, the manufacturing margin of the depth of focus (D OF) is insufficient. Moreover, the switching cell system for connecting the select lines SSL and DSL is related to the conduction of a channel such that accurate control of the size of the CD and the size of the pattern is required. Furthermore, the size and width of the switching transistor and the select lines are large © the size of the control gate included in the cell string, so that it is difficult to form a fine pattern using the spacer 130. As a result, an additional second photoresist pattern 140 is required in the peripheral region. Referring to FIG. 3, the spacer 130 and the second photoresist pattern 140 are used as a mask to etch the etch target layer 110 to form a plurality of control gates and at both ends of the string. The etch target patterns 155a and 155b of the gate of the switching transistor are arranged. A third photoresist pattern (not shown) is formed to expose the outer edges of the semiconductor substrate on which the etch target patterns 155a and 155b are formed. The third photoresist pattern (not shown) is a cut mask for dividing a spacer portion of a line end region which is formed in the deposition of the spacer material layer. Using the third photoresist pattern (not shown) as a mask to remove a portion of the etch target patterns 155a and 155b disposed on the line end to divide each line and remove the third photoresist pattern (not shown). In the SPT, when a pad pattern 140 having a pad for defining the gate of the switching transistor is formed, a BARC film is formed in 200929328 before the photoresist pattern 140 is formed, thereby preventing the photoresist pattern from being formed. 140 was damaged. However, the BARC film cannot be formed due to the spacer 130 previously formed. As shown in Fig. 1d, when the BARC film cannot be formed when the spacer 130 is formed, the photoresist pattern 140 may have a defect profile and other defects. Although the anti-reflection film may be deposited to have a predetermined thickness in a peripheral region having no spacer 130 when the spacer 130 is formed, the anti-reflection film is not formed on the spacer A fine area of 1 30 is deposited to have a large thickness. In this case, the anti-reflective film is deposited to improve the profile and CD uniformity of the photoresist pattern 140. However, when etching the etch target layer 1 1 后 after forming the photoresist pattern 140 having the pad type, the method is required to include using the photoresist pattern 140 as a mask to remove the anti-reflection film. Also, it is necessary to increase the thickness of the photoresist pattern 140, so that it is impossible to ensure a manufacturing margin. When the anti-reflective film is removed by an etching gas including CF<, the spacer 130 is eroded to reduce its height. As a result, the etching selectivity is insufficient in etching the etching target layer 110. ® As described above, 'in the conventional method for fabricating a semiconductor device, it is difficult to apply an anti-reflection film in the formation of the photoresist pattern 140 having a pad type, which causes a slit due to reflection of light, The pattern of the photoresist pattern formed in the peripheral region, the slag in the narrow block between the patterns, and the pattern due to the decrease in adhesion to the substrate are pulled up. SUMMARY OF THE INVENTION Various embodiments of the present invention are directed to providing a method for fabricating a semiconductor device, the method comprising forming an anti-reflective film by applying a resist film to a pattern of 200929328 prior to forming an etch target pattern by a unit mask process. A pattern for the pad to improve the profile and CD uniformity of the pattern for the pad and to prevent the slag and pattern of the photoresist pattern from being pulled up, thereby improving the characteristics of the element. According to an embodiment of the invention, a method for fabricating a semiconductor device includes: forming a first mask pattern over an etch target layer; forming a second mask pattern over the etch target layer; forming a spacer The etch target layer is etched on the sidewalls of the first mask pattern and the second mask pattern; and an etch mask having the second mask pattern removed. In this case, the material and size of the second mask pattern are different from the material and size of the first mask pattern. Preferably, the first mask pattern and the spacer formed on the sidewall of the first mask pattern are used as the etching mask for forming a gate pattern of a switching transistor, wherein the switching The crystal connects a source select line and a drain select line to both ends of a string. Also, a spacer formed on the sidewall of the second mask pattern is used as the etching mask for forming a plurality of control gate patterns in the cell string. According to an embodiment of the invention, a method for fabricating a semiconductor device includes: continuously forming a rough mask pattern for forming a gate pattern of a switching transistor and forming a pattern in a cell string. One of the fine mask patterns for controlling the gate; and the spacers are formed on the sidewalls of the coarse mask pattern and the thin mask pattern to perform the STI process. According to an embodiment of the present invention, a method for fabricating a semiconductor element is: forming an etch target layer over a semiconductor substrate; and forming a pattern on the edge of the semiconductor substrate Forming a planarization sacrificial film over the formed structure (including the pad pattern); etching the sacrificial film to form a sacrificial pattern without etching the pad pattern; forming a spacer On the sacrificial pattern and the pad pattern; removing the sacrificial pattern to retain the spacers; and etching the etch target by using the spacers and the pad pattern having the spacers as a mask Floor. [Embodiment] Figs. 2a to 2g illustrate a cross-sectional view of a method for fabricating a semiconductor device in accordance with an embodiment of the present invention. In this embodiment, the semiconductor device component includes a cell string connected to the plurality of control gates and a source select line (SSL) and a drain select line connected to both ends of the cell string. (DSL) switching transistor. Referring to Fig. 2a, an etch target layer 210 is formed over a semiconductor substrate 200. A polysilicon layer 220a and a first BARC film 250a are formed over the etch target layer 210. A first photoresist pattern 260a defining a pattern for the pad is formed over the first BARC film 25a. The etch target layer 210 has a sink structure including a polysilicon 210a and a nitride film 210b. Referring to FIG. 2b, the polysilicon layer 220a is etched by using the first photoresist pattern 2 60a as a mask to form a pattern 220 for the pad, wherein the pattern 220 defines the switching for connecting SSL or DSL. The gate of the transistor. A spacer is formed on the sidewall of the pattern 220 via a subsequent spacer formation process. As a result, the pattern 220 is formed to be smaller than the gate of the switching transistor (having the thickness of the spacer). After the first BARC film 250a is formed, an exposure process is performed to prevent defects or slits of the first photoresist pattern 2 60a from 200929328. That is, after forming a B ARC film over an etch target layer, a photoresist pattern is formed to reduce the reflective capability of the etch target layer, thereby preventing the defect of the pattern for the pad and the slag of the photoresist pattern. And pulled up. Referring to Figure 2c, a chemical mechanical honing (CMP) process is performed to planarize a sacrificial film 230 formed over the pattern 220 and the etch target layer 210. The sacrificial film 230 includes a TEOS film. Also, since the sacrificial film 〇 230 determines the height of the spacer in an SPT process, the sacrificial film 230 is formed to have more than a predetermined height. When the sacrificial film 230 is formed to have a small height, it is difficult to form a spacer having a desired height and thickness via a subsequent process. For example, a spacer formed on the side of a mask pattern can be deposited at a thickness of about 30 nm at a time. However, when the mask pattern is not higher than 30 nm, the spacer is formed to have a thin thickness. When the sacrificial film 230 is deposited to have a predetermined thickness, a step difference is caused by the pattern 220. This step may cause a loss of focus in a subsequent process to degrade the plurality of fine control gate patterns in a cell string. As a result, the CMP process is implemented to remove the step. A hard mask 240 and a second anti-reflection film 250b are formed over the planarization sacrificial film 230. The hard mask 240 includes a polysilicon because it has insufficient etch selectivity to etch the sacrificial film 230 at the bottom in the photoresist pattern. A second photoresist pattern 260b for defining a word line is formed over the second anti-reflection film 250b. -12- 200929328 The second photoresist pattern 260b is formed to have a line/space type. Line: The ratio of intervals is 1:3. Referring to Figure 2d, the second photoresist pattern 260b is used as a mask to etch the second anti-reflection film 250b and the hard mask 240. The second photoresist pattern 260b, the second anti-reflection film 250b and the hard mask 240 are used as a mask to etch the bottom sacrificial film 230. The pattern 220 is retained without etching because the sacrificial film 230 has an etch selectivity difference from the TEOS film and the pattern 220, wherein the pattern 〇 220 is a polysilicon. As shown in Figs. 2c and 2d, when the second photoresist pattern 260b is formed by the exposure process, the second anti-reflection film 250b prevents a defect pattern which may be generated due to a difference in refractive index of the hard mask 240. The second photoresist pattern 260, the second anti-reflection film 250, and the hard mask 240 are removed. Referring to Fig. 2e, a polysilicon layer as a spacer forming material is deposited over the formed structure (including a sacrificial pattern 230a and the pattern 220). ❹ ... the etch-back process is performed until the sacrificial pattern 230a is exposed to form a spacer 270 on the sidewalls of the sacrificial pattern 230a and the pattern 220. The spacer 270 is formed on the sidewall of the pattern 220. To increase the CD of the pattern 220 so that a gate pattern larger than the pattern 220 can be formed. Referring to Figure 2f, the sacrificial pattern 2 3 0a is removed so that spacers 27 for forming a plurality of control gate patterns in the cell string can be retained. -13- 200929328 The sacrificial pattern 230a is removed by a wet uranium engraving method using HF. The nitride film 210b which is the following material was not removed due to the resistance in the HF solution. Pattern 220 having the same etch selectivity as the spacer 270 is also not removed. Referring to Fig. 2g, the etch target layer 210 is etched by using the spacer 270 and the pattern 220 on the sidewall on which the spacer 270 is formed as a mask. The nitride film 210b and the polysilicon 210a are continuously etched. The pattern 2 20 used as a mask includes a polysilicon which improves etching uniformity compared to other materials used as a mask because the pattern 220 etches the same underlying material. The spacer 270 and the pattern 220 are removed to form etch target patterns 215a and 215b', wherein the etch target patterns 215a and 215b define a plurality of control gate patterns and gates for connecting the SSL or DSL switching transistors pole. A third photoresist pattern (not shown) exposing an outer edge of the semiconductor substrate 200 having the etch target patterns 215a and 215b is formed. The third photoresist pattern (not shown) is a cut mask for dividing a portion of the spacer disposed on one of the line end regions produced in the deposition of the spacer material layer. • ΤΪΤ*· removes one of the etch target patterns 2 1 5 disposed on the line end with the second photoresist pattern (not shown) as a mask to divide each line and remove The second photoresist pattern (not shown) is formed by forming a polysilicon film in the embodiment of the present invention (the polysilicon film is an etching mask 14 for forming a thick gate pattern). 200929328) and forming a spacer for forming a fine gate pattern, and simultaneously forming a spacer (the spacer is an etching mask for forming a fine gate pattern) and forming a pattern for forming The photoresist pattern of the thick gate pattern. By a double exposure process, gate patterns having different sizes can be formed in a semiconductor device, thereby reducing the complexity of the process. Further, after forming a B ARC film, each exposure process is performed to increase the accuracy of formation of each photoresist pattern having a different size. As described above, in a method for fabricating a semiconductor device according to an embodiment of the present invention, an anti-reflection film is applied to form an etch target pattern by a unit mask process to form a film. The pattern of the pad is used to improve the contour and CD uniformity of the pattern for the pad and to prevent the slag and pattern of the photoresist pattern from being pulled up to improve the characteristics of the element. The above-described embodiments of the present invention are described and not limited. Various alternatives and equalities are possible. The invention is not limited by the type of deposition, etch honing, and the patterning steps described herein. The invention is also not limited to any particular type of semiconductor component. For example, the invention can be implemented in a dynamic random access memory (DRAM) or non-volatile memory component. Other additions, deletions, or modifications are apparent to the disclosure and are intended to fall within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The first to third drawings illustrate a cross-sectional view of a conventional method for fabricating a semiconductor device. 2a through 2g are cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. -15- 200929328 [Description of main component symbols] 200 Semiconductor substrate 2 10 Etching target layer 220 Pattern 220a Polycrystalline sand layer 230 Sacrificial film 240 Hard mask 25 0a First BARC film 25 0b Second anti-reflection film 260b Second photoresist pattern 270 spacer
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