KR20110001718A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20110001718A
KR20110001718A KR1020090059379A KR20090059379A KR20110001718A KR 20110001718 A KR20110001718 A KR 20110001718A KR 1020090059379 A KR1020090059379 A KR 1020090059379A KR 20090059379 A KR20090059379 A KR 20090059379A KR 20110001718 A KR20110001718 A KR 20110001718A
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KR
South Korea
Prior art keywords
pattern
layer
forming
poly
photoresist pattern
Prior art date
Application number
KR1020090059379A
Other languages
Korean (ko)
Inventor
박사로한
이기령
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090059379A priority Critical patent/KR20110001718A/en
Publication of KR20110001718A publication Critical patent/KR20110001718A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70216—Mask projection systems
    • G03F7/70341—Details of immersion lithography aspects, e.g. exposure media or control of immersion liquid supply
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

A method of forming a semiconductor device according to an embodiment of the present invention includes forming a photoresist pattern on an etched layer, forming a spacer on sidewalls of the photoresist pattern, removing a photoresist pattern, a gap fill on the etched layer and the spacer Forming a poly layer, planarizing the gapfill poly layer to expose a top of the spacer to form a poly pattern, removing the exposed spacer layer, and etching the etched layer using the poly pattern as an etching mask It includes.

SPT, gap fill poly, overlay margin

Description

Method of forming a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

The present invention relates to a method of forming a semiconductor device, and more particularly, in the implementation of a pad layout in which interconnect areas are difficult to implement when applying a negative tone SPT method, an overlay margin can be increased during a manufacturing process. A method for forming a semiconductor device.

As semiconductor devices are highly integrated, the size and pitch of patterns for implementing circuits constituting semiconductor devices are gradually decreasing. Looking at the Rayleigh equation, the size of the fine pattern in the semiconductor device is proportional to the wavelength of light used in the exposure process and inversely proportional to the size of the lens. Therefore, a method of reducing the wavelength of light or increasing the size of the lens used in the exposure process has been mainly used for forming a fine pattern.

In addition, in-process photo processing technology refines the mask design to properly control the amount of light that passes through the mask, develop new photosensitizers, and develop scanners using high numerical aperture lenses. By overcoming efforts to develop modified masks, the technical limitations of semiconductor device manufacturing apparatuses have been overcome. However, due to limitations in exposure and resolution ability that proceed using current light sources (for example, KrF, ArF, etc.), it is difficult to form a width and an interval of a desired pattern. For example, until now, exposure techniques for manufacturing a pattern size of about 60 nm have been developed, but there are many difficulties in manufacturing a pattern size smaller than that.

Various studies have been conducted to form a photosensitive film pattern having a size and a gap of a fine pattern to overcome the limitation of the light source. One method is a double patterning technology (DPT) method in which a pattern is formed by performing two photographic processes. The DPT method uses a DE2T (Double Expose Etch Technology) method that exposes and etches a pattern having twice the period of the pattern period, and then exposes and etches a second pattern having the same double period between them, and a spacer. There is a SPT (Spacer Patterning Technology) method of forming a pattern. The DE2T method and the SPT method may be respectively formed by a process of negative tones and positive tones, respectively.

The negative tone DE2T method removes the pattern formed in the first mask process from the second mask process and forms a desired pattern. The positive tone DE2T method combines the pattern formed in the first mask process and the second mask process to form a desired pattern. How to form. However, the DE2T method, which achieves the desired pattern density by performing the second mask process and etching process after the first mask process and etching process, increases the complexity of the process by increasing the number of additional processes required to perform the second mask process and etching process. There is a disadvantage to increase. In addition, there is a possibility that alignment errors occur in the patterns obtained through the first mask process and the second mask process that are independent of each other, commonly referred to as overlay.

On the other hand, the SPT method is a self align method that can prevent the disadvantage of misalign because the mask process is performed only once for patterning the cell region. However, an additional mask process is required to separate the pattern portion of the mat edge region to form the pad pattern in the core and peripheral circuit regions, and the deposition uniformity of the spacer formation region and the spacer formation. CD uniformity due to the etching process is not easy, so CD uniformity is a problem.

1A to 1G are cross-sectional views illustrating a negative tone SPT method. Here, an example of forming a control gate of a flash memory will be described.

Referring to FIG. 1A, after forming an isolation layer defining an active region on a semiconductor substrate, a capping first silicon oxynitride layer is formed on an upper structure formed by depositing an ONO dielectric film / gate poly / tungsten silicide (WSi) or the like. (SiON) 110 is formed. The first TEOS 112 and the first poly 114 are deposited as a hard mask on the first silicon nitride oxide layer 110. Here, the height of the hard mask formed of the first poly 114 determines the height of the spacer, which is the core of the SPT process, as a partition pattern.

However, since the first poly 114 cannot be etched by the photoresist pattern, the first amorphous carbon 116 and the second silicon oxynitride film 118 are used as the hard mask for etching the first poly 114. Formed on top of poly 114. Subsequently, a bottom anti-reflective coating (BARC) layer 119 is formed on the second silicon nitride oxide layer 118.

The photoresist film is coated on the BARC 119, and the photoresist pattern 120 is formed through an exposure and development process on the photoresist using a mask in which a pattern having a pitch twice the desired pitch is defined. For example, when the etch bias is not considered, when the line is formed with a 40 nm CD, the space is formed with a CD of 120 nm. That is, the line / space ratio is 1: 3.

Referring to FIG. 1B, the BARC 119, the second silicon nitride oxide layer 118, the amorphous carbon 116, and the first poly 114 are sequentially etched using the photoresist pattern 120 as an etching mask. The poly pattern 114a is formed, and the photosensitive film pattern 120, the BARC 119, the second silicon nitride film 118, and the amorphous carbon 116 are removed. In this case, an upper portion of the first TEOS 112, which is a hard mask, is partially etched by the thickness of a spacer formed later. The reason for this etching is to match the height of the first poly pattern 114a and the thickness of the spacer to be formed of Tetra (Tetraethyl Orthosilicate). If the height of the first poly pattern 114a and the thickness of the spacer are not the same, the etching selectivity is changed due to the difference in the materials constituting the etching mask (barrier) during the etching process of the spacer, thereby changing the etching profile. Can be. To prevent this, the upper portion of the first TEOS 112, which is a hard mask, is etched. In addition, during the formation of the spacer 122, the film must be deposited with a spacer material at a temperature lower than the deposition temperature of the first poly pattern 114a and the lower hard mask first TEOS 112 to lift the film due to thermal stress. (film lifting) can be prevented.

Referring to FIG. 1C, a second TEOS 122 using a spacer material is deposited on the hard mask first TEOS 112 including the first poly pattern 114a. Here, since the deposition material used as the spacer has a great influence on the line width, the second TEOS 122 having excellent step coverage is used. A material that can be formed by atomic layer deposition (ALD) may be used.

1D and 1E, a gap fill hard mask second poly 124 is formed on the second TEOS 122 and an etch back process is performed on the second poly 124. Do this. At this time, the second poly 124 must be sufficiently deposited to have a uniform flat surface irrespective of the region where the fine first poly pattern 114a is formed to etch a predetermined depth so that the second TEOS 122, which is a spacer material, is exposed. In this case, the second poly pattern 124a may be formed as shown in FIG. 1E.

Referring to FIG. 1F, the second TEOS 122 is partially etched to expose the first poly pattern 114a, thereby forming a gap fill hard mask second poly pattern 124a formed between the second TEOS 122, which is a spacer material. A line pattern is formed together with the first poly pattern 114a. Here, a dry etch back and a wet strip method are applied as a method of etching the second TEOS 122.

Referring to FIG. 1G, by using the first poly pattern 114a and the second poly pattern 124a as an etching mask, the first TEOS pattern is etched by etching the first TEOS 112 and the second TEOS 122, which are spacers, respectively. 112a and a second TEOS pattern 122a are formed. Thereafter, the first silicon nitride oxide layer 110 is etched using the first TEOS pattern 112a and the second TEOS pattern 122a as an etch mask to form a fine pattern having a small pitch that cannot be formed by conventional exposure equipment. To form.

As described above, the SPT process using the material having the good gap fill characteristics described with reference to FIGS. 1A to 1G repeats the process of depositing and etching the hard mask layer several times and etching the lower insulating layer according to the hard mask pattern formed at that time. Since the process is performed, there is a disadvantage that the turn-around-time (TAT) is increased to increase the manufacturing cost. That is, as the manufacturing process of the semiconductor device including the fine pattern becomes longer, it is difficult to apply the above-described SPT process for mass production of the semiconductor device.

In order to overcome the above-described problem, the present invention provides a method of manufacturing a semiconductor device that can reduce the manufacturing cost of the semiconductor device by reducing the number of processes in the process of forming a fine pattern by applying the negative SPT method.

The present invention provides a method of forming a photoresist pattern on an etched layer, forming a spacer on sidewalls of the photoresist pattern, removing the photoresist pattern, forming a gapfill poly layer on the etched layer and the spacer, Forming a poly pattern by planarizing the gapfill poly layer to expose an upper portion of the spacer, removing the exposed spacer layer, and etching the etched layer using the poly pattern as an etch mask. Provided are a method of forming an element.

Preferably, forming a spacer on a sidewall of the photoresist pattern includes forming a spacer layer having a uniform thickness on the etched layer and the photoresist pattern, and etching the spacer layer to expose the photoresist pattern. do.

Preferably, the etching of the spacer layer may be performed by an etch back process.

Preferably, the forming of the poly pattern may be performed using one of an etch back process, a chemical mechanical polishing process, and a wet etching process.

Preferably, the method of forming the semiconductor device further comprises depositing an antireflection film between the etched layer and the photoresist pattern.

Preferably, the method of forming the semiconductor device further includes etching the exposed anti-reflection film using the photoresist pattern as an etching mask after the formation of the photoresist pattern.

Preferably, the anti-reflection film remaining under the photoresist pattern is removed together during the process of removing the photoresist pattern.

Preferably, the etched layer is characterized in that it comprises a TEOS film.

Preferably, the spacer film is characterized in that it comprises an oxide film.

Preferably, the method of forming the photosensitive film pattern is one of an immersion exposure process using ArF and an exposure process using ArF or KrF.

In the present invention, when the negative tone SPT method is applied, spacers are formed on sidewalls of the photoresist pattern instead of a hard mask pattern made of an insulating film, thereby depositing a conventional hard mask layer and patterning the hard mask layer through an exposure process. This can be greatly simplified, which reduces the turn-around-time (TAT).

In addition, the present invention can use a poly layer deposited through the same process as an etching mask, compared to the case of using an etching mask consisting of two poly layers deposited through different processes in the prior art of the hard mask layer or the etching layer There is an advantage of increasing the uniformity during etching.

In the present invention, a negative SPT process is simplified among the methods for forming a fine pattern included in a semiconductor device. Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A to 2I are cross-sectional views illustrating a manufacturing method of forming a fine circuit pattern through the SPT method according to the present invention.

Referring to FIG. 2A, a photosensitive film pattern 220 is formed on the etched layer 210 on which the fine pattern is to be formed. The hard mask layer 212 is deposited on the etched layer 210, and the anti-reflection film 219 is deposited on the hard mask layer 212. Here, the hard mask layer 212 includes a TEOS film. In addition, the photoresist pattern 220 may be formed by coating the photoresist on the antireflection layer 219 and then patterning the photoresist using one of an immersion exposure process using ArF and an exposure process using ArF or KrF. The line width of the photoresist pattern 220 is equal to the line width of a fine pattern to be formed later, and the spacing between the photoresist patterns 220 is equal to or more than twice the line width of the photoresist pattern 220.

As shown in FIG. 1A, when performing the conventional negative SPT process, the first poly 114, the first amorphous carbon 116, and the second silicon material are disposed between the first TEOS 112 and the lower anti-reflection film 119. Although a plurality of insulating layers or hard mask layers, such as the oxide film 118, are deposited, the present invention has a large difference from depositing the anti-reflection film 219 directly on the hard mask layer 212.

Referring to FIG. 2B, the hard mask layer 212 is exposed by removing the anti-reflection film 219 exposed between the photoresist patterns 220.

Referring to FIG. 2C, a spacer layer 222 having a predetermined thickness is deposited on the hard mask layer 212 and the photoresist pattern 220. In this case, the thickness of the spacer layer 222 becomes a gap between the fine patterns finally formed, and the spacer layer 222 may include an oxide layer.

Referring to FIG. 2D, the spacer layer 222 is etched to expose the upper portion of the photoresist pattern 220 and the hard mask layer 212 so that the spacer 222 is formed only on the sidewall of the photoresist pattern 220.

Referring to FIG. 2E, the exposed photoresist pattern 220 is removed so that only the spacers 222 remain on the hard mask layer 212. In addition, the anti-reflection film 219 remaining under the photoresist pattern 220 is also removed. That is, when the photoresist pattern 220 is removed, the spacers 222 formed on the sidewalls of the photoresist pattern 220 are not removed but have a shape of a pattern spaced apart by a predetermined interval, and a hard mask between the spacers 222. Layer 212 is exposed.

Referring to FIG. 2F, a poly layer 224 is deposited on the spacer 222. In this case, the poly layer 224 may be deposited without a void in the space between the spacers 222 using a material having excellent gap fill characteristics.

Referring to FIG. 2G, the poly layer 224 is planarized until the spacer 222 is exposed to form the poly pattern 226. In this case, in order to form the poly pattern 226, the poly layer 224 may be etched using one of an etch back process, a chemical mechanical polishing process, and a wet etching process.

Referring to FIG. 2H, a portion of the hard mask layer 212 is exposed by removing the spacers 222 exposed between the poly patterns 226.

In the conventional case, since the poly pattern is deposited through two different processes, even if the same material is used, the uniformity of the pattern is inferior, whereas the poly pattern 226 formed according to the manufacturing method according to the exemplary embodiment of the present invention is different from the conventional method. Otherwise, since the material is deposited through the same process, the uniformity is improved. The uniformity improvement of the poly pattern 226 may improve the uniformity of the fine pattern formed in the etched layer 210.

Referring to FIG. 2I, the exposed hard mask layer 212 is etched using the poly pattern 226 as an etch mask. In the subsequent process, the patterned hard mask layer 212 may be used as an etching mask to etch the lower etching layer 210 to form a fine pattern.

As described above, the present invention has the advantage of reducing the turn-around-time (TAT) by forming a spacer layer directly on the sidewall of the photoresist pattern when applying the negative tone SPT method. A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a photoresist pattern on an etched layer, forming a spacer layer on top of the etched layer and the photoresist pattern, and etching the spacer layer to expose an upper surface of the photoresist pattern. Removing the exposed photoresist pattern, forming a gap fill poly layer on the spacer layer, etching the gap fill poly layer to expose the upper surface of the spacer layer, forming a poly pattern, and removing the exposed spacer layer. And etching the etching target layer using the poly pattern as an etching mask.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A to 1G are cross-sectional views illustrating a negative tone SPT method.

2a to 2i are cross-sectional views showing a manufacturing method for forming a fine circuit pattern through the SPT method according to the present invention.

Claims (10)

Forming a photoresist pattern on the etched layer; Forming a spacer on sidewalls of the photoresist pattern; Removing the photoresist pattern; Forming a gapfill poly layer on the etched layer and the spacer; Planarizing the gapfill poly layer to form a poly pattern such that an upper portion of the spacer is exposed; Removing the exposed spacers; And Etching the etched layer using the poly pattern as an etching mask Method of forming a semiconductor device comprising a. The method of claim 1, Forming spacers on sidewalls of the photoresist pattern Forming a spacer layer having a uniform thickness on the etched layer and the photoresist pattern; And Etching the spacer layer to expose the photoresist pattern Method of forming a semiconductor device comprising a. The method of claim 2, Etching the spacer layer is performed by an etch back process. The method of claim 1, The forming of the poly pattern may be performed using any one of an etch back process, a chemical mechanical polishing process, and a wet etching process. The method of claim 1, And depositing an anti-reflection film between the etched layer and the photoresist pattern. The method of claim 5, After forming the photoresist pattern, using the photoresist pattern as an etching mask, etching the exposed anti-reflection film. The method of claim 6, And the anti-reflection film remaining under the photoresist pattern is removed together during the process of removing the photoresist pattern. The method of claim 1, The etching target layer comprises a TEOS film. The method of claim 1, And the spacer film comprises an oxide film. The method of claim 1, The method of forming a semiconductor device, characterized in that using the method of one of the liquid immersion exposure process using ArF and the exposure process using ArF or KrF.
KR1020090059379A 2009-06-30 2009-06-30 Method for manufacturing semiconductor device KR20110001718A (en)

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