KR100620173B1 - Method for forming gate pattern minutely in semiconductor device fabrication process - Google Patents

Method for forming gate pattern minutely in semiconductor device fabrication process Download PDF

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KR100620173B1
KR100620173B1 KR1020020086645A KR20020086645A KR100620173B1 KR 100620173 B1 KR100620173 B1 KR 100620173B1 KR 1020020086645 A KR1020020086645 A KR 1020020086645A KR 20020086645 A KR20020086645 A KR 20020086645A KR 100620173 B1 KR100620173 B1 KR 100620173B1
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gate
forming
fine pattern
semiconductor device
polysilicon
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KR1020020086645A
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Korean (ko)
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KR20040060116A (en
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박철수
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities

Abstract

본 발명은 반도체 소자 게이트 형성 방법에 관한 것으로, 즉, 본 발명은 고집적 반도체 소자의 미세 패턴 게이트 형성에 있어서, 종래 KrF를 이용하여 고집적도에서 요구되는 게이트 미세 패턴 형성을 위한 리소그라피 공정을 수행함으로써 제조 비용을 크게 절감시킬 수 있게 되는 이점이 있다.The present invention relates to a method for forming a semiconductor device gate, that is, the present invention is prepared by performing a lithography process for forming a gate fine pattern required at high integration using a conventional KrF in forming a fine pattern gate of a highly integrated semiconductor device There is an advantage that can significantly reduce the cost.

Description

게이트 미세 패턴 형성 방법{METHOD FOR FORMING GATE PATTERN MINUTELY IN SEMICONDUCTOR DEVICE FABRICATION PROCESS}METHOD FOR FORMING GATE PATTERN MINUTELY IN SEMICONDUCTOR DEVICE FABRICATION PROCESS}

도 1a 내지 도 1c는 본 발명의 실시 예에 따른 게이트 미세 패턴 형성방법을 도시한 공정 수순도,1A to 1C are process flowcharts illustrating a method of forming a gate fine pattern according to an exemplary embodiment of the present invention;

도 2는 상기 도 1의 공정 중 게이트 식각을 위한 하드 마스크 생성시의 세부 공정 단면도.FIG. 2 is a detailed cross-sectional view of the hard mask for gate etching during the process of FIG. 1. FIG.

본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 반도체 소자 제조시 게이트 미세 패턴 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a gate fine pattern in manufacturing a semiconductor device.

근래에 들어 반도체 소자의 집적도가 증가함에 따라 리소그라피 툴(Lithography tool) 또한 계속해서 변화되는 추세에 있다. In recent years, as the degree of integration of semiconductor devices increases, lithography tools continue to change.

그러나, 종래 리소그라피 소스는 디자인 룰(Design rule)의 감소에 따라 g-라인에서 I라인으로 또 Duv KrF에서 Duv ArF로 변화되므로써 툴을 구매하는 초기비용 뿐만아니라 공정 비용 또한 과도하게 증가되는 문제점이 있었다.However, the conventional lithography source has a problem that the process cost is excessively increased as well as the initial cost of purchasing the tool by changing from g-line to I-line and from Duv KrF to Duv ArF as the design rule decreases. .

따라서 상기 반도체 소자 집적도에 따른 Duv ArF대신 종래 KrF를 동일하게 사용하면서도 고 집적 반도체 소자 디자인 룰을 만족시키게 된다면 많은 비용을 절감할 수 있을 것으로 기대된다.Therefore, if the conventional KrF is used instead of the Duv ArF according to the semiconductor device integration level, and satisfies the high integrated semiconductor device design rule, it is expected that much cost can be saved.

따라서, 본 발명의 목적은 종래 디자인 룰에서 사용되는 KrF를 동일하게 사용하면서도 고집적도 반도체 소자에서 요구되는 미세 패턴의 게이트를 형성할 수 있도록 하는 반도체 소자 제조시 게이트 미세 패턴 형성 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for forming a gate fine pattern in the manufacture of a semiconductor device capable of forming a gate having a fine pattern required for a highly integrated semiconductor device while using the same KrF used in a conventional design rule.

상술한 목적을 달성하기 위한 본 발명은 반도체 소자 제조시 게이트 미세 패턴 형성방법에 있어서, (a)실리콘 기판에 게이트 절연막과 게이트 전극막을 순차적으로 적층시키는 단계와; (b)상기 게이트 전극용 감광막을 패터닝 수행하여 상기 게이트 전극막을 소정 깊이까지 건식 식각시키는 단계와; (c)게이트 길이 축소용 폴리실리콘을 오목한 형태의 요철 모양으로 증착시키는 단계와; (d)상기 요철 부위에 게이트 전극 형성용 하드 마스크 산화막을 증착시키는 단계와; (e)상기 폴리실리콘과 산화막의 높은 건식 식각 선택비를 이용하여 게이트 미세패턴을 형성시키는 단계;를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a gate fine pattern in the manufacture of a semiconductor device, comprising the steps of: (a) sequentially stacking a gate insulating film and a gate electrode film on a silicon substrate; (b) dry etching the gate electrode film to a predetermined depth by patterning the photoresist film for the gate electrode; (c) depositing polysilicon for reducing the gate length into a concave-convex shape; (d) depositing a hard mask oxide film for forming a gate electrode on the uneven portion; (e) forming a gate fine pattern using a high dry etching selectivity between the polysilicon and the oxide film.

이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시 예의 동작을 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.

도 1a 내지 도 1c는 본 발명의 실시 예에 따른 미세 패턴 형성 방법을 도시한 공정 수순도이다. 이하 상기 도 1a 내지 도 c를 참조하여 본 발명의 미세 패턴 형성방법을 상세히 설명한다. 1A to 1C are process flowcharts illustrating a method for forming a fine pattern according to an embodiment of the present invention. Hereinafter, a method of forming a fine pattern of the present invention will be described in detail with reference to FIGS. 1A to C.                     

먼저 도 1a에서와 같이 실리콘 기판(1)에 STI(Shallow Trench Isolation)(2)를 형성하고 그 상부에 게이트(Gate) 절연막(3)과 게이트 전극(4)을 순차적으로 적층 형성시킨다. 이어 게이트 전극용 감광막(5)을 패터닝(Patterning)하여 노출된 게이트 전극(4)을 미리 설정된 소정의 깊이까지 건식 식각시킨다.First, as shown in FIG. 1A, a shallow trench isolation (STI) 2 is formed on the silicon substrate 1, and a gate insulating film 3 and a gate electrode 4 are sequentially stacked on the silicon substrate 1. Subsequently, the gate electrode photoresist film 5 is patterned to dry-etch the exposed gate electrode 4 to a predetermined predetermined depth.

그리고 도 1b에서와 같이 게이트 전극용 감광막(5)을 제거하고, 게이트 길이를 줄이고자 하는 양의 절반 두께에 해당하는 게이트 길이 축소용 폴리실리콘(Poly silicon)(6)을 그 상부에 증착시킨다. 그런 후, 그 요철 부위에 재충진(Refilling) 가능하며 상기 폴리실리콘의 단차보다 1.5배 이상의 게이트 전극 형성용 하드마스크 산화막(7)을 증착시키고, CMP(Chemical Mechanical Polishing)를 수행하여 평탄화시킨다. 도 2는 상기 하드마스크 생성의 일 예를 도시한 도면으로, 상기 도 2에서 보여지는 바와 같이 실제로 0.15μm 배선은 KrF로 충분하나 0.09μm 배선은 ArF를 사용해야 한다. 그러나 본 발명에서는 상기한 도 1b에서와 같이 KrF배선을 그대로 사용할 수 있다.As shown in FIG. 1B, the gate electrode photoresist film 5 is removed and a gate length reduction polysilicon 6 corresponding to half the thickness to reduce the gate length is deposited thereon. Thereafter, the hard mask oxide film 7 for refilling the uneven portion and forming the gate electrode 7 or more than 1.5 times higher than the level of the polysilicon is deposited, and planarized by performing chemical mechanical polishing (CMP). FIG. 2 is a diagram illustrating an example of hard mask generation. As shown in FIG. 2, in fact, 0.15 μm wiring is sufficient as KrF, but 0.09 μm wiring should use ArF. However, in the present invention, as shown in FIG. 1B, the KrF wiring can be used as it is.

이어 도 1c에서와 같이 폴리실리콘(6)과 산화막(Oxide)의 높은 건식 식각 선택비(50:1 이상)를 이용하여 게이트 미세 패턴을 완성시키게 된다. Subsequently, as shown in FIG. 1C, the gate fine pattern is completed by using a high dry etching selectivity (50: 1 or more) of the polysilicon 6 and the oxide.

따라서 상기한 바와 같이 본 발명에서는 고집적 반도체 소자의 게이트 형성시 종래 KrF를 게이트 미세 패턴 공정을 수행함으로써, 제조 비용을 크게 절감시킬 수 있게 된다.Therefore, as described above, in the present invention, the gate fine pattern process is performed on the KrF when the gate of the highly integrated semiconductor device is formed, thereby greatly reducing the manufacturing cost.

한편 상술한 본 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명 의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.

이상에서 설명한 바와 같이, 본 발명은 고집적 반도체 소자의 미세 패턴 게이트 형성에 있어서, 종래 KrF를 이용하여 고집적도에서 요구되는 게이트 미세 패턴 형성을 위한 리소그라피 공정을 수행함으로써 제조 비용을 크게 절감시킬 수 있게 되는 이점이 있다.As described above, in the present invention, in the formation of a fine pattern gate of a highly integrated semiconductor device, a manufacturing cost can be greatly reduced by performing a lithography process for forming a gate fine pattern required at high integration using a conventional KrF. There is an advantage.

Claims (3)

반도체 소자 제조시 게이트 미세 패턴 형성방법에 있어서,In the method of forming a gate fine pattern when manufacturing a semiconductor device, (a)실리콘 기판에 게이트 절연막과 게이트 전극막을 순차적으로 적층시키는 단계와;(a) sequentially stacking a gate insulating film and a gate electrode film on a silicon substrate; (b)상기 게이트 전극용 감광막을 패터닝 수행하여 상기 게이트 전극막을 소정 깊이까지 건식 식각시키는 단계와;(b) dry etching the gate electrode film to a predetermined depth by patterning the photoresist film for the gate electrode; (c)게이트 길이 축소용 폴리실리콘을 오목한 형태의 요철 모양으로 증착시키는 단계와;(c) depositing polysilicon for reducing the gate length into a concave-convex shape; (d)상기 요철 부위에 게이트 전극 형성용 하드 마스크 산화막을 증착시키는 단계와;(d) depositing a hard mask oxide film for forming a gate electrode on the uneven portion; (e)상기 폴리실리콘과 산화막의 높은 건식 식각 선택비를 이용하여 게이트 미세패턴을 형성시키는 단계;를 포함하는 것을 특징으로 하는 게이트 미세 패턴 형성 방법.(e) forming a gate fine pattern using a high dry etching selectivity between the polysilicon and the oxide film. 제1항에 있어서,The method of claim 1, 상기 (c)단계에서, 상기 폴리실리콘은, 줄이고자 하는 게이트 길이의 양의 절반 두께로 게이트 형성 부위 양측면에 요철 모양으로 형성되는 것을 특징으로 하는 게이트 미세 패턴 형성 방법.In the step (c), the polysilicon, the gate fine pattern forming method, characterized in that formed in the concave-convex shape on both sides of the gate forming portion to a thickness of half the amount of the gate length to reduce. 제1항에 있어서,The method of claim 1, 상기 (d)단계에서, 상기 하드 마스크는, 상기 폴리실리콘의 단차보다 1.5배 이상의 높이로 상기 요철부위에 증착되며, CMP를 통해 평탄화되는 것을 특징으로 하는 게이트 미세 패턴 형성방법.In the step (d), the hard mask, the gate fine pattern forming method, characterized in that deposited on the uneven portion 1.5 times higher than the step of the polysilicon, and planarized through the CMP.
KR1020020086645A 2002-12-30 2002-12-30 Method for forming gate pattern minutely in semiconductor device fabrication process KR100620173B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990003857A (en) * 1997-06-26 1999-01-15 김영환 Photosensitive film formation method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990003857A (en) * 1997-06-26 1999-01-15 김영환 Photosensitive film formation method

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