200920158 八、 本案若有化學式時，請揭示最能顯示發明特 徵的化學式：（無） 九、 發明說明： 【發明所屬之技術領域】 本發明係有關於-種穿孔薄膜製法，尤指一種微電 子穿孔薄膜的製作方法。 【先前技術】 參閱圖1,習知一為本國專利公告第2〇〇5〇1788號 『矽麥克風之製造』，其主要方法係利用一第一晶圓 11,先分別於該第一晶圓彳彳之表面形成氧化層^、凹 穴112和重摻雜石夕I 113後，再取一第二晶圓12形成 金屬層122等，後利用微電子結合技術，結合該第一、 二晶圓11、12,再利用微電子電路之沉積、蝕刻、曝光、 清洗等習知製程，藉以形成具有一振動膜層114、一凹 穴112和複數外接電極端13之穿孔薄膜12彳，而達習 知一矽麥克風之製造。 參閱圖2，習知二為美國第6847〇9〇號專利之 『silicon capacity microphone (電容式矽麥克風）』， 其主要先於第一晶圓21形成一振動膜層211,再於第二 晶圓22之蟲晶層221上’設有複數穿透該蟲晶層221 之孔洞222’並於該第一晶圓21之表面，形成一支撐層 212後’藉由微電子結合技術把該第—、第二晶圓21、 22接合後，利用姓刻、曝光、清洗等習知製程，製造出 200920158 具有穿孔薄膜223和振動膜層211之習知二電容式矽麥 克風。 參閱圖 3’ ％知二揭露於 sens〇rs anc| actuators A87 (2001) PP.188-193 之『_丨 microphone using porous silicon as sacrificial layer for the air gap (利用多孔矽作為犧牲層之單晶矽麥克 風）』，其主要方法係藉由植佈重摻雜矽層3()於一晶圓 31之表面，隨後利用微電子電路之製程步驟，如沈積、 姓刻、曝光和清洗等習知製程，形成—犧牲層32、一振 動膜層33和金屬電極端34。再藉由該晶圓31背面之 另-金屬層作為蝕刻光罩35，以完成一穿孔薄膜％， 並進-步蝕刻該犧牲層32和重摻雜矽層3〇,完成一具 有間隔空間37的習知三利用多孔料為犧牲層之單晶 矽麥克風製作。 歸納上述’瞭解有關前述習知穿孔薄膜之製作過程 及方法’於實際製作中仍發現有多處缺失1將一 述如下： .利用晶圓之底層背面沈積之金屬層作為穿孔薄臈之 ㈣光罩時’晶圓背面㈣過深造成對焦、曝光及顯 影困難#外，因無輔助結構供以控制預留之穿孔 膜的孔洞大小及厚度’穿孔薄膜之孔徑常設計很小: 使钱刻液或㈣氣體難以到達犧牲層進行㈣， 形成7均句完整之間隔空間。再者，若預留之穿二 膜過薄’亦使製程更為艱難，結構強度大為降低，常 200920158 造f犧牲層蝕刻時穿孔薄膜破裂及與振動膜層產生 黏著現象，1率無法提升，導致成本過高。 2.不論單晶片或雙晶片之穿孔薄膜製作，若利用離子植 佈或擴散方法來控制重摻雜矽層深度及大小，將不易 準確控制其摻雜濃度的分佈深度，極難形成超過 1〇um以上之縱深分佈。另外，此法無法準確控制穿 孔薄膜之孔徑大小，且於晶圓後續回火製程，因重摻 雜石夕層深度不足，導致晶圓極易有高殘留應力，造成 晶圓易碎、弯曲，除製程良率低外，亦無法提高成品 效能。 本發明係提供解決上述穿孔薄膜製造上之相關問 題’並揭露子穿蘭膜製作方法，可使各類微感 測器和微電子電路整合於同—晶片，以減少雜訊干擾、 增加處理速度、提高品質和降低成本，以符合目前現代 各類民生產品以輕、薄、短、小和高整合性為主要發展 之趨勢。如何設計出一簡單有效的製程方法，確保生產 良率及產品之可靠度，且可大幅降低成本，長久以來一 直是業界殷切盼望及本發明人欲行解決之困難點所在。 【發明内容】 一般微電子穿孔薄膜，常用於微感測器且需另一振 動膜廣搭配，以建構一具間隔空間之電容式微感測器。 此電容式微感測器常用於偵測外界之物理性或化學性 變動量，如聲音、壓力、熱、位移、流量等，所造成該 電容值的變化，進一步把該電容值變化量轉換成電壓或 200920158 電流等易控制與處理之訊號。然均勻間隔空間之形成、 微電子牙孔薄膜之厚度與結構強度，則攸關電容式微感 測器製作成敗與否。 本發明之主要目的，在於提供一種有效控制微電子 穿孔薄膜厚度及孔徑大小之微電子穿孔薄膜製作方法。200920158 VIII. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: (none) IX. Description of the invention: [Technical field of the invention] The present invention relates to a method for producing a perforated film, especially a microelectronic A method of making a perforated film. [Prior Art] Referring to FIG. 1, the first method is the manufacture of a "microphone" by the national patent publication No. 2〇〇5〇1788, the main method of which is to use a first wafer 11 separately from the first wafer. After the oxide layer ^, the recess 112 and the heavily doped Ishi I 113 are formed on the surface of the crucible, a second wafer 12 is taken to form a metal layer 122, etc., and then the first and second crystals are combined by microelectronic bonding technology. Circles 11, 12, and then using conventional processes such as deposition, etching, exposure, cleaning, etc. of microelectronic circuits, thereby forming a perforated film 12彳 having a vibrating film layer 114, a recess 112, and a plurality of external electrode terminals 13 I know the manufacture of a microphone. Referring to FIG. 2, the second is the "silicon capacity microphone" of the U.S. Patent No. 6,847,9, which is mainly formed on the first wafer 21 to form a vibrating film layer 211 and then in the second crystal. The hole 22 of the circle 22 is provided with a plurality of holes 222' penetrating the insect layer 221 and formed on the surface of the first wafer 21 to form a support layer 212. After the second wafers 21 and 22 are joined, a conventional two-capacitance microphone having a perforated film 223 and a diaphragm layer 211 of 200920158 is manufactured by a conventional process such as engraving, exposure, and cleaning. Refer to Figure 3 '% know two exposed in sens〇rs anc| actuators A87 (2001) PP.188-193 "_丨microphone using porous silicon as sacrificial layer for the air gap (using a porous germanium as a sacrificial layer of single crystal germanium) Microphone), the main method is to heavily dope the germanium layer 3 () on the surface of a wafer 31, and then use the microelectronic circuit process steps, such as deposition, surname, exposure and cleaning, etc. A sacrificial layer 32, a vibrating film layer 33, and a metal electrode terminal 34 are formed. Then, a further metal layer on the back surface of the wafer 31 is used as the etching mask 35 to complete a perforated film %, and the sacrificial layer 32 and the heavily doped germanium layer 3 are further etched to complete a space 37. The conventional three is made of a single crystal chirp microphone using a porous material as a sacrificial layer. To sum up the above-mentioned 'understanding the manufacturing process and method of the above-mentioned conventional perforated film', in the actual production, many defects are still found as follows: 1. The metal layer deposited on the back side of the wafer is used as the perforated thin (four) light. When the cover is 'the back of the wafer (four) is too deep, causing focus, exposure and development difficulties #, outside, because there is no auxiliary structure to control the hole size and thickness of the perforated film reserved. 'The aperture of the perforated film is often designed very small: make money engraving Or (4) The gas is difficult to reach the sacrificial layer (4), forming a complete interval of 7 uniform sentences. In addition, if the reserved film is too thin, the process is more difficult, and the structural strength is greatly reduced. In the case of the 200920158, the perforated film is ruptured and the film is adhered to the vibrating layer, and the rate cannot be improved. , resulting in excessive cost. 2. Regardless of the fabrication of perforated films of single or double wafers, if ion implantation or diffusion methods are used to control the depth and size of the heavily doped germanium layer, it will be difficult to accurately control the distribution depth of the doping concentration, which is extremely difficult to form more than 1〇. The depth distribution above um. In addition, this method cannot accurately control the pore size of the perforated film, and in the subsequent tempering process of the wafer, due to insufficient depth of the heavily doped layer, the wafer is highly susceptible to high residual stress, resulting in fragile and curved wafers. In addition to low process yields, it is also impossible to improve the performance of finished products. The invention provides a solution to the above-mentioned problems in the manufacture of the perforated film and discloses a method for fabricating the sub-blue film, which can integrate various micro-sensors and micro-electronic circuits into the same wafer to reduce noise interference and increase processing speed. Improve quality and reduce costs, in line with the current trend of modern, various types of people's livelihood products with light, thin, short, small and high integration. How to design a simple and effective process method to ensure the production yield and reliability of the product, and to greatly reduce the cost, has long been the industry's eagerly awaited and the inconvenience of the inventor to solve. SUMMARY OF THE INVENTION A general microelectronic perforated film is commonly used in a micro-sensor and requires a wide mix of vibrating membranes to construct a capacitive micro-sensor with a spaced space. The capacitive micro-sensor is often used to detect external physical or chemical fluctuations, such as sound, pressure, heat, displacement, flow, etc., which cause changes in the capacitance value, and further convert the capacitance value into a voltage. Or 200920158 Current and other signals that are easy to control and process. However, the formation of a uniform space, the thickness and structural strength of the microelectronic aperture film, the success or failure of the capacitive micro-sensor. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for fabricating a microelectronic perforated film which effectively controls the thickness and pore size of a microelectronic perforated film.
本發明之又一目的，在於提供一種增加微電子穿孔 薄膜厚度及結構強度，避免該微電子穿孔薄膜破裂及與 振動膜層產生黏著之製作方法。 本發明之又一目的，在於提供一種增加微電子穿孔 薄膜孔徑大小，進而增加蝕刻液進出犧牲層之流量、犧 牲層之蝕刻速率、間隔空間均勻性之製作方法。 本發明之又一目的，在於提供一種有效控制微電子 穿孔薄膜上方保護層、犧牲層、振動膜層與導電層之平 坦度製作方法。 本發明之又一目的，在於提供一種微電子穿孔薄膜 製作方法，其主要方法係於__微電子基板之表面預設位 置，姓刻形成至少-内篏於該微電子基板中之内嵌槽 溝。該内㈣溝之斷面形狀係可依製程需求選擇設計為 圓形、四邊形、三角形、多邊形、不規則形及田字形之 一者0 種微電子穿孔薄膜 ，定義至少一支辅 選擇設計為圓形、 之一者；該輔助結 本發明之又一目的，在於提供— 製作方法，係可於該内篏槽溝位置中 助結構。該辅助結構之斷面形狀係可 四邊形、三角形、多邊形及不規則形 200920158 構之材料可依需求選擇金屬材料、非金屬材料、金屬化 合物、非金屬化合物及其中組合式之一者；而該輔助結 構之形成方法，可依製程需求選擇與該微電子基板一體 成型、分開成型之一者。 本發月之又目的，在於提供一種微電子穿孔薄膜 製作方法，係可於該内篏槽溝位置中，便於選擇一些金Another object of the present invention is to provide a method for fabricating a microelectron perforated film thickness and structural strength to prevent cracking of the microelectronic perforated film and adhesion to the vibrating film layer. Another object of the present invention is to provide a method for increasing the pore size of a microelectronic perforated film, thereby increasing the flow rate of the etching solution into and out of the sacrificial layer, the etching rate of the sacrificial layer, and the uniformity of the space between the spacers. Another object of the present invention is to provide a method for fabricating a flat layer of a protective layer, a sacrificial layer, a vibrating film layer and a conductive layer above the microelectronic perforated film. Another object of the present invention is to provide a method for fabricating a microelectronic perforated film, the main method of which is to preset a position on the surface of the __microelectronic substrate, and the last name forms at least the inner groove embedded in the microelectronic substrate. ditch. The cross-sectional shape of the inner (four) groove can be selected as one of a circular, quadrilateral, triangular, polygonal, irregular shape and a shape of one of the microelectronic perforated films according to the process requirements, and at least one auxiliary selection design is defined as a circle. One of the objects of the present invention is to provide a method of making a structure in the position of the inner gutter. The cross-sectional shape of the auxiliary structure is a quadrilateral, a triangular shape, a polygonal shape, and an irregular shape. The material of the 200920158 structure can select one of a metal material, a non-metal material, a metal compound, a non-metal compound, and a combination thereof according to requirements; and the auxiliary The method for forming the structure may be one of integrally forming and separately forming the microelectronic substrate according to the process requirements. The purpose of this month is to provide a microelectronic perforated film manufacturing method, which is convenient for selecting some gold in the position of the inner groove.
屬材料、非金屬材料、金屬化合物及其中組合式之一， 以填充該内篏槽溝。 ^本發月之又目的，在於提供一種微電子穿孔薄膜 製作方法，可於填充材料後，依需求選擇於該微電子基 板具内嵌槽溝面’以物理性、化學性及其兩者組合者之 的平坦化製程，達到平坦化目的。 〗本發明之又-目的，在於提供—種微電子穿孔薄膜 製作方法’可依需求選擇於該微電子基板具内篏槽溝面 成長保護層、犧牲層、振動膜與導電層。 本發明之另-目的，在於提供一種微電子穿孔薄膜 製作方法，係可利用高選擇比之钱刻方式，在該微電子 板八内篏槽溝面做姓刻保護後，先行由該微電子基板 :内敗槽溝面之異面預設位置，钱刻至該内篏槽溝之底 部，或使部份内篏槽溝裸露出，藉以控制㈣孔薄膜之 厚度。 本發月之另-目的，在於提供__種微電子穿孔薄膜 製作方法’可先選擇—高選擇比姓刻方式，對該微電子 基板Μ篏槽溝面之異面的内篏槽料填充材料進行钱 200920158 刻0 本發明之另一目的，在於提供一種微電子穿孔薄膜 製作方法，可針對該微電子基板具内篏槽溝面之犧牲 層，選擇一南選擇比敍刻方式，藉由上述所形成内嵌槽 溝之開孔’使該内篏槽溝中之辅助結構自動脫離，進而 增加微電子穿孔薄膜之孔徑尺寸。 本發明之又一目的，在於提供一種微電子穿孔薄膜It is one of a material, a non-metal material, a metal compound, and a combination thereof to fill the inner gutter. The purpose of this month is to provide a microelectronic perforated film manufacturing method, which can be selected after the filling of the material, and the combination of the physical and chemical properties of the microelectronic substrate. The flattening process of the person achieves the purpose of flattening. Further, another object of the present invention is to provide a method for fabricating a microelectronic perforated film, which can be selected from the surface of the microelectronic substrate to have a protective layer, a sacrificial layer, a vibrating film and a conductive layer. Another object of the present invention is to provide a method for fabricating a microelectronic perforated film, which can utilize the high selection ratio and the engraving method to perform the protection of the surname on the surface of the microelectronic board. Substrate: The preset position of the opposite surface of the inner groove surface, the money is engraved to the bottom of the inner groove, or the inner groove is exposed, thereby controlling the thickness of the (four) hole film. The other purpose of this month is to provide a method for fabricating a microelectronic perforated film, which can be selected first—a high-selection ratio pattern, and the inner surface of the microelectronic substrate is grooved. Material Carrying Money 200920158 Note 0 Another object of the present invention is to provide a method for fabricating a microelectronic perforated film, which can select a south selective ratio sculpt for the sacrificial layer of the inner surface of the microelectronic substrate. The opening of the inlaid groove formed as described above automatically disengages the auxiliary structure in the inner groove, thereby increasing the aperture size of the microelectronic perforated film. Another object of the present invention is to provide a microelectronic perforated film
製作方法，係可容易整合於現有的微電子製程中，達成 提高品質及降低生產成本。 【實施方式】 兹為使貴審查委員對本發明之方法所達成功效有 進一步之瞭解與認識’謹佐以較佳實施圖例及配合本發 明之詳細說明如下： 如圖4所示，係為本發明之微電子穿孔薄膜之微電 子基板之立體示意圖。其係先提供一微電子基板Μ，再 選擇金屬材料、非金屬材料、金屬化合物、非金屬化合 物及其中組合式之一者’藉由一般微電子之沈積方式， 於該微電子基& 41之-表面，形成至少-層保護層 411,而該保護層411可分別選擇具保護、緩衝、絕緣、 隔離及導電功效者。配合圖5所示，可選擇於該微電子 基板41與該微電子基板41的保護層411之—者的表 面，於該表面之預定位置’利用-般微電子之乾姓刻、 ㈣刻方式及其混合制之其中之—者，#刻形成至少 -内篏於該微電子基板41中的内篏槽溝412，而該内篏 200920158 槽溝412之斷面形狀可依製程需求選擇設計為圓形、四 邊形、三角形、多邊形、不規卿及田字形之—者該 實施例係以田字形形成。 仍參閱圖5,再定義至少—辅助結構413於該内嵌 槽溝扣中，該辅助結構413之數目、斷面形狀及尺寸 大】可隨圖6的填充材料414之製程特性與該内篏槽 、 之’莱度、斷面形狀和尺寸大小作相對調整。該輔The production method can be easily integrated into the existing microelectronics process to achieve improved quality and lower production costs. [Embodiment] A further understanding and understanding of the effects achieved by the method of the present invention will be provided. The detailed description of the preferred embodiment and the accompanying drawings are as follows: A schematic view of a microelectronic substrate of a microelectronic perforated film. The first is to provide a microelectronic substrate Μ, and then select one of a metal material, a non-metal material, a metal compound, a non-metal compound, and a combination thereof, by means of general microelectronic deposition, on the microelectronic substrate & 41 The surface is formed with at least a protective layer 411, and the protective layer 411 can be selected for protection, buffering, insulation, isolation, and electrical conductivity, respectively. As shown in FIG. 5, the surface of the microelectronic substrate 41 and the protective layer 411 of the microelectronic substrate 41 can be selected, and the predetermined position of the surface is used to perform the "four-inscription" method using the general microelectronics. And the mixture thereof is formed, and at least the inner groove groove 412 is formed in the microelectronic substrate 41, and the cross-sectional shape of the inner groove 200920158 groove 412 can be selected according to the process requirements. The circle, the quadrangle, the triangle, the polygon, the irregular, and the figure are formed in the form of a field. Still referring to FIG. 5, at least the auxiliary structure 413 is defined in the inner groove groove. The number, shape and size of the auxiliary structure 413 are large. The process characteristics of the filling material 414 of FIG. The groove, the 'degree of view, the section shape and the size are relatively adjusted. The auxiliary
助結構川之斷面形狀可選擇設計為圓形、四邊形、三 角形 '多邊形及不規則形之—者。該辅助結構413之材 枓可依需求選擇金屬材料、非金屬材料、金屬化合物、 \屬化《物及其中組合式之—者。*該辅助結構川 之形成方法，可依製程需求選擇與該微電子基板41 一 體成型、分開成型之-者。如圖5,該實施例係選擇以 4支正方形石夕晶之輔助結構413,與該微電子基板41 一 體成型於每一内篏槽溝412中。 續參閱圖6 ’該内篏槽冑412可選擇一填充材料 ’例如：金屬材料、非金屬材料、金屬化合物、非 金屬化合物及其中組合式之-者，填充於該内嵌槽溝 二。而該填充材料414之高度係可選擇高於該保護 之上j面，如圖7所示，亦可選擇與該保護層411 之上表面同南度，如菌q __ ^ _ 圖8所不。而當選擇該填充材料4】4 :问度π於該保蠖層4”之上表面者，可先將該微電子 土板41具該填充材料414之表面，以物理性、化學性 及其兩者組合者之〜的平坦化製程’將高於該保護層 200920158 4”之填充材料414去除，如圖8態樣，使該填充材料 414與該保護層41彳之上表面同高度。 請參閲圖9’再藉由微電子之沈積的方式，於該内 篏槽溝412和該保護層411之上表面，形成至少一犧牲 層415及至少-振動膜層416，其中，該犧牲層415和 該振動膜層416，可分別選擇以金屬材料、非金屬材料、 金屬化合物、非金屬化合物及其組合式之一製作：例如 氧化層、氮化石夕' 單晶碎 '多晶石夕、鈦、氮化鈦（TjN)、 鋁、銅、金、銀、金屬化合物、其他金屬物質及其組合 式之一製作而成。 並參閱圖10’可於該振動膜層416與該微電子基板 41具内篏槽溝412面上，選擇沈積及植佈一導電材料 後，再藉由一微電子電路之製程步驟，如蝕刻、曝光和 清洗等步驟，分別定義圖案以作為該振動膜層416之外 部電極層417和微電子基板41上保護層41彳之外部電 極端418。 仍參閱圖10，可續於該微電子基板41具該内嵌槽 溝412面之異面預定位置，藉由一般微電子之沈積、蝕 刻、曝光和清洗等步驟，選擇利用金屬材料、非金屬材 料、金屬化合物、非金屬化合物及其組合式之一者，於 該微電子基板41具該内篏槽溝412面之異面，形成一 姓刻保護層41 9。此外，該钱刻保護層41 g之製程順序， 可選擇先於該外部電極層417和外部電極端418，亦可 選擇後於該外部電極層417和外部電極端418。 12 200920158 奴後，將該微電子基板41具該内篏槽溝412面作 ㈣保護’再利用_方式’由該微電子基板41具該 内欲槽溝412面之異面預設位置，蝕刻該微電子基板41 至該内篏槽溝412底部或使部份内嵌槽溝412裸露出 來，分別如圖11、12所示。其中，該蝕刻方式可選擇 以乾蝕刻方式，亦可用EDp、……、K〇H(氫氧化鉀）、 TMAH(氫氧化四卸錄）、HF、B〇E、硫酸、紹姓刻液、 金蝕刻液之濕蝕刻方式及其混合使用之其中之一者。 如圖13所示，再進一步利用一般微電子之高選擇 比蝕刻方法，先行對該内篏槽溝412内之填充材料414 蝕刻後，再針對該保護層411上該犧牲層415選擇另一 或相同之尚選擇比蝕刻方法，其中，該兩高選擇比之蝕 刻方法，可各別依製程需求選擇乾蝕刻方式與包含 EDP、Ν#2、KOH(氫氧化鉀）、TMAH(氫氧化四鉀銨）、 HF、BOE、硫酸、鋁蝕刻液、金蝕刻液之濕蝕刻方式及 其混&使用之其中之一者，藉由上述形成於該内篏槽溝 412之開孔，蝕刻該犧牲層415，待該輔助結構413上 方部分之犧牲層415蝕刻後，該内篏槽溝412内之輔助 結構413便自動脫離該微電子基板41，以增加蝕刻液進 入飯刻該犧牲層415之通道，進而完成間隔空間42，俾 精準控制該微電子穿孔薄膜40之厚度和開孔大小，如 圖14所示。 綜合上述，當知本發明係有關於一種微電子薄膜之 製作方法，尤指一種微電子穿孔薄膜40製作方法，其 13 200920158 主要方法係包含提供一微電子基板41，且形成有至少一 内篏於該微電子基板41中之内篏槽溝412於該微電子 基板41之表面預設位置上，再定義該内篏槽溝412内 之輔助結構413，並選擇填充材料414，填充於該内篏 槽溝412。 隨後’再由該微電子基板41具該内篏槽溝412面 之異面的預設位置，利用一高選擇比之蝕刻方法，蝕刻 該微電子基板41至該内篏槽溝412底部或裸露部份内 篏槽溝412。再進一步選擇利用高選擇比蝕刻方式先 行對該内篏槽溝412之填充材料414蝕刻後，再針對該 保護層411上之犧牲層41 5，選擇高選擇比蝕刻方式， 藉由上述形成於該内篏槽溝412之開孔，使該内篏槽溝 412内之輔助結構413上方部分之犧牲層41 5被蝕刻 後，自動脫離該微電子基板41，增加後續钱刻液進入該 犧牲層415之通道，使蝕刻液流量更高，俾以提高蝕刻 率及均勻蝕刻該犧牲層415。達到精準控制穿孔薄膜4〇 厚度及開孔大小，並增加穿孔薄膜4〇結構強度，且可 避免穿孔薄膜40與振動膜層416黏著，以及縮短該犧 牲層415蝕刻時間，更能增加該間隔空間42之均勻性， 故確實可提高產品效能與生產良率並降低製作成本者。 本發明實為一富有新穎性、進步性，及可供產業利 用功效者，應符合專利申請要件無疑，爰依法提請發明 專利申請，懇請貴審查委員早曰賜予本發明專利，實 感德便。 200920158 任何熟悉此技藝者，在不脫離本創作發明之精神或 範圍内，可作各種結構之更動與潤飾，凡依本創作發明 精神及以下專利申請範圍所作之各種變動及潤飾均屬 本創作之範圍。 【圖式簡單說明】 圖1 .係習知揭露於台灣專利第2〇〇5〇1788號之『矽麥 克風之製造方法』之局部截面示意圖；The shape of the cross-section of the auxiliary structure can be selected as a circle, a quadrangle, a triangle, a 'polygon and an irregular shape'. The material of the auxiliary structure 413 can be selected according to the requirements of the metal material, the non-metal material, the metal compound, the "generator" and the combination thereof. * The method for forming the auxiliary structure can be selected and formed separately from the microelectronic substrate 41 according to the process requirements. As shown in Fig. 5, this embodiment selects an auxiliary structure 413 of four square stones, and the microelectronic substrate 41 is integrally formed in each of the inner trenches 412. Continuing to refer to Fig. 6', the inner trench 412 may be selected from a filling material 'e.g., a metal material, a non-metal material, a metal compound, a non-metal compound, and a combination thereof, to be filled in the inner trench 2 . The height of the filling material 414 can be selected to be higher than the j-plane above the protection. As shown in FIG. 7, it can also be selected to be the same as the upper surface of the protective layer 411, such as the bacteria q __ ^ _ . When the filling material 4]4 is selected: the degree of π is above the surface of the protective layer 4", the surface of the filling material 414 may be firstly applied to the surface of the filling material 414 to be physically and chemically The flattening process of the combination of the two is removed from the filling material 414 of the protective layer 200920158 4, as shown in FIG. 8 such that the filling material 414 is at the same height as the upper surface of the protective layer 41. Referring to FIG. 9 ′, at least one sacrificial layer 415 and at least a diaphragm layer 416 are formed on the inner trench groove 412 and the upper surface of the protective layer 411 by means of deposition of microelectronics, wherein the sacrifice The layer 415 and the vibrating membrane layer 416 can be respectively selected by one of a metal material, a non-metal material, a metal compound, a non-metal compound, and a combination thereof: for example, an oxide layer, a nitriding stone, a single crystal, and a polycrystalline stone. Made of titanium, titanium nitride (TjN), aluminum, copper, gold, silver, metal compounds, other metal materials and combinations thereof. Referring to FIG. 10', the vibrating film layer 416 and the microelectronic substrate 41 are provided with an inner trench groove 412, and a conductive material is deposited and implanted, and then processed by a microelectronic circuit, such as etching. The steps of exposing and cleaning are respectively defined as the outer electrode layer 417 of the vibrating film layer 416 and the outer electrode end 418 of the protective layer 41 on the microelectronic substrate 41. Still referring to FIG. 10, the microelectronic substrate 41 may have a predetermined position on the surface of the inscribed groove 412, and the metal material and the non-metal are selected by the steps of deposition, etching, exposure, and cleaning of general microelectronics. One of a material, a metal compound, a non-metal compound, and a combination thereof, the microelectronic substrate 41 has a different surface of the inner groove 412 surface to form a protective layer 41 9 . In addition, the processing sequence of the protective layer 41g may be selected before the external electrode layer 417 and the external electrode terminal 418, or may be selected after the external electrode layer 417 and the external electrode terminal 418. 12 200920158 After the slave, the microelectronic substrate 41 has the inner groove 412 surface as (4) protection 'reuse_method' from the microelectronic substrate 41 having the opposite position of the inner groove 412 surface, etching The microelectronic substrate 41 is exposed to the bottom of the inner trench 412 or a portion of the inner recessed trench 412, as shown in FIGS. The etching method may be selected by dry etching, or may be EDp, ..., K〇H (potassium hydroxide), TMAH (hydrogen hydride), HF, B〇E, sulfuric acid, Shaosheng engraving, One of the wet etching methods of gold etching liquid and its mixed use. As shown in FIG. 13, the high-selection ratio etching method of the general microelectronics is further used, after the filling material 414 in the inner trench 412 is etched, and then the sacrificial layer 415 on the protective layer 411 is selected to be another or The same is preferred than the etching method, wherein the two high-selection etching methods can be selected according to the process requirements, and the dry etching method is selected to include EDP, Ν#2, KOH (potassium hydroxide), TMAH (tetrapotassium hydroxide). One of the wet etching methods of ammonium, HF, BOE, sulfuric acid, aluminum etching solution, gold etching solution, and the use thereof, etching the sacrifice by the opening formed in the inner groove 412 After the sacrificial layer 415 of the upper portion of the auxiliary structure 413 is etched, the auxiliary structure 413 in the inner trench 412 is automatically separated from the microelectronic substrate 41 to increase the passage of the etching solution into the sacrificial layer 415. Then, the space 42 is completed, and the thickness and opening size of the microelectronic perforated film 40 are precisely controlled, as shown in FIG. In summary, the present invention relates to a method for fabricating a microelectronic film, and more particularly to a method for fabricating a microelectronic perforated film 40. The method of 13 200920158 includes providing a microelectronic substrate 41 and forming at least one inner crucible. In the microelectronic substrate 41, the inner trench 412 is at a predetermined position on the surface of the microelectronic substrate 41, and the auxiliary structure 413 in the inner trench 412 is defined, and the filling material 414 is selected and filled therein. Groove ditch 412. Then, the microelectronic substrate 41 has a predetermined position of the opposite surface of the inner trench 412, and the microelectronic substrate 41 is etched to the bottom or the bottom of the inner trench 412 by a high selective etching method. Part of the inner groove 412. Further, the high-selection etching method is used to etch the filling material 414 of the inner trench 412, and then the high-selection etching method is selected for the sacrificial layer 41 5 on the protective layer 411. The opening of the inner trench 412 causes the sacrificial layer 41 5 in the upper portion of the auxiliary structure 413 in the inner trench 412 to be etched, and then automatically detaches from the microelectronic substrate 41, thereby increasing the subsequent money engraving into the sacrificial layer 415. The channel is such that the flow rate of the etchant is higher, and the etching rate is increased and the sacrificial layer 415 is uniformly etched. The thickness of the perforated film and the size of the opening are precisely controlled, and the structural strength of the perforated film is increased, and the perforation film 40 is prevented from adhering to the vibrating film layer 416, and the etching time of the sacrificial layer 415 is shortened, and the space is further increased. The uniformity of 42 can indeed improve product performance and production yield and reduce production costs. The invention is a novelty, progressive, and available for industrial use, and should meet the requirements of the patent application. The invention patent application is filed according to law, and the examination committee is invited to give the invention patent as soon as possible. 200920158 Anyone who is familiar with the art can make various changes and refinements of the structure without departing from the spirit and scope of the invention. All changes and refinements made in accordance with the spirit of the invention and the scope of the following patent applications belong to this creation. range. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial cross-sectional view showing the "manufacturing method of buckwheat gram wind" disclosed in Taiwan Patent No. 2〇〇5〇1788;
圖2:係習知揭露於美國專利第6847〇9〇號之『印丨七如 capacity microphone (電容式矽麥克風）』之局 部截面示意圖； ° 圖3:係習知揭露於Sens〇rs _贿⑽1) ΡΡ·18β-193 : r Single.Chjp c〇ndensers 睛⑽咖 usin9 Ρ〇_ silicon as sacrifice layerfortheairgap (利用多孔石夕犧 牲層形成空間之單晶石夕電容式麥克風）』之局部 截面示意圖； 圖4:係本發明微電子穿孔薄膜製作方法’形成保護層 之局部立體示意圖 圖5 圖6 圖 係本發明微電子穿孔薄膜製作方法，形成内篏槽 溝和定義辅助結構之局部立體示意圖； I:本發明微電子穿孔薄媒製作方法，内篏槽溝内 填充材料後之局部俯視示意圖； 係填本發明微電子穿孔薄膜製作方法，内嵌槽溝内 材料高度高於保護層上表面截面示㈣； 15 200920158 圖8 圖9 ： 圖10 圖11 : 圖12 : 圖13 : 圖14 : :係本發明微電子穿孔薄膜 # _1 一 猓製作方法，内篏槽溝内 填充材料高度等於保護層 臂上表面之截面示意圖； 係本發明微電子穿孔薄膜製 联衣作方法，形成犧牲層 振動膜層之局部截面示意圖. •係本發明微電子穿孔薄膜激 联裂作方法，定義形成外 部電極層、外部電極端及楙雷 啼及微電子基板具内篏槽溝 面之異面的蝕刻保護層局部截面示意圖； 係本發明微電子穿孔薄膜製作方法，由微電子基 板具内篏槽溝面之異面，姓刿 蚀刻至内篏槽溝底部之 局部截面示意圖； 係本發明微電子穿孔薄膜製作方法，由微電子基 板具内篏槽溝面之異面’蝕刻形成裸露部份内篏 槽溝之局部截面示意圖； 係本發明微電子穿孔薄膜製作方法’内篏槽溝之 填充材料完全被钮刻後之局部截面示意圖；及 係本發明微電子穿孔薄膜製作方法，犧牲層被蝕 刻’且内篏槽溝内之辅助結構自動脫離微電子基 板後’形成間隔空間及微電子穿孔薄膜之局部截 面示意圖。 200920158Figure 2: is a partial cross-sectional view of the U.S. Patent No. 6,847,9, 丨 丨 cap cap cap cap cap cap cap cap cap cap ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; (10)1) ΡΡ·18β-193 : r Single.Chjp c〇ndensers Eye (10) coffee usin9 Ρ〇 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ FIG. 4 is a partial perspective view showing a method for fabricating a microelectronic perforated film according to the present invention. FIG. 6 is a partial perspective view showing a method for fabricating a microelectronic perforated film according to the present invention, forming an inner gutter groove and defining an auxiliary structure; The method for fabricating a microelectronic perforated thin medium according to the present invention is a partial top view of a material filled in a trench; the method for fabricating the microelectronic perforated film of the present invention, wherein the height of the material in the embedded trench is higher than the upper surface of the protective layer (4); 15 200920158 Figure 8 Figure 9: Figure 10 Figure 11: Figure 12: Figure 13: Figure 14: : The microelectronic perforated film of the present invention # _1 A method of making, in the inner groove The cross-sectional view of the height of the filling material is equal to the upper surface of the protective layer arm; the partial cross-section of the vibrating film layer of the sacrificial layer is formed by the microelectronic perforated film manufacturing method of the present invention. A partial cross-sectional view showing an etching protective layer forming an external electrode layer, an external electrode end, and a different surface of the germanium rake and the microelectronic substrate having the inner groove surface; the method for fabricating the microelectronic perforated film of the present invention, comprising a microelectronic substrate A partial cross-section of the inner surface of the inner groove surface, which is etched to the bottom of the inner groove; is a method for fabricating the microelectronic perforated film of the present invention, and the microelectronic substrate has a different surface of the inner groove groove to form a bare A partial cross-sectional view of a portion of the inner grooving groove; a partial cross-sectional view of the filling material of the inner grooving groove of the present invention, which is completely engraved by the button; and a method for fabricating the microelectronic perforated film of the present invention, sacrificing The layer is etched' and the auxiliary structure in the inner trench is automatically separated from the microelectronic substrate to form a space and microelectronics A partial cross-sectional schematic view of the apertured film. 200920158
【主要元件符號說明】 11 第一晶圓 111 氧化層 112 凹穴 113 重摻雜矽層 114 振動膜層 12 第二晶圓 121 穿孔薄膜 122 金屬層 13 外接電極端 21 第一晶圓 211 振動膜層 212 支撐層 22 第二晶圓 221 蠢晶層 222 孔洞 223 穿孔薄膜 30 重摻雜矽層 31 晶圓 32 犧牲層 33 振動膜層 34 金屬電極端 35 蝕刻光罩 36 穿孔薄膜 37 間隔空間 40 微電子穿孔薄膜 41 微電子基板 411 保護層 412 内篏槽溝 413 輔助結構 414 填充材料 415 犧牲層 416 振動膜層 417 外部電極層 418 外部電極端 419 蝕刻保護層 42 間隔空間 17[Main component symbol description] 11 First wafer 111 Oxide layer 112 Pocket 113 Heavy doped germanium layer 114 Vibration film layer 12 Second wafer 121 Perforated film 122 Metal layer 13 External electrode terminal 21 First wafer 211 Vibration film Layer 212 support layer 22 second wafer 221 stray layer 222 hole 223 perforated film 30 heavily doped germanium layer 31 wafer 32 sacrificial layer 33 diaphragm layer 34 metal electrode end 35 etching mask 36 perforated film 37 space 40 micro Electron perforated film 41 Microelectronic substrate 411 Protective layer 412 Inner groove 413 Auxiliary structure 414 Filling material 415 Sacrificial layer 416 Vibrating film layer 417 External electrode layer 418 External electrode end 419 Etching protective layer 42 Space 17