CN107994023B - Process for preparing superfine pore structure - Google Patents
Process for preparing superfine pore structure Download PDFInfo
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- CN107994023B CN107994023B CN201711140505.8A CN201711140505A CN107994023B CN 107994023 B CN107994023 B CN 107994023B CN 201711140505 A CN201711140505 A CN 201711140505A CN 107994023 B CN107994023 B CN 107994023B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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Abstract
The invention relates to a preparation process of an ultrafine pore structure, which comprises the following steps: providing a chip structure; etching is carried out, a contact hole is formed in the top layer deposition film of the chip structure, and the upper surface of the tungsten plug in the second top layer deposition film is exposed in the contact hole; depositing silicon dioxide into the contact hole, and forming a silicon dioxide deposition layer on the side wall of the contact hole and the upper surface of the tungsten plug so as to form a superfine hole; carrying out high-temperature annealing on the silicon dioxide deposition layer; carrying out wet cleaning to remove a part of silicon dioxide deposition layer positioned on the upper surface of the tungsten plug in the superfine hole; depositing an adhesive material into the superfine holes to form an adhesive layer; and depositing tungsten into the superfine pores to fill the residual pores of the superfine pores with the tungsten to form a superfine pore structure. According to the invention, the high-temperature annealing step of the silicon dioxide side wall is added in the forming process of the superfine pore structure, so that the influence of the subsequent wet cleaning and bonding material deposition steps on the thickness of the side wall is reduced, and the size of the superfine pore structure is ensured.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing processes, in particular to a manufacturing process of an ultrafine pore structure.
Background
With the continuous development of semiconductor technology, the memory manufacturing technology has gradually transited from a simple planar structure to a more complex three-dimensional structure, and the technical development of 3DNAND is one of the mainstream of international research and development
The structure of 3DNAND is generally implemented by depositing a multi-layered thin film and then etching to form a contact hole for connecting a wiring layer in a lower layer with a wiring layer in an upper layer in 3 DNAND. In recent processes, and in order to improve the performance of memories, the diameter of contact holes becomes ultra-fine.
In the process of the superfine hole, the size of the hole is often reduced by using a silicon dioxide side wall technology, and the specific method is that a contact hole with a common size is formed in a thin film layer by etching, and the surface of a lower tungsten plug is exposed; then, a silicon dioxide layer is formed on the side wall of the contact hole through deposition and wet cleaning to form a superfine hole, then a bonding layer is deposited on the inner wall of the superfine hole, and tungsten is deposited in the residual hole to finally form a superfine hole structure.
In actual production operation, in order to prevent the lower tungsten plug from being oxidized, the silicon dioxide side wall needs to grow in a low-temperature atomic layer deposition mode. The silicon dioxide layer generated by low-temperature atomic layer deposition has two adverse factors, namely, the wet etching rate is high and the silicon dioxide layer is easy to shrink at high temperature.
Disclosure of Invention
The present invention has been made to solve at least one of the above problems, and an object of the present invention is to provide a process for producing an ultrafine pore structure.
A preparation process of an ultrafine pore structure comprises the following steps:
and providing a chip structure, wherein the chip structure comprises a substrate and a plurality of layers of deposited films sequentially deposited on the surface of the substrate, and a tungsten plug penetrating through the deposited films is arranged in the next-to-top deposited film.
And etching to form a contact hole in the top layer deposited film, wherein the contact hole extends downwards from the upper surface of the top layer deposited film to the upper surface of the next top layer deposited film, and the upper surface of the tungsten plug is exposed in the contact hole.
And depositing silicon dioxide into the contact hole, and forming a silicon dioxide deposition layer on the side wall of the contact hole and the upper surface of the tungsten plug to form a superfine hole.
And carrying out high-temperature annealing on the silicon dioxide deposition layer.
And performing wet cleaning to remove part of the silicon dioxide deposition layer on the upper surface of the tungsten plug in the superfine hole, so that the upper surface of the tungsten plug is exposed in the superfine hole.
And depositing a bonding material into the superfine hole, and forming a bonding layer on the surface of the residual silicon dioxide deposition layer on the inner wall of the superfine hole and the upper surface of the tungsten plug.
And depositing tungsten into the superfine pores to fill the residual pores of the superfine pores with the tungsten to form a superfine pore structure.
Wherein, in the step of depositing the bonding material, the deposition temperature of the bonding material is 550-650 ℃, and in the step of high-temperature annealing, the temperature of the high-temperature annealing is 550-650 ℃.
In the step of depositing the silicon dioxide, the deposition method of the silicon dioxide is low-temperature atomic layer deposition.
Wherein the deposition temperature of the bonding material is 600 ℃, and the high-temperature annealing temperature is 600 ℃.
Wherein the deposition temperature of the silicon dioxide is 50 ℃.
The invention has the following beneficial effects:
according to the invention, the high-temperature annealing step of the silica side wall is added in the forming process of the superfine pore structure, so that the influence of the subsequent wet cleaning and bonding material deposition steps on the thickness of the side wall is reduced, the size of the superfine pore structure is ensured, and the deposition temperature of the bonding layer and the high-temperature annealing temperature are both arranged at about 600 ℃, so that the purpose of accurately controlling the size of the superfine pore is achieved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a flow chart illustrating a process for manufacturing an ultra fine pore structure according to an embodiment of the present invention.
Fig. 2a to 2g are structural flow charts illustrating a manufacturing process of an ultra fine pore structure according to an embodiment of the present invention.
Wherein, 1, chip structure; 10. depositing a film on the top layer; 20. depositing a film on the secondary top layer; 100. a contact hole; a 120 silicon dioxide deposition layer; 200. superfine pores; 210. a tungsten plug; 220 adhesive layer.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The basic idea of the invention is that in the process of forming the superfine pore structure size by the silica side wall technology, after the silica layer is formed by deposition, a step of rapid high-temperature annealing is added to improve the quality of the silica layer side wall and reduce the influence of the subsequent forming process on the silica layer side wall.
As shown in fig. 1, the present invention provides a process for preparing an ultra-fine pore structure, comprising the steps of:
providing a chip structure, wherein the chip structure comprises a substrate and a plurality of layers of deposition films sequentially deposited on the surface of the substrate, and a tungsten plug penetrating through the deposition films is arranged in the next top layer deposition film; etching is carried out, a contact hole is formed in the top layer deposition film, the contact hole extends downwards from the upper surface of the top layer deposition film to the upper surface of the next top layer deposition film, and the upper surface of the tungsten plug is exposed in the contact hole; depositing silicon dioxide in the contact hole, and forming a silicon dioxide deposition layer on the side wall of the contact hole and the upper surface of the tungsten plug to form a superfine hole; carrying out high-temperature annealing on the silicon dioxide deposition layer; wet cleaning is carried out, and a part of silicon dioxide deposition layer positioned on the upper surface of the tungsten plug in the superfine hole is removed, so that the upper surface of the tungsten plug is exposed in the superfine hole; depositing a bonding material into the superfine hole, and forming a bonding layer on the surface of the residual silicon dioxide deposition layer on the inner wall of the superfine hole and the upper surface of the tungsten plug; and depositing tungsten into the superfine pores to fill the residual pores of the superfine pores with the tungsten to form a superfine pore structure.
The process for forming the ultra fine pore structure according to the present invention will be explained in detail below by way of specific examples with reference to fig. 2a to 2g, wherein fig. 2a to 2g are flow charts of longitudinal sectional structures of the forming process of the present application, and each of fig. 2a to 2g shows structural changes occurring in the corresponding step.
Fig. 2a corresponds to the step of providing the chip structure of fig. 1. As shown in fig. 2a, a chip structure 1 is provided, the chip structure 1 includes a substrate (not shown in the figure) and a plurality of deposited films sequentially deposited on the surface of the substrate, and among the remaining deposited films of the chip structure 1 except for the top deposited film 10, at least a tungsten plug 210 is disposed in the next-to-top deposited film 20 and penetrates through the interior of the next-to-top deposited film 20. Typically, the substrate is a silicon wafer and the multilayer deposited film is alternating layers of silicon nitride and silicon oxide.
Fig. 2b corresponds to the step of etching to form contact holes of fig. 1. As shown in fig. 2b, a contact hole 100 is etched in the top deposited film 10 at the top position of the multi-layered deposited film, and extends through the top deposited film 10 and downward from the upper surface of the top deposited film to the upper surface of the next top deposited film 20, so that the upper surface of the tungsten plug 210 is exposed within the contact hole 100.
Fig. 2c corresponds to the step of forming the microfine pores by depositing the silica of fig. 1. As shown in fig. 2c, silicon dioxide is deposited into the contact hole 100, a silicon dioxide deposition layer 120 is formed on the sidewalls of the contact hole 100 and the upper surface of the exposed tungsten plug 210, and a microfine pore 200 having a smaller pore diameter is formed inside the contact hole 100, and the inner wall of the microfine pore 200 is the surface of the silicon dioxide deposition layer 120. In this step, the deposition method of silicon dioxide is low-temperature atomic layer deposition, the deposition temperature is 50 ℃, and a suitable low temperature can prevent the tungsten plug 210 located in the next-to-top deposited film 20 from being oxidized.
Fig. 2d corresponds to the step of fig. 1 of high temperature annealing the silicon dioxide deposition layer 120. As shown in fig. 2d, setting the temperature of the high temperature annealing to be near the deposition temperature of the adhesive material can minimize the amount of shrinkage of the silicon oxide deposition layer 120 in the step of depositing the adhesive layer while saving energy. The optimal deposition temperature of the bonding material is 550-650 ℃, so the optimal temperature range of high-temperature annealing is 550-650 ℃. In one specific embodiment, the high temperature anneal temperature and the deposition temperature are both 600 ℃.
Fig. 2e corresponds to the step of wet cleaning of fig. 1. As shown in fig. 2e, the silicon dioxide deposition layer 120 is removed by wet etching to remove the portion of the upper surface of the tungsten plug 210, so that the upper surface of the tungsten plug 210 is exposed again in the ultra fine hole 200.
Fig. 2f corresponds to the step of depositing the adhesive material of fig. 1. A bonding material is deposited by using a plasma enhanced chemical vapor deposition method, as shown in fig. 2f, and the bonding material is deposited on the surface of the remaining silica deposition layer of the microfine pore 200 and the upper surface of the tungsten plug 210, and a bonding layer 220 is formed on the inner wall of the microfine pore 200.
Fig. 2g corresponds to the step of depositing metallic tungsten of fig. 1. As shown in fig. 2g, the metal tungsten fills the remaining pores of the microfine pores, forming a microfine pore structure including the remaining silica deposition layer, the adhesive layer and the tungsten filling inside the top deposited film 10, which is bonded with the tungsten plugs 210 of the lower layer.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (3)
1. The preparation process of the superfine pore structure is characterized by comprising the following steps of:
providing a chip structure, wherein the chip structure comprises a substrate and a plurality of layers of deposition films sequentially deposited on the surface of the substrate, and a tungsten plug penetrating through the deposition films is arranged in the next top layer deposition film;
etching is carried out, a contact hole is formed in the top layer deposition film, the contact hole extends downwards from the upper surface of the top layer deposition film to the upper surface of the next top layer deposition film, and the upper surface of the tungsten plug is exposed in the contact hole;
depositing silicon dioxide into the contact hole, and forming a silicon dioxide deposition layer on the side wall of the contact hole and the upper surface of the tungsten plug so as to form a superfine hole;
carrying out high-temperature annealing on the silicon dioxide deposition layer;
wet cleaning is carried out, and a part of silicon dioxide deposition layer positioned on the upper surface of the tungsten plug in the superfine hole is removed, so that the upper surface of the tungsten plug is exposed in the superfine hole;
depositing a bonding material into the superfine hole, and forming a bonding layer on the surface of the residual silicon dioxide deposition layer on the inner wall of the superfine hole and the upper surface of the tungsten plug;
depositing tungsten into the superfine pores to fill the residual pores of the superfine pores with tungsten to form a superfine pore structure;
in the step of depositing the bonding material, the deposition temperature of the bonding material is 600 ℃, and the high-temperature annealing temperature is 600 ℃.
2. The manufacturing process according to claim 1,
in the step of depositing the silicon dioxide, the deposition method of the silicon dioxide is low-temperature atomic layer deposition.
3. The manufacturing process according to claim 2,
the deposition temperature of the silica was 50 ℃.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711140505.8A CN107994023B (en) | 2017-11-16 | 2017-11-16 | Process for preparing superfine pore structure |
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| CN201711140505.8A CN107994023B (en) | 2017-11-16 | 2017-11-16 | Process for preparing superfine pore structure |
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| CN107994023B true CN107994023B (en) | 2021-01-26 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080054701A (en) * | 2006-12-13 | 2008-06-19 | 주식회사 하이닉스반도체 | Method of manufacturing a metal line in semiconductor device |
| CN101719469A (en) * | 2009-11-10 | 2010-06-02 | 上海宏力半导体制造有限公司 | Method for manufacturing CVD silicon oxide capable of improving forming quality |
| CN101740545A (en) * | 2008-11-21 | 2010-06-16 | 三星电子株式会社 | Wiring structure of semiconductor device and method of forming a wiring structure |
| CN102339830A (en) * | 2010-07-15 | 2012-02-01 | 海力士半导体有限公司 | Semiconductor device and method for fabricating the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5705409A (en) * | 1995-09-28 | 1998-01-06 | Motorola Inc. | Method for forming trench transistor structure |
| JPWO2005027605A1 (en) * | 2003-09-09 | 2007-11-15 | Hoya株式会社 | Manufacturing method of double-sided wiring glass substrate |
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- 2017-11-16 CN CN201711140505.8A patent/CN107994023B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080054701A (en) * | 2006-12-13 | 2008-06-19 | 주식회사 하이닉스반도체 | Method of manufacturing a metal line in semiconductor device |
| CN101740545A (en) * | 2008-11-21 | 2010-06-16 | 三星电子株式会社 | Wiring structure of semiconductor device and method of forming a wiring structure |
| CN101719469A (en) * | 2009-11-10 | 2010-06-02 | 上海宏力半导体制造有限公司 | Method for manufacturing CVD silicon oxide capable of improving forming quality |
| CN102339830A (en) * | 2010-07-15 | 2012-02-01 | 海力士半导体有限公司 | Semiconductor device and method for fabricating the same |
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