TW200849515A - Heat dissipation type package structure and fabrication method thereof - Google Patents

Heat dissipation type package structure and fabrication method thereof Download PDF

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TW200849515A
TW200849515A TW096121275A TW96121275A TW200849515A TW 200849515 A TW200849515 A TW 200849515A TW 096121275 A TW096121275 A TW 096121275A TW 96121275 A TW96121275 A TW 96121275A TW 200849515 A TW200849515 A TW 200849515A
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Taiwan
Prior art keywords
heat
wafer
package structure
semiconductor
dissipating
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TW096121275A
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TWI343103B (en
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Min-Shun Hung
Ho-Yii Tsai
Chien-Ping Huang
Cheng-Hsu Hsiao
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Siliconware Precision Industries Co Ltd
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Priority to TW096121275A priority Critical patent/TWI343103B/zh
Priority to US12/157,831 priority patent/US8013436B2/en
Publication of TW200849515A publication Critical patent/TW200849515A/zh
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Publication of TWI343103B publication Critical patent/TWI343103B/zh
Priority to US13/195,617 priority patent/US8361843B2/en

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    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/732—Location after the connecting process
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

200849515 九、發明說明： 【發明所屬之技術領域】 本發明係有關 種得以供半導體晶 其製作方法。 【先前技術】 一種半導體封裝結構及其製法，尤指一 片有效散熱之散熱型半導體封裝=及 傳統半導體封裝件為避免内部之半 水塵污染，因此必須在半導體晶片上覆蓋一：麥：：外： 外界隔絕，惟構成該封裝膠體之封裝樹脂為一熱傳Z 差之材質，其熱導係數僅為〇.8w/m。κ， …、坐、 片=時產生之熱量無法有效藉該封裝膠體傳遞=晶 V致熱積存現象產生’使晶片性能及使驗 因為提高半導體封裝件之散熱效率，遂有於中 增6又散熱件之構想應運而生。 惟若散熱件亦為封裝膠體所完全包覆時，半導體晶片 量的散熱途徑仍須通過封裝膠體，散熱效果：提 升仍然有m無法符合散熱之需求，因而，為有 :晶：熱量，其-方式係使散熱件充分顯露出該封裝膠 膜轉 2方式係使半導體晶片之表面直接外露出封裳 以供半導體晶片產生之熱量得由外露於大氣中之 面直接逸散。 :茶閱第1A圖所示，美國專利第5,45〇,283號即揭示 壯接外路出半導體晶月表面之半導體封裝件，該半導 、牛1 〇如使半導體晶片之頂面外露出用以包覆該 110374 5 200849515 半導版曰日片u之封裝膠體14。由於該半導體晶片η之頂 面外露出封裝膠體14而直接與大氣接觸，故該半導體晶片 熱量得直接逸散至大氣中，其散熱途徑毋須通經 封衣恥體14，藉以增加散熱效率。 制、止明配合芬閱f 1Β圖’然而，該種半導體封裝件10在 存在有料之缺點。首先，該半導體晶片11黏接至 ί:體2lt，f置入封裝模具之模穴15中以進行形成該封 ^ 之核壓作業（Molding)時，須先將一朦片（Tape)13 ^於模穴15之頂壁上，俾使封裝模具合模後該半導體晶 得透過卿片13頂抵至模穴15之頂壁，以避 ，二广體晶片11之頂面上形成有溢膠(Flash);然而，若 晶片、11於基板12上之黏接高度控制不佳而導致 &導體？t導體晶片U之基板12的整體高度過低，使 ;2體曰曰片11之頂面未能透過該膠片Π有效地頂抵至 :二5 =頂壁’而於兩者間形成有間隙時，用以形成該封 衣膠脰14之料化合物即會溢膠於該半導體晶片η之頂 ::半;導體晶片11之頂面上形成有溢膠，除會影 二+ ¥心片11之散熱效率外’並會造成製成品之外觀 =良，故往往須予去膠(Deflash)之後處理；然而，是 種去膠處理不惟耗時，辦 θ加封衣成本，且亦會導致製成品 敕： ’若該黏接有該半導體晶片U之基板12的 過高，導㈣半導體W u透過該膠片Μ頂抵 曰片=二頁壁的力量過大，則往往會使質跪之該半導體 日曰片11因過度之壓力而裂損（Crack)〇 1】0374 6 200849515 同時，封裝模具之合模壓力仍會經由該膠片13傳遞至 該半導體晶片11，而造成該半導體晶片u之裂損，故令 封裝完成之製成品的良率無法有效提升，亦令其製造費用 難以降低。 、 蓥於丽述習知技術之缺失，美國專利第6,458,626號 (如弟2A至2C圖）、第M445498號（如第3圖）、以及第 6,699,731號（如第4圖）案（專利權人均同於本申請案之申 請人），係揭露一種可將散熱件直接黏置於半導體晶片上而 不會產生壓損晶片或溢膠問題，或可直接使半導體晶 面外露之半導體封裝件。 圖所不，該半導體封裝件乃在散熱件21欲外 路二％之表面上形成-與封裝膠體24間之接合性差 散熱件21直接黏— 裝膠…全包覆該散熱件以使封 裝膠…蓋於散熱件21之介及面=曰;如鳴 示)’如此，封裝模厂_所使二= 於半導體W 2G與散熱件 、和度乃大 模具不會觸及㈣件以使半=== 模後’ 損之虞，·接著，進行切割作 :又MV致裂 件2】上方之封裝膠體24去除，：二圖:斤不)，並將散熱 上之介面層25(例如為鍍金層)與散、m於散熱件21 於其與封裝膠體24間之 '、、、牛21間之黏結性大 該介面層25仍存留：：二將封裝膠體24剝除後， 、件21上，但因介面層25與封裝 110374 7 200849515 膠體24間之黏結性差，封裝膠體24不致殘留於介面層25 ，上（如第2C圖所示），故無溢膠之問題。相對地，當形成於 月欠元、件21上之介面層25(例如為聚亞癒胺樹脂製成之膠黏 片）舁政熱件21間之黏結性小於其與封裝膠體24間之黏結 ，時，將封裝膠體24剝除後，該介面層25會黏附於封^ 膠體24上而隨之去除（如第3圖所示），故該散熱件^上 亦不會形成溢膠。 • #或如第4 ®所示，該種半導體封裝件係於半導體晶 片上形成一附有介面層切之金屬材質的覆接片^， 同亥封衣膠體34之封裝化合物的熱膨脹係數不 導體)曰1 = 333的關係，使黏結性差之介面層333與該半 間的:面“及形成於該半導體晶片31周圍之封褒膠體34 =產生脫層，如此即可輕易地將該介面層切、覆 丰、及形成於該覆接片33上之封裝化合物340自咳 +蛤肢日日片31表面及形成於 ° 膠體34之声而y且干㈣日日片31周圍之封裝 之表面上輕易地撕除，使該半主 外露出封裝膠體34，以m BB表面能 由外露於大氣巾之表面賴Μ之熱量得 於該半導體θ # 3Ϊ > | 、放。且在模壓之過程中，由 亍♦體日日片31之表面係完全 此不會於半導體晶片31表 所覆接，因 進行任何去除#脒％ 、 乂壬何封裝化合物，故毋須 Ν云除W皿膠之後處理，而 外艰 成之半導體封裝件外觀之良好。 氏封衣成本並確保製 惟於前述之半導體封裝件 利半導體封裝業界實際操作應用。k ;尔續且成本高，不 ΠΟ374 8 200849515 :因此二何提供一種於封裝模屢製程時不致麼傷半導 二，時製程簡便且成本較低之散熱型封裝結構及製 法，貝、為目前亟待解決之課題。 【發明内容】 本發明之一目的在於 得以有效逸散半導體 鑒於以上所述習知技術之缺點 提供一種散熱型封裝結構及其製法 晶片運作時產生之熱量。 -法本:::再一目的在於提供—種散熱型封裝結構及其 *致於封裝模壓過程中壓傷半導體晶片。 本：明：另一目的在於提供—種散熱型封裝結構及其 衣法：侍以降低製程成本及簡化製程步驟。 法，揭：其它目的，本發明之散熱型封裝結構製 體曰t 至少一具相對主動面及非主動面之半導 性：接二ΓΛ導體晶片主動面透過覆晶方式接置並電 :連=曰片承載件上；於該晶片承載件上接置一散埶 严邻 件具有一散熱部、-自該散熱部向下延伸之支 於該散熱部之開孔，以供該散熱件藉由 二支按相料於該晶片承載件上，同時使該半導體 :置於該散熱部與該支撐部所構成之容置空間中，並^ 散熱部之開孔對應於該半導體晶片非主動二 封農模墨作業，以於該晶片方，進订 曰Η ;«與办μ 力不戰仟上形成一包覆該半導體 政熱件之封裝膠體；以及薄化該半導體晶片上方夕 封裝膠體，藉以外露出該半導體晶片非主動面及散教 面。该晶“載件係可㈣基板或㈣架型式。 、 110374 9 200849515 透過4述之製法，本發明亦揭霖一 構，係包括：晶片承载件’·半導體晶。广“:、㈣裝結 及非主動面，該半導體晶片係以 ：相對之主動面 至該晶片承載件上，·散熱件，具有置並電性連接 部向下延伸之支撐部、以及一形 I夂°卩、一自该散熱 供該散熱件藉由該支撐部而架樓於該==部之開孔，以 置於該散熱部與該 以 用以包覆該半導體晶片及散敎件 =曰曰片承载件上， 動面及散熱部頂面外露出該封裝膠體。4導體晶片非主 因此，本發明之散熱型封裝結 導體晶片以覆晶方式接著並電性連接法主要係將半 該晶片承载件上接置_具散熱部及自件，亚於 =的散熱件，其中該散熱部形成有:;:=之 構成之容置空間二，熱部與該支禮部所 片非主動面之上方，：著 於該半導體晶 ，散熱件的封裝膠體，並薄化該封裝;:該::體晶片， :片非主動面及散熱部頂面外露 =導體 =程成本及簡易製程方式製得二二 :導、J裝結構，同時本發明製程中係使娜：二― +導體晶片及散熱件 介 ㈣衣♦肢先覆盍 片及散熱件，避免 / 、衣骖肢以外露出半導體晶 避免於封裝㈣過程中屢傷半導體晶片。 110374 10 200849515 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式’熟習此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 [第一實施例] 請參閱第5A至5E圖，係為本發明之散熱型封裝結構 及其製法第一實施例之示意圖。 如第5A圖所示，提供至少一具相對主動面411及非 主動面412之半導體晶片41，以將該半導體晶片4〗接置 並電性連接於晶片承載件42上。該晶片承載板42係例如 為球柵陣列（BGA)基板或平面柵格陣列（LGA)基板，而該半 V組曰日片41係例如為覆晶式半導體晶片，且該覆晶式半導 體晶片係透過複數導電凸塊41G以將其主動面電性連接至 該晶片承载件42。 如第5B圖所示，於該晶片承載件上接 45該政熱件45具有一散熱部45卜一自該散熱部⑸向 下延伸之切部452、以及—形成於該散熱部451之開孔 4曰5 V ::該第—散熱件45藉由該支撐部452 *架撐於該 :4二盘：:2上，同時使該半導體晶片41容置於該散熱 體晶片4Ϊ1撐部452所構成之容置空間巾，並使該半導 ίϊΐ 45〇夕應於該散熱部451之開孔45〇位置。該散熱部 二二2係大於半導體晶片41平面尺寸，且該散熱 =又各向於該半導體晶片非主動面412高度。 弟5C圖所示’ *行封裝模壓作#，將該結合有半 110374 11 200849515 導體晶片41、散教件45沒曰ΰ '千及曰曰片承载件42之結構置入封壯 ，具之模穴中（未圖示）’以填入封裝樹腊，以後即^ 該封裝模具，俾於該晶片承载件42上形成 半 …散熱件45之封裝膠體44，其中由於;散： # 5lr^度略⑥於該半導體晶片非主動面4 ^免習知封㈣具直接_於半㈣晶片上而發生裂= 如第5D及5E圖所示’利用如研磨等薄化作業，以移 除覆蓋於該半導體晶月非主動 ^ 面412 1方之封裝膠體44 二^ 猎以使該+導體晶片非主動 面412及散熱件45之散敎部45〗了百；从+ b # 舣…°丨451頂面外露出該封裝膠體 ，、而提供半導體晶片41良好散熱途徑。 L ^刖述衣法，本發明復揭露一種散熱型封裝結構， 係包括有：晶片承載件42;半導體晶片41，具相對之主動 ^411及非主動面412,該半導體晶片4!係以其主動面411 接置亚電性連接至該晶片承載件42 _L ;散熱件45，係且 有一散熱部451、—自該散熱部451向下延伸之支撐部 452、以+及—形成於該散熱部451之開孔㈣，以供該散熱 :45藉由5玄支撐部452而架撐於該晶片承載件42上，同 才使該半導體晶片41容置於該散熱部45 1與該支樓部452 二構成之#置空間中，且該散熱部451頂面高度係與該半 非主動面南度相等；以及封裝膠體44，係形 :於該晶片承载件42上，用以包覆該半導體晶片41及散 …、 且使ϋ玄半導體晶片41非主動面及散熱部45 1頂 110374 12 200849515 '面外露出該封裝膠體44，如此即可使該半導體晶片4ι有 •效逸散其運作時所產生之熱量至外界。 [第二實施例] 請參閱第6圖，係為本發明之散熱型封裳結構第二择 意圖。如圖所示，本實施例之散熱型封裝結構： ”則述貫施例大致相同，其主要差異係在移除位於半導體 二？之封裝膠體後，復於外露出該封裳膠體54之散 :、:頂面上塗佈-如油墨㈣之保護層56,以防止兮 散熱部551之氧化。 丨方止3 ΠΙ此，本發明之散熱型封裝結構 方式接著並電性連接至晶 支推部的散埶:接f中:::部及自該散熱部向下延伸之 之開孔，以熱部形成有對應於半導體晶月 構成之容置空間中，U與該支撐部所 U . . . ^ D亥放熱部之開孔對應於該半導體曰 片非主動面之上方，接著形 /牛¥版曰日 該散熱件的封裝膠體 已復該半導體晶片及 晶片非主動面及散教部項面：封裝膠體，俾使該半導體 透過低製程成本及簡易紫 封衣骖脰，如此即可 散熱型封裝結構，同Β士：恭式衣得外露出半導體晶片之 半導體晶片及散熱件，了 ί明製程中係使封裝谬體先覆蓋 片及散熱件，避免於封裝;m膠體以外露出半導體晶 上述實施例僅例示性 中壓傷半導體晶片。 非用於限制本發明。卢^本每明之原理及其功效，而 ^ ^锊別注意者，係該晶片承载件 110374 13 200849515 之遙擇，以及晶片與B y $ 任何熟習此項技藝之人士 、件之1性連接方式之採用， 疇下，對上述實施例進行修：：：：背本發明之精神及範 利保護範圍，應如後述之卜直、？變。因此’本發明之權 【圖式簡單說明】 ^專㈣圍所列。 第1A及1B圖係為美 半導體封裝件剖面示意圖 苐2A至2C圖係為美 半導體封裝件剖面示意圖 國專利第5,450,283號所揭露 國專利第6,458,626號所揭露 之 之 第3圖係為美國專利第6,444,498號所揭露之半導體 封裝件剖面示意圖； 第4圖係為美國專利第6,699,731號所揭露之半導體 封裝件剖面示意圖； ^ 第5八至5E圖係為本發明之散熱型封裝結構及其製法 第一實施例之示意圖；以及 第6圖係為本發明之散熱型封裝結構第二實施例之示 意圖。 【主 要元件符號說明 10 半導體封裝件 12 基板 14 封装膠體 20 半導體晶片 23 基板 25 介面層 11 半導體晶片 13 膠片 15 模穴 21 散熱件 24 封裝膠體 31 半導體晶片 14 110374 200849515 333 介面層 33 覆接片 34 封裝膠體 41 半導體晶片 410 導電凸塊 411 主動面 412 非主動面 42 晶片承載件 44 封裝膠體 45 散熱件 450 開孔 451 散熱部 452 支撐部 51 半導體晶片 54 封裝膠體 551 散熱部 56 保護層 15 110374

Claims (1)

  1. 200849515 十、申凊專利範圍： .1. -㈣熱型封裝結構製法，係包括： 提仏至）一具相對主動面及非主動面之半導體晶 垃以將該半導體晶片主動面透過覆晶方式接置並電性 連接於晶片承载件上； 邱敘都該曰曰片承载件上接置一散熱件，該散熱件具有-二；埒挪立自δ玄散熱部向下延伸之支撐部、以及-形成 於=1 之開孔’以供該散熱件藉由該支稽部而架撐 部成同半導體晶片容置於繼 冓成之备置空間中，並使該散熱部之開 孔對應於科導體晶片非主動面之上方； 覆兮拉壓作業’以於該晶片承載件上形成-包 後斜％體晶片及散熱件之封裂膠體；以及 薄化該半導辦S y u + 半導體曰.Π 封農膠體，藉以外露出該 牛蜍體M片非主動面及散熱部頂面。 2. 範圍第1項之散熱型封裝結構製法，其中， 5亥曰曰片承载件為基板及導線架之其中一者。 乾圍第1項之散熱型封裝結構製法，其中， 敎)基板*平祕陣列 4·:Π:?ίΓ/項之散熱型封裂結構製法，其中， =:片糸透過複數導電凸塊以將其主動面電性 埂接至该晶片承載件。 5.如申請專利範圍第1項之散熱型封裝結構製法，其中， 110374 16 200849515 vr=開孔之尺寸係大於半導體晶片平面尺寸。 ..丄::⑽第1項之散熱型封裝結構製法，其中， 業係利用研磨技術移除覆蓋於該半導體晶片 非主動面上方之封裝膠體。 7.如!請專利範圍第6項之散熱型封裝結構製法，其中， 5玄缚化作業中亦同時研磨掉部分散熱部。 .8.2^利範圍第1項之散熱型封裝結構製法，復包括 、“路出該封裝膠體之散熱部頂面塗佈—伴蠖層。 9·如申請專利銘图楚Q g μι μ 散熱型封裝結構製法，其中， 該保護層為油墨（ink)。 10.一種散熱型封裝結構，係包括： 晶片承載件； 半導體晶片，呈相盤夕± 體晶片係以m 非主動面，該半導 上；’、 動面接置並電性連接至該晶片承載件 .主浐：熱件，具有一散熱部、-自該散熱部向下延伸之 _藉由該支撐部而架樓於二=孔’以供該散熱件 體曰片^w 承载件上’同時使該半導 日日谷；^散熱部與該支撐部所構成之容置空 高度相等；以及頁面回度係與該半導體晶片非主動面 封衣膠體’係形成於該晶 半導體晶片及散孰件W仵用以包覆该 熱部頂面外露出該封裝膠體。 動面及欢 110374 17 200849515 11 ·如申清專利範圍笛 ，晶片承載件==項之散熱型封裝結構，其中，該 干马基板及導線架之其中一者。 12. 如申請專利範圍第 曰 ㈤弟10項之散熱型封裝結構，其中，該 日日月承載板為球栅陳 Ο基板之其令=車列（BGA)基板及平面柵格陣列 13. 如申請專利範圍第1〇 貝之放熱型封叙結構，其中，該 牛¥體日日片係透過複數導+几 V屯凸塊以將其主動面電性連 接至6亥晶片承載件。 14. 如申請專利範圍第1〇 貝之放熱型封裝結構，其中，該 政：二開孔之尺寸係大於半導體晶片平面尺寸。 15·如申凊專利範圍第 一β y 、之放熱型封裝結構，復包括有 ^s，係形成於外露出該封 1 6 ‘由咬⑦η Λ 3了衣修體之散熱部頂面。 ::;:=5項，㈣裝結構，其中，該 110374 18
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