TW200832537A - Semiconductor wafer, and semiconductor device manufacturing method using the wafer - Google Patents

Semiconductor wafer, and semiconductor device manufacturing method using the wafer Download PDF

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Publication number
TW200832537A
TW200832537A TW096146071A TW96146071A TW200832537A TW 200832537 A TW200832537 A TW 200832537A TW 096146071 A TW096146071 A TW 096146071A TW 96146071 A TW96146071 A TW 96146071A TW 200832537 A TW200832537 A TW 200832537A
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TW
Taiwan
Prior art keywords
semiconductor wafer
identification
semiconductor
wafer
semiconductor device
Prior art date
Application number
TW096146071A
Other languages
Chinese (zh)
Inventor
Shigeo Masai
Original Assignee
Matsushita Electric Ind Co Ltd
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Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Publication of TW200832537A publication Critical patent/TW200832537A/en

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

To raise a manufacturing yield by reducing the misalignment of a dicing position when a semiconductor chip is to be made fine. The position detection of the chip after diced is ensured to improve a pickup efficiency. The semiconductor wafer is characterized by including such a recognizing target for each semiconductor device forming region (or chip) as can be detected by at least one optical detecting means, so that the position on the semiconductor wafer can be recognized from the position of the recognizing target.

Description

200832537 九、發明說明： 【發明所屬之技術領域】 、本發明有關於半導體晶圓，及制其之半導體裝置之製 有關於在半導體製造步驟中之半導體晶圓之 :置辨識技術，例如，有關於在晶圓之切割（dici⑻步驟 中辨識曰曰;：之位置，或在切片步驟後之半導體晶片撿拾 (pickup)步驟令，用來辨識晶片之位置之技雜。 【先前技術】 上在：：體裝置之製造時’所採用之方法是在半導體晶圓 ::乳化步驟、電極形成步驟、雜質擴散步驟等，一 件，對其進行切割，撿拾利用切割而分割 广加半導體晶片’將其組震到引線桓架⑽ me或框木载體（frame carHer)等之组裝構件。 一在=種半導體裝置之製造步驟中，切割技術如圖⑴斤 二'，「用：方法是預先在半導體晶圓1之表面外周部之 ta =域（多餘區域)开…自之辨識… χγ 久_ 3、4、5’亚且在通過晶圓1之大致中心之 谁-/J1配置2個’經由光學式檢測該辨翻標把，而 進仃位置檢測，藉以決定切割線。 個之辨識用標把2、3、4、5形成在半導體晶 用光學伽手段，例如光學顯微鏡，檢 你u :丄一後在切㈣’百先，利用光學式檢測手段， 例如在光學顯微鏡之位置對準點〇，檢測標乾2、3、4、5。 依照檢測到之餘之位置和顯微鏡之位置對準㈣之相 312ΧΡ/發明說明書(補件)/97-02/96146071 5 200832537 對位置關係，辨識半導體晶圓1之基準位置。因為可以明 確地檢測半導體晶圓1之辨識用標靶2、3、4、5，所以 不冒產生半導體晶圓1之基準位置之錯誤辨識，可以正確 地辨識半導體晶圓1之位置（專利文獻1)。 • 然後，在切割完成後，當一個一個地撿拾被貼著固定在 -擴展薄片（exPand sheet)上之多個之半導體晶片6之情況 時’採用以下之步驟。首先，在步驟丨··決定最初撿拾之 φ半=體晶片6，對與該位置對應之彈性夾（collet)(把持 手段）進行定位，利用彈性夾進行該半導體晶片6之撿 拾。在步驟2 ··在撿拾後使彈性夾移動預先決定之指定間 距部份。在步驟3:在該位置進行半導體晶片6之圖案辨 識，修正彈性夾之位置使其對準在實際之半導體晶片6之 位置。在步驟4:在進行對應之半導體晶片6之撿拾之後， 回到步驟2而重複進行該動作。關於步驟丨之半導體晶片 之撿拾，獲得半導體晶片之最外部之3點之位置資訊，根 ⑩據其而預測半導體晶片存在之位置，根據該預測決定彈性 夾之把持手段對各個半導體晶片之位置（專利文獻2)。 • [專利文獻1]曰本專利特開平6-120322號公報 •[專利文獻2]日本專利特開平3-180050號公報 【發明内容】 (發明所欲解決之問題） 在此種之半導體製造之切割技術和半導體製造之撿拾 方法中，形成在半導體晶圓内之晶片在lmm平方以下之小 晶片時有可能使生產效率降低。 312XP/發明說明書(補件)/97-02/96146071 6 200832537 小^片在切割步驟時，為能分割成為多個之半導體晶 呼半導晶31之切割次數增加。例如，在u -方向，例如X軸= 半導體晶片時，在同 向而要300次以上之切割步驟。 導：==割方法中’利用預先4個之標㈣識半 辨識半導體晶圓位置係對小晶片以外 t ，但疋在小晶片於同-方向例如X軸方向之12 :+導體晶圓之情況，成為進行300次之刀片發送 位。當切割刀片位置誤差為〇.2心，_次之2 = 有可能產生60Am之等差。桌么…， 之刀片發达便 下所形成之半導體晶圓時^ J線之幅度為6—以 μ ^ ® ^ Μ#"1之位置誤差不是切斷切 :線:：是會造成切斷電晶體或電阻，半導體』電I; 題。 裝置等之製入區域（以下稱為電路區域）之問 個種^1晶/1 在12对半導體晶圓内形成有7〇_ 们曰曰片以上。在上述專利文獻2之技術中，獲得夂 體晶片之最外部之3點之位置 ^蛤 片之存在位置，根據該預測決定彈性央之： ;導，r置。在上述方法中，對於二:=: 片，大多之情況對各個半導體晶片之定位需 日日 會使生產效率降低為其問題。 又τ日1，將 士另外’為缺S生產效率騎半導體晶h %，擴展薄片之擴張狀態在半導體晶圓内為不均—頁測 由於周圍溫度，薄片之品質等，薄片經常不會再現： 312XP/發明說明書(補件)/97-〇2/96146071 7 200832537 =伸展在此種情況，因為會產生晶片和晶 異，所，會杨拾不良品，和使半導體晶片殘留== 此=題隨者晶片之微細化之進展，成為極深刻之問題。 發明針對上述之問題，其目的是即使 、 之微細化使切割次數增大時，亦可以減小=== 偏移’可以達成高良率化。 位置之位置 另外’本發明之目的是確實地進行切㈣ 之位置檢測，藉以提高撿拾效率。 B曰片 (解決問題之手段） 用以解決上ϋ問題之本發明之半導體晶圓其特徵 =定數之（半導體裝置形成區域）晶片之每—個，具備有 】用至少1個以上之光學式檢測手段而可以進行檢測之 辨硪用標革巴，依照上述辨識用標鞋之位置可以 晶圓之位置。 T守版 另外，在本發明之半導體晶圓之製造方法中，其特徵在 於利用光學式檢測手段經由檢測上述辨識用標靶i位 ，，而用來辨識半導體裝置形成區域（晶片）位置，藉以提 尚生產效率，並且防止撿拾不良品和防止晶片殘留。 曾亦即，本發明是一種半導體晶圓，被晝定成為多個之半 導體裝置形成區域；其特徵在於··在上述半導體晶圓表面 之指定數之上述半導體裝置形成區域之每一個，具備有至 少一個之辨識用標靶；上述辨識用標靶可以利用光學式檢 测手段檢測，並根據該檢測到之位置可以辨識半導體晶圓 上之位置。 Ba胃 312沿/發明麵書(補件)/97-02/96146071 8 200832537 時’在半導體晶圓内之指定數之半導體襄 域之每一個，具備有利用1個之光學式檢測手 段而可以進行檢測之辨識用標把，所以經由檢測辨識用標 靶之位置’可以辨識半導體裝置形成區域亦即晶片位置。 因此丄即使擴展薄片之擴張狀態在半導體晶圓内成為 二：由於周圍溫度，薄片之品質等’使薄 產 ^變f之情料，亦可以指定各個半導體裝置形成區域 .以可以防止撿拾不良品和產生晶片殘留。 一 另外’在本發明巾其㈣在於在上料導體晶 辨識用標乾在每一個之半導體裝置形成區域，至少 個0 直1 ^照此種構造時，因為可以指定各個之半 區域，所以可以避免上述不良品之檢拾，可 = 進行組裝。 人男双手地 包卜半在導tr/在上述半導體晶圓使上述辨識用標乾 i包3以+導體處理之最上佈線層所形成者。 依照此種構造時’不會使工時增大 ，容易地形成。另外，假如成為形成在元= =部份時’不論佔用面積如何，都可以不使工時增大: 另外，在本發明中在上述半導體晶圓更包含在指定 二導體裝置形成區域之每一個，具傷形成有i個之辨識用 “乾之虛擬半導體裝置形成區域（座擬晶片）。 5 依照此種構糾，在指枝之半導體裝置形成區域之每 312XP/發明說明書(補件)/97-02/96146071 9 200832537 -個，形成具有作為辨識用半導體I置形成區域之辨識用 標革巴之虛擬半導體裝置形成區域，藉而可以用來以更高之 可靠度進行位置辨識，以該辨識用標乾作為基準= 導體裝置形成區域配置，可以奸撼今址 罝7以根據該被圮憶之資料決定不 良之半v體裝置形成區域位置。 另外，在本發明中在上述半導體晶圓包含在上述辨識用 標靶之上層，保護膜被除去。 依照此種構造時，辨識用標把之光學式辨識成為更確 實0 另外，在本發明中在上述半導體晶圓包含上述 聚醯亞胺（polyimide)膜。 ’、”、為 另外，在本發明中在上述半導體晶圓包含上述辨識用標 靶形成在與上述半導體裝置形成區域之周緣相當之區域: 依照此種構造時，經由在與容易產生大幅之位置偏移之 半導體裝置形成區域周緣相當之區域，形成辨識用標革巴， ⑩可以用來進行更高精確度之定位。 另外，在本發明中在上述半導體晶圓包含上述辨識用標 革巴被配置在襯塾之近旁。 依照此種構造時，在組裝時可以有效地提高位置精確 度0 另外，在本發明中在上述半導體晶圓包含上述辨識用標 靶在襯墊或襯墊近旁由構成上述襯墊之材料之圖案所構 成。 Μ 依照此種構造當組裝時，除了可以有效地提高位置精確 312XP/發明說明書(補件)/97-02/96146071 10 200832537 f外彳以僅在襯墊之圖案製作步驟以變更光 二另外例如利用在襯墊之圖案形成中空圖宰之方法，‘ : g)時’使熔融金屬等流入該成為中空圖荦之巴 域’可以用來進行連接而不會使電氣連图= 造成電阻之增大。 降低’亦不會 在本么日月中在上述半導體晶圓上 含使含有概塾上之帶狀之保護膜除去區域。識用^包 =此種構造時，可以使辨識成為容易而且高可靠度。 入你/々在^明中在上述半導體晶圓上述辨識用標祀包 3使在母-個之半導體裝置形成區域成為不同，以可以個 別辨識之方式所形成。 依照此種構造時’經由在辨識用標輕分配號碼等，附加 ，有之名稱’可以個別辨識。因此經由將不良品或臨限電 壓貧料等與號碼一起記憶，可以不會錯誤地確實組裝。 另外在本U中在上述半導體晶圓上述辨識用標乾包 含在同一線上至少設置有2個。 依照此種構造時，因為在同一線上設置2個之辨識用標 革巴’所以偏移之檢測變為容易。 另外，在本發明中在上料導體晶B1上述辨翻標把包 含在每一線，隔開指定之間隔設置至少有2個。 依,、、、此種構4 ，因為在每一線設置2個之辨識用標 乾’所以除了線方向之偏移外，角度之偏移檢測亦變為容 易0 312XP/發明說明書(補件)/97-02/96146071 200832537 人另外S本發明中在上述半導體晶圓上述辨識用標乾包 /、有/、上述晶片之切割線相當之線平行之邊之矩形圖 案。 、^照此種構造時，矩形圖案因為不容易產生圖案劣化所 以有效，具有偏移之檢測亦變為容易之效果。 另外在本發明中構成用以實現上述半導體晶圓之 罩。 ^ 依照此種構造時，經由在光罩附加辨識用圖案，不需要 用寸別之步驟，利用通常之步驟就可以容易地形成辨識 :卜圖在案本發明中在上述光罩包含在"具備有1個之 圖：照此種構造時’經由在1片之光罩形成1個之辨識用 可以在與丨片之光罩對應之指定數之半導體裝置形 士區域之每-個，附加辨識用圖案，包含是否良 疋’可以使組裝作業成為更容易。 开本發明中在上述光罩包含在與各個半導體裝置 4&域對應之每一個，具備有j個之辨識用圖案。 依照此種構造時，可以在半導體裝置形成區域之每一個 :、加固有之號碼等之識別號碼，包含是否良好之判定，可 以使組裝作業成為更容易。 導=卜番在本發明中在上述光罩更包含與指定數之各個半 开成區域對應之1個，具備有涵蓋該半導體裝置 屯成S域全面之辨識用虛擬圖案。 312XP/發明說明書(補件)/97·02/96146071 12 200832537 依照此種構造時，因為在丨片光罩且 識用虛擬圖案，所以可以容易地形成^ 至少1個之辨 用標乾’亦即虛擬半導體裝置形成區域可^之辨識 體晶圓。 虛极日日片）之半導 制迭方、广$月疋使用有上述半導體晶81之半導體裝置之 ^方法，在將上述半導體晶圓分割成為 纽域對應之各個晶片之_步驟，包含有200832537 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor wafer, and a semiconductor device therefor, relating to a semiconductor wafer in a semiconductor manufacturing step: for example, Regarding the cutting of the wafer (identification of 曰曰; in the step of dici (8); or the semiconductor wafer picking step after the dicing step, the technique for identifying the position of the wafer. [Prior Art] The method used in the manufacture of the body device is a semiconductor wafer: an emulsification step, an electrode forming step, an impurity diffusion step, etc., one of which is cut, and the semiconductor wafer is cut and cut by cutting. The group is struck to an assembly member such as a lead truss (10) me or a frame car carrier (frame carHer). In the manufacturing step of the semiconductor device, the cutting technique is as shown in Fig. 1 (1), and the method is pre- The ta = domain (excess area) of the outer peripheral portion of the surface of the semiconductor wafer 1 is opened... from the identification... χ γ long _ 3, 4, 5' sub-and at the approximate center of the wafer 1 - / J1 configuration 2 'Through optical detection of the identification of the target, and the position detection, to determine the cutting line. Identification of the indicators 2, 3, 4, 5 formed in the semiconductor crystal optical means, such as optical microscope, check you u: After cutting (4) '100 first, use optical detection means, for example, at the position of the optical microscope to align the point 〇, detect the standard 2, 3, 4, 5. According to the detected position and the position of the microscope Alignment (4) phase 312 ΧΡ / invention manual (supplement) /97-02/96146071 5 200832537 For the positional relationship, identify the reference position of the semiconductor wafer 1. Since the identification target 2 of the semiconductor wafer 1 can be unambiguously detected 3, 4, and 5, the position of the semiconductor wafer 1 can be correctly recognized without erroneous recognition of the reference position of the semiconductor wafer 1 (Patent Document 1). Then, after the cutting is completed, pick up one by one. In the case where a plurality of semiconductor wafers 6 fixed on an exPand sheet are attached, the following steps are employed. First, in step 丨, the first φ half = body wafer 6 is selected, and Location pair The elastic clip (holding means) is positioned, and the semiconductor wafer 6 is picked up by the elastic clip. In step 2, the elastic clip is moved by a predetermined pitch portion after picking up. In step 3: This position performs pattern recognition of the semiconductor wafer 6, and corrects the position of the elastic clip to be aligned with the actual semiconductor wafer 6. In step 4: after picking up the corresponding semiconductor wafer 6, returning to step 2 and repeating In the process of picking up the semiconductor wafer of the step, the position information of the outermost three points of the semiconductor wafer is obtained, and the root 10 predicts the position where the semiconductor wafer exists, and the holding means of the elastic clip is determined according to the prediction for each semiconductor wafer. Position (Patent Document 2). [Patent Document 1] Japanese Laid-Open Patent Publication No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. In the cutting technology and the semiconductor manufacturing method, it is possible to reduce the production efficiency when the wafer formed in the semiconductor wafer is small wafers of 1 mm square or less. 312XP/Invention Manual (Supplement)/97-02/96146071 6 200832537 In the cutting step, the number of times of cutting for the semiconductor wafer semi-conductive crystal 31 which can be divided into a plurality of pieces is increased. For example, in the u-direction, for example, the X-axis = semiconductor wafer, the cutting step is 300 times or more in the same direction. Guide:==Cutting method 'Using the pre-four standard (four) to identify the semiconductor wafer position is outside the small wafer t, but in the small-chip in the same direction, such as the X-axis direction of 12: + conductor wafer In the case, it becomes the blade transmission bit for 300 times. When the cutting blade position error is 〇.2 heart, _ second 2 = it is possible to produce an equivalent of 60Am. Table?... When the blade is developed under the semiconductor wafer, the amplitude of the J line is 6—to μ ^ ® ^ Μ#"1 The position error is not cut off: Line:: It will cause cutting Broken transistor or resistor, semiconductor 』I; In the manufacturing area of the device or the like (hereinafter referred to as a circuit region), a single crystal/1 is formed in the semiconductor wafer of 12 pairs or more. In the technique of Patent Document 2, the position of the outermost three points of the dies wafer is obtained, and the position of the slab is determined. According to the prediction, the elastic state is determined: In the above method, for the two:=: film, in many cases, the positioning of each semiconductor wafer requires daily production to be reduced. In addition, τ 日1, 士士 additional 'seats the semiconductor crystal h% for the production efficiency of the lack of S, and the expanded state of the expanded sheet is uneven in the semiconductor wafer. The sheet is often not reproduced due to the ambient temperature, the quality of the sheet, etc. 312XP/Invention Manual (supplement)/97-〇2/96146071 7 200832537=Extension in this case, because wafers and crystals will be generated, which will pick up defective products and make semiconductor wafers remain == this = The progress of the miniaturization of the chip has become a very profound problem. The present invention has been made in view of the above problems, and an object thereof is to achieve a high yield by reducing the number of cuts even when the number of cuts is increased. Position of the position Further, the object of the present invention is to reliably perform the position detection of the cut (four), thereby improving the picking efficiency. B 曰 ( 手段 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The detection means can be used for the detection of the target, and the position of the wafer can be determined according to the position of the identification shoe. In addition, in the method of manufacturing a semiconductor wafer according to the present invention, the optical detecting means detects the position of the semiconductor device forming region (wafer) by detecting the target i-bit of the identification. Improve production efficiency and prevent picking up defective products and prevent wafer sticking. In the present invention, a semiconductor wafer is defined as a plurality of semiconductor device forming regions, and each of the semiconductor device forming regions having a predetermined number of semiconductor wafer surfaces is provided. At least one identification target; the identification target can be detected by an optical detection means, and the position on the semiconductor wafer can be identified based on the detected position. Ba stomach 312 edge / invention book (supplement) / 97-02 / 96146071 8 200832537 - each of the semiconductor fields specified in the semiconductor wafer, with one optical detection means Since the identification target for detection is performed, the semiconductor device formation region, that is, the wafer position, can be identified by detecting the position of the identification target. Therefore, even if the expanded state of the expanded sheet becomes two in the semiconductor wafer: it is possible to specify the area in which each semiconductor device is formed due to the surrounding temperature, the quality of the sheet, etc., so as to prevent picking up defective products. And produce wafer residue. A further 'in the present invention, the fourth (4) is that in the semiconductor device forming region of the feeding conductor crystal identification, at least 0 straight 1 ^ according to this configuration, since each half region can be specified, To avoid the above-mentioned defective products, you can = assemble. The male and the female hands are half-turned on the semiconductor wafer, and the above-mentioned semiconductor wafer is formed by the uppermost wiring layer treated by the + conductor. According to this configuration, 'the work time is not increased, and it is easily formed. In addition, if it is formed in the element == part, the working time may not be increased regardless of the occupied area: In addition, in the present invention, the semiconductor wafer is further included in each of the designated two-conductor device forming regions. In the form of a flaw, there is a "dry virtual semiconductor device forming region (seat wafer)." According to this configuration, every 312XP/invention specification (supplement) in the semiconductor device forming region of the finger 97-02/96146071 9 200832537, forming a virtual semiconductor device forming region having an identification target for forming a region for identifying the semiconductor I, thereby being used for position recognition with higher reliability, The identification using the stem as the reference = the conductor device forming region configuration, can be smashed to the present site 以 7 to determine the defective half-v body device forming region position based on the recalled data. Further, in the present invention, the above semiconductor wafer Included in the upper layer of the above-mentioned identification target, the protective film is removed. According to this configuration, the optical identification of the identification target becomes more certain. In addition, in the present invention The semiconductor wafer includes the polyimide film. In the present invention, the semiconductor wafer includes the identification target formed on a periphery of the semiconductor device formation region. Area: According to this configuration, the identification standard bag 10 can be formed in a region corresponding to the periphery of the semiconductor device forming region where the large positional displacement is likely to occur, and the positioning can be performed for higher accuracy. Further, in the invention, the semiconductor wafer includes the identification mark bar disposed in the vicinity of the lining. According to this configuration, the positional accuracy can be effectively improved at the time of assembly. In addition, in the present invention, the semiconductor wafer includes the pattern of the material for constituting the spacer in the vicinity of the spacer or the spacer. Composition.依照 In accordance with this configuration, when assembled, in addition to effectively improving the positional accuracy 312XP / invention manual (supplement) / 97-02 / 96146071 10 200832537 f 彳 彳 彳 衬垫 衬垫 衬垫 衬垫 衬垫 衬垫 衬垫 衬垫 衬垫 衬垫 衬垫 衬垫 衬垫 衬垫 衬垫 衬垫 衬垫 衬垫 衬垫In the method of forming a hollow pattern in the pattern of the liner, ':g) 'flowing molten metal or the like into the hollow domain' can be used for connection without causing electrical connection diagram = causing an increase in resistance . The reduction is also not required to include a protective film removal region on the semiconductor wafer in the present day and the month. Knowing the package = This type of construction makes identification easy and highly reliable. In the above-mentioned semiconductor wafer, the identification label package 3 is made different in the semiconductor device forming region, and can be formed separately. According to this configuration, the name "additional, and the name" can be individually identified by assigning a number or the like to the identification mark. Therefore, it is possible to reliably assemble without erroneously storing the defective product or the threshold voltage and the like together with the number. Further, in the present invention, at least two of the above-described identification wafers for the semiconductor wafer are provided on the same line. According to this configuration, since two identification stamps are provided on the same line, the detection of the offset becomes easy. Further, in the present invention, the above-mentioned discrimination target is included in each of the upper conductor crystals B1, and at least two are provided at intervals of a predetermined interval. According to , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , /97-02/96146071 200832537 In the present invention, the above-described semiconductor wafer has a rectangular pattern in which the identification dry package/there is a parallel line to the line corresponding to the cutting line of the wafer. According to this configuration, the rectangular pattern is effective because it is less likely to cause pattern deterioration, and the detection of the offset becomes easy. Further, in the present invention, a cover for realizing the above semiconductor wafer is constructed. ^ According to this configuration, by attaching the identification pattern to the photomask, it is not necessary to use the step of the inch, and the identification can be easily formed by the usual steps: in the present invention, the mask is included in the " There is one of the figures: in the case of such a structure, the identification of one of the masks by one sheet can be added to each of the specified number of semiconductor device shapes corresponding to the mask of the wafer. The identification pattern, including whether it is good or not, can make assembly work easier. In the present invention, each of the photomasks included in each of the semiconductor device 4& fields is provided with j identification patterns. According to this configuration, it is possible to make the assembly work easier in the identification number of each of the semiconductor device forming regions: the number of the reinforcement, and the like, including whether or not the determination is good. In the present invention, the photomask further includes one corresponding to each of the half-opening regions of the designated number, and includes a virtual pattern for identification covering the entire S-domain of the semiconductor device. 312XP/Invention Manual (Supplement)/97·02/96146071 12 200832537 According to this configuration, since the reticle reticle and the virtual pattern are recognized, it is possible to easily form at least one of the identification stems. That is, the virtual semiconductor device forming region can identify the body wafer. The method of dividing the semiconductor wafer into the respective wafers corresponding to the new field, using the method of using the semiconductor device of the semiconductor crystal 81 described above, includes the method of dividing the semiconductor wafer by the semiconductor device of the semiconductor crystal 81

識;標—依照上述辨識嶋 、、泉之V驟，和依照上述切割線進行切割之步驟。 /依…、此種構造日守，因為以光學式檢測辨識用標#，並進 可以減小位置偏移，並且可叫 、、另外，本發明是在上述半導體裝置之製造方法中，在上 述切別步驟將半導體晶圓分割成為與半導體裝置形成區 域^應之各個之晶片，撿拾該半導體晶圓之步驟包含··以 ⑩光學式檢測上述辨識用標靶之步驟；和依照上述辨識用標 乾決定撿拾位置之步驟。 _ 依照此種構造時，因為依照光學式檢測結果進行撿拾， 所以可以容易地進行確實之組裝。 另外’本發明是在上述半導體裝置之製造方法中，上述 辨識用標靶被構建成可以識別每一個晶片，在檢查步驟 (對每一個晶片進行檢查），記憶步驟（將檢查結果和各個 辨識用標靶一起記憶在記憶器），和撿拾步驟（用來撿拾在 上述切割步驟被分割成為各個晶片之半導體晶圓）包含有 312XP/發明說明書(補件)/97-02/96146071 13 200832537 述記憶器避開在上述檢查步驟檢查為不合格之晶片 而進行撿拾之步驟。 :照此種構造時’不會組裝不良品而可以確實地組裝。 面、工由在半$體1置形成區域之每—個附加號碼等之 ^之識別圖案，將以檢查㈣所獲得之檢查結果記憶在 4器’可以依照晶片之特性進行分組等，可以實現適當 之使用用途，可以謀求提高良率。 (發明效果） ，照上述半㈣晶圓時，因為可以明確韻形成在半導 肢曰曰圓表面上之辨識用_’所以在半導體製造之切割步 糾，於辨識半導體晶圓位置時不會辨識錯誤，而可以實 現南精確度之㈣。另外’在半㈣製造之撿拾步驟時、， 可以明確地辨識該辨識用標靶’所以可以辨識晶片位置， 谋求提兩生產效率’並且防止撿拾不良品和晶片殘留。 【實施方式】 下面參照圖式用來詳細地說明本發明之實施形能。 (實施形態1) ' ~ 圖i表示亡發明之實施形態i之半導體晶圓，在盘圖 13所示之先前技術例半導體晶圓之同等部份附加、 符號。 在本實施形態中其特徵在於在半導體晶圓1内形 多個之半導體裝置形成區域（晶片）6，在每一個之該半耸 體裝置形成區域’形成有辨識用標靶7。在該半導：曰： 丨之每一個半導體裝置形成區域6製入有電路區域’：： 312XP/發明說明書(補件)/97-〇2/9似咖1 η 200832537 個半導體裝置形成區 造處理之形成芒k 辨識用7’係於半導體製 等之辨識用層:蹲^ 案梦作Β± 在半導體晶圓之製造時之佈線層之圖 半導體：圓内用作為佈線用光罩而製作。該等之標靶7在 1體日日®内之χγ轴被配置成具有相同之間隔。 外’辨識用標革巴7夕士 f曰此^ 度即可。 乾7之大小取好較大’只要有50"程 在^ ^明使用上述辨識用標乾7辨識半導體晶圓1之 位置之方法。另外，裝置半導體晶圓1之切 以在χγ方向移動外，亦被構建成可以旋轉。 切為光學式檢測手段之對物顯微鏡，同時使上述 之χΓη月向Π方向移動，並配置成使在半導體晶圓1 所配置餘7a之右下端位於對物顯微鏡之位置 對準點0。 其次’從該狀態使切斷台8在x軸方向和Y軸方向移 朗物顯㈣之位置對準點G位於最接近標革巴 a之4 7b之右下端。這時’測定對物顯微鏡之位置對 準點0之切斷台8在X轴方向和Y軸方向之移動距離。. f事先，要先辨識最接近之標靶化和7b之右下端之距 離時，在上述者中，從切斷台8在乂轴方向和丫轴方向之 移動距離，可以辨識半導體晶圓1之傾斜。 例如’當對定向平面（心如⑽㈣㈣之义轴之傾斜 為ΔΘ ’辨識標熱之X軸方向之間隔為d，從標乾之右下 端到鄰接標乾之右下端之在x轴方向之移動距離為Δχ 312ΧΡ/發明說明書(補件)/97·02/96146071 15 200832537 時，成為 COS△卜Λχ/d。 :此：依據△“‘(△〜)，可以求得^。 3二，方式所求得之半導體晶圓1之傾斜ΛΘ，特別 壯詈<口個之切副線’將校正後之資訊預先記憶在切割 次之切割之誤差為°.2㈣對半導體晶圓 f仃切剎，而可以正確地實施切割。 =等之偏移量~、Δχ和對χγ轴方向之傾斜△以1 個個之切割錄^隹j k w， 、、 人，杈正後之資訊預先記憶在切片裝 面二二1 _人之切片之誤差為0.2# m對半導體晶圓全 進仃刀割，而可以正確地實施切割。 依照上述實施形態1時可以獲得以下之效果。 合斜:錯决地進打半導體晶圓1之位置確認，所以不 :一 1衣者在半導體晶圓外周侧之晶圓環（waferring)進 订切片，或除去半導體晶圓之有效電路區域部份之切割， 可以謀求良率之提高。 σ (實施形態2) 二兄Γ本發明之實施形態2。圖3表示使用在本發明 ▲之二加㈣之半導體晶圓之形成之光罩。圖4是具有使用 忒光罩所形成之佈線層之半導體晶圓之剖面圖，圖5是上 ，圖用來表不使該半導體晶圓如實施形態】之方式之切 ，後，組裝在引線框架或框架載體等之組裝構件前之狀 ΐ同ί圖、1和圖2同等部份以相同之符號表示。圖5⑻ 疋圖5(a)之主要部份擴大圖。 312ΧΡ/發明說明書(補件)/97-02/96146071 16 200832537 在本實施形態中，除了實施形態}之構造外，在構成辨 識用圖案區域之虛擬半導體裝置形成區域（以下稱為虛擬 晶片）η内，利用半導體處理之最上佈線層製入作為辨識 用標乾12之L字狀圖案。該等之辨識標乾12在半導體晶 圓之衣日^•之佈線之圖案製作時，使用佈線用光罩製作。 • ϋ 3表不半導體晶圓之製造時之佈線層之圖案 時，所使用之最上層佈線之圖案形成用之光罩。該光罩9 將電路區域製人到各個圖案1G。在該各個圖案Μ之其餘 區域’與辨識用標把⑺相當之辨識用圖案7R在每-個晶 片》又置1個’另外，在光罩9上設置虛擬區域UK，其具 備有與1個之辨識用標乾！ 2相當之辨識用圖案^找。 使用上述光罩㈣成之該等辨制標乾12和辨識用標 ::^ a It Z J ^ ^ ^ 系之保護膜！3之聚酸亞胺t :? “佈線層上之有機 4 A 亞胺膑。圖4是具備有辨識用圖案 亞虛=晶片U之剖面圖。在其他之圖案區域形成有聚酿 ^女版，但疋在具備有辨識用標幻2之虛擬晶片u上， =谷易洲光學式檢财段，例如以光學顯微鏡進行檢 測’所以不形成聚酿亞胺膜。 丄：表：具傷使用該光罩並以圖案製作形成之辨 ίΓ: 虛擬晶片U，和具備有辨識用標W之半Identification; mark - according to the above identification 嶋,, spring V, and the cutting step according to the above cutting line. In the manufacturing method of the semiconductor device described above, the above-described cutting is performed in the above-described semiconductor device manufacturing method. In another step, the semiconductor wafer is divided into wafers corresponding to the semiconductor device formation region, and the step of picking up the semiconductor wafer includes: a step of optically detecting the identification target by 10; and Decide on the steps to pick up the location. _ According to this configuration, since the pickup is performed in accordance with the optical detection result, the actual assembly can be easily performed. Further, in the above method of manufacturing a semiconductor device, the above-described identification target is constructed such that each wafer can be identified, in an inspection step (inspection for each wafer), and a memory step (for inspection results and identification) The target is memorized together in the memory), and the pick-up step (for picking up the semiconductor wafer that is divided into individual wafers in the above-described cutting step) includes 312XP/invention specification (supplement)/97-02/96146071 13 200832537 The step of picking up the wafer that has been checked for failure in the above inspection step is avoided. : In this configuration, 'the defective product is not assembled and can be assembled reliably. The identification pattern of each surface of the area formed by the half-body 1 formation area, and the inspection result obtained by the inspection (4) is memorized in the '4', which can be grouped according to the characteristics of the wafer, etc. Appropriate use can be used to improve yield. (Effect of the Invention) According to the above-mentioned half (four) wafer, since it is possible to clearly identify the rhyme formed on the round surface of the semi-guided limb, the cutting step in the semiconductor manufacturing process does not recognize the position of the semiconductor wafer. Identify errors and achieve South Accuracy (4). Further, in the pickup step of the semi-fourth manufacture, the identification target ' can be clearly recognized, so that the wafer position can be recognized, the two production efficiency can be improved, and the defective product and the wafer can be prevented from remaining. [Embodiment] Hereinafter, the embodiment of the present invention will be described in detail with reference to the drawings. (Embodiment 1) ' ~ Figure i shows a semiconductor wafer of the embodiment i of the prior art, which is attached to the equivalent portion of the semiconductor wafer of the prior art example shown in the disk diagram 13. In the present embodiment, a plurality of semiconductor device forming regions (wafers) 6 are formed in the semiconductor wafer 1, and an identification target 7 is formed in each of the semiconductor device forming regions '. In this semiconductor: 曰: 半导体 each of the semiconductor device forming regions 6 is formed with a circuit region ':: 312XP / invention manual (supplement) / 97 - 〇 2 / 9 like coffee 1 η 200832537 semiconductor device formation area For the formation of the treatment, the 7' is used for the identification layer of the semiconductor system, etc.: 蹲^ 梦 Β Β 在 在 在 在 在 在 在 在 在 在 在 在 在 在 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体. The targets 7 of the targets 7 are arranged to have the same interval in the gamma axis within the body day. Outside 'identification with the standard leather bar 7 Xi Shi f曰 this ^ degree can be. The size of the stem 7 is made larger as long as there is a 50" method for identifying the position of the semiconductor wafer 1 using the above-described identification stem 7 . Further, the device semiconductor wafer 1 is cut to move in the χγ direction, and is also constructed to be rotatable. The objective microscope cut into an optical detecting means is moved while moving the above-mentioned χΓn to the Π direction, and is arranged so that the right lower end of the remaining portion 7a of the semiconductor wafer 1 is located at the alignment point 0 of the objective microscope. Next, from this state, the alignment point G of the cutting table 8 in the x-axis direction and the Y-axis direction is located at the right lower end closest to the 4 7b of the standard bar a. At this time, the moving distance of the cutting table 8 of the alignment microscope 0 in the X-axis direction and the Y-axis direction is measured. f In advance, when the distance between the closest target and the lower right end of 7b is first identified, in the above, the semiconductor wafer 1 can be identified from the moving distance of the cutting table 8 in the x-axis direction and the x-axis direction. Tilt. For example, when the inclination of the axis of the orientation plane (the heart is like (10) (four) (four) is ΔΘ 'the interval between the X-axis directions of the identification heat is d, the movement from the lower right end of the stem to the right lower end of the adjacent stem is in the x-axis direction. When the distance is Δχ 312ΧΡ/inventive manual (supplement)/97·02/96146071 15 200832537, it becomes COS△Λχ/d. : This: According to △ “'(△~), you can find ^. 2, the way The tilt of the obtained semiconductor wafer 1 is particularly strong. The cut-off sub-line 'pre-memorizes the corrected information in the cutting time. The error of the cutting is °. 2 (4) on the semiconductor wafer f-cutting brake The cutting can be carried out correctly. = The offsets ~, Δχ, and the inclination to the χ γ axis direction are recorded by one of the cuts of the 隹jkw, ,, people, and the information of the 杈 后 is pre-memorized in the slice Face 2:1 _ human slice error is 0.2 # m, the semiconductor wafer is fully cut, and the cutting can be performed correctly. According to the above embodiment 1, the following effects can be obtained. The position of the semiconductor wafer 1 is confirmed, so no: one or one person is outside the semiconductor wafer. The wafer side of the peripheral side can be sliced or the portion of the effective circuit region of the semiconductor wafer can be removed, and the yield can be improved. σ (Embodiment 2) The second embodiment of the present invention is the second embodiment. 3 is a view showing a photomask formed using the semiconductor wafer of the second embodiment of the present invention. FIG. 4 is a cross-sectional view of a semiconductor wafer having a wiring layer formed using a diret, and FIG. 5 is a top view. The semiconductor wafer is not cut in the manner of the embodiment, and then assembled in the front of the assembly member such as the lead frame or the frame carrier, and the same parts as in FIG. Fig. 5(8) is an enlarged view of the main part of Fig. 5(a). 312ΧΡ/Invention Manual (Supplement)/97-02/96146071 16 200832537 In the present embodiment, in addition to the structure of the embodiment, the configuration is used for identification. In the dummy semiconductor device formation region (hereinafter referred to as dummy wafer) n of the pattern region, an L-shaped pattern as the identification stem 12 is formed by the uppermost wiring layer of the semiconductor processing. The identification stem 12 is on the semiconductor wafer. Cloth day When the pattern is produced, it is produced by using a wiring mask. ϋ 3 When the pattern of the wiring layer at the time of manufacturing the semiconductor wafer is not shown, the mask for forming the pattern of the uppermost layer used is used. The area is made to the respective patterns 1G. In the remaining areas of the respective patterns ', the identification pattern 7R corresponding to the identification target (7) is set to one on each wafer. In addition, a virtual area is set on the reticle 9. UK, which has the identification of one of the identification labels! 2 The identification pattern is equivalent to ^. Use the above-mentioned mask (4) to make the identification of the stem 12 and the identification mark:: ^ a It ZJ ^ ^ ^ Protective film! 3 of the acid imine t:? "Organic 4 A imine oxime on the wiring layer. Figure 4 is a cross-sectional view of the identification pattern sub-virtual = wafer U. In other pattern areas formed a poly However, 疋 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = The mask is formed by patterning: the virtual wafer U, and the half with the identification mark W

置形成區域（以下稱為晶片）6之半導體晶圓 用與貫施形態1同樣之方、、參、隹> a $ J 在薄片18上之狀態。㈣置對準和切割’而貼著 3聰發明說明書(補件)/97·02/96146071 17 200832537 依照此種方式，在本發明之半導體晶圓中，在具備有辨 識用圖案之虛擬晶片11上，形成有撿拾辨識用標無12， 在錄拾辨識用標歡12±，除去作為保護膜13之聚酿亞 T膜:在構成半導體晶圓之發基板17之表面，介隔層間 .絕賴16，形成由最上層佈線層構成之辨識用標靶12， _其上層形成有氧化矽膜，氮化矽膜等之無機保護膜14, 和由聚醯亞胺膜構成之有機系之保護膜13。符號15是佈 線=之層間絕緣膜。當無機保護膜14使用氮化石夕膜之情 況卞為此具有防止反射之效果，最好存在於辨識用標乾 上。 另外’構成作為第2辨識用圖案之辨識用標乾之虛擬晶 片11如上述之方式，在半導體晶圓之製造時之佈線層 之圖案製作時，使用佈線用光罩進行製作。另外，辨識用 標靶12形成用之圖案之大小最好成為較大，可以成為_ // m %度’且只要是利用光學式&測手段可以檢測之形 _ 狀’可以成為任意之形狀。 其次，參照圖5用來說明使用以上述圖3所示之 形成之半導體晶圓卜於形成半導體裝置時之半導體晶片 -之撿拾方法。該半導體晶圓1是在每指定數之晶片設i曰且 備辨識用圖案12之虛擬晶片u，並且在每一個晶片使辨 識用標革巴7形成在佈線層。 圖5表示使固定有多個之晶片6之擴展薄片18擴張後 之狀癌。首先’在步驟31 :最初利用藉由光學式檢測手 段之辨識攝影機，辨識虛擬晶片u上之辨識用而在標乾 312XP/發明說明書(補件)/97-〇2/96146071 ig 200832537 和晶片間隔。這時，以不會撿拾具有辨 晶片11以及由於檢查而成為不良品之 产杳所^將如此之貧訊預先記憶在撿拾裝置（記憶由於 :斤產生之晶圓映像等之資訊)。在步驟s2:其次依照 利用辨識攝影機所辨識到晶 、 S Γ = t利用彈性夾進行該晶片之撿拾。在步驟 — 弹夾私動到下-個之辨識用標靶12之晶片，谁 订步驟S1。然後，重複進行步驟S1至3。 依照上述實㈣態時可以獲得T狀效果。 因為利用辨識用標靶12可以氺岛彳 經由辨識其周邊晶片之晶片^辨識晶片，所以 不會發生由於經擴展之薄片片片^ 引起之不良撿拾，和不會有晶片殘留。 -“而 另外，因為可以在該情況檢測夂 以不會有晶片之定位需要長：曰曰片之位置資訊，所 效率。 '守間之情況’而可以提高生產 另外’在此處是在每—個晶片形 是亦可以構成圖案，在每_個 辛識用“革巴7,但 案’例如區塊號碼或姓名等。：此二二可個別辨別之圖 S1 :最初，利用藉由光學式 、况，在上述步驟 地辨識該辨識用標靶7，並盆、^之辨識攝影機，順序 檢查。這時，以不會撿^人且共、:己L在自己憶器。然後進行 η和由於檢查而成為不=備有辨識用標乾之虛擬晶片 訊預先記憶在撿拾裝置,阳 方式，將如此之資 己憶由於檢查產生之晶圓映像等 312XP/發明說明書(補件)/97-02/96146071 200832537 之，訊）。在步驟S2 :其次依照利用辨識攝影機 ::片和：片間隔，使彈性失(把持手段)移動，利用彈 個之辨識用一晶片，進行步動 行步驟S1至3。 欠重硬進 依照此種方法時，即使在錯誤地使晶 =每-個晶片形成有可辨識之辨識用縣:所以： (實施形態3) ^次說明本發明之實施形態3。圖6表示本發明之 形您之半導體晶圓之形成所使用之光罩，圖二 光罩所形成之半導體晶圓，將與圖工和圖2同等：= 同之符號表示。圖6⑻是圖6(a)之主要部份擴大圖，圖 7(b)是圖7(a)之主要部份擴大圖。 圖7表示半導體晶圓在製造時，使用於佈線層之 作時所使用之最上層佈線之圖案形成用之光罩所形成之 半導體晶圓。該半導體晶圓’與上述實施形態2不同，在 每一個晶片未具備有辨識用標靶7,在丨片之光罩，於與 1個之虛擬晶片11相當之區域具有辨識用標靶12為其特 徵。與上述實施形態2同樣地，該光罩9在圖案1{^入 有電路區域。 《 然後，在構成辨識用圖案區域之虛擬晶片u内，利用 ^導體處理之最上佈線層，製入作為辨識用標靶12之L 字狀圖案。該等之辨識標靶12 ’在半導體晶圓之製造時 312XP/發明說明書(補件)/97-02/96146071 20 200832537 之佈線S製作時’如圖6(a)和（b)所示，使用佈線用 光罩製作。用以形成賴用躲12之辨識用®案12R， 形成在虛擬晶片11形成用之圖帛⑽表面全體。在此處 至少於該辨識用標乾上，為能容易地利用光學顯微鏡檢 f不=成覆盍在佈線層上作為有機系之保護膜13之聚The semiconductor wafer in which the formation region (hereinafter referred to as wafer) 6 is placed is in the same state as the configuration of the first embodiment, and the reference, 隹 > a $ J is on the sheet 18. (4) Alignment and dicing 'and affixed with 3 Cong invention manual (supplement) /97·02/96146071 17 200832537 In this manner, in the semiconductor wafer of the present invention, the dummy wafer 11 having the identification pattern is provided On the top, the identification mark 12 is formed, and the labeling 12± is removed, and the poly-tano film T as the protective film 13 is removed: on the surface of the substrate 17 constituting the semiconductor wafer, the interlayer is interposed. Lai 16, forming an identification target 12 composed of an uppermost wiring layer, and an inorganic protective film 14 formed of a ruthenium oxide film, a tantalum nitride film, or the like, and an organic system composed of a polyimide film Membrane 13. Reference numeral 15 is an interlayer insulating film of wiring =. When the inorganic protective film 14 is made of a nitride film, it has an effect of preventing reflection for this purpose, and it is preferably present on the identification stem. Further, as described above, the dummy wafer 11 constituting the identification target for the second identification pattern is produced by using a wiring mask during patterning of the wiring layer during the manufacture of the semiconductor wafer. Further, it is preferable that the size of the pattern for forming the identification target 12 is large, and it can be _ // m % degree ' and can be any shape as long as it can be detected by the optical & . Next, referring to Fig. 5, a method of picking up a semiconductor wafer using the semiconductor wafer formed as shown in Fig. 3 above to form a semiconductor device will be described. The semiconductor wafer 1 is a dummy wafer u provided with a pattern 12 for identification for each designated number of wafers, and an identification stamp 7 is formed on the wiring layer for each wafer. Fig. 5 shows a cancer in which the expanded sheet 18 to which a plurality of wafers 6 are fixed is expanded. First of all, in step 31: initially using the identification camera by optical detection means to identify the identification on the virtual chip u in the standard dry 312XP / invention manual (supplement) / 97-〇2/96146071 ig 200832537 and wafer spacing . At this time, such a poor news is preliminarily stored in the pick-up device (memory due to information such as the wafer image generated by the battery), without picking up the wafer 11 and the defective product due to the inspection. In step s2: secondly, according to the identification of the crystal by the identification camera, S Γ = t, the wafer is picked up by the elastic clip. In the step - the clip is privately moved to the next wafer for identifying the target 12, who sets the step S1. Then, steps S1 to 3 are repeated. The T-like effect can be obtained according to the above (4) state. Since the identification target 12 can be used to identify the wafer via the wafer identifying the peripheral wafer, the defective pickup due to the expanded sheet does not occur, and no wafer remains. - "In addition, because it can be detected in this case, there will be no need for the positioning of the wafer: the location information of the cymbal, the efficiency. The situation of the shoud can increase the production of the other 'here is in every A wafer shape can also be used as a pattern, and each _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ : The two figures can be individually identified. S1: Initially, the identification target 7 is identified by the optical method and the above steps, and the identification camera is potted and checked. At this time, it will not be awkward and common, and it is already in your own memory. Then η and due to the inspection become not = the virtual chip with the identification of the stem is pre-memorized in the pick-up device, the positive mode, will be such a memory, the wafer image generated by the inspection, etc. 312XP / invention manual (supplement ) /97-02/96146071 200832537, news). In step S2: secondly, the elastic loss (holding means) is moved in accordance with the use of the recognition camera :: slice and film interval, and the step S1 to 3 are performed by using a wafer for identification. In the case of this method, even if the crystal is erroneously formed into a discriminable identification county for each wafer: (Embodiment 3) The third embodiment of the present invention will be described. Figure 6 shows the reticle used in the formation of the semiconductor wafer of the present invention. The semiconductor wafer formed by the reticle will be equivalent to the drawing and Figure 2: = the same symbol. Fig. 6 (8) is an enlarged view of a main portion of Fig. 6 (a), and Fig. 7 (b) is an enlarged view of a main portion of Fig. 7 (a). Fig. 7 shows a semiconductor wafer formed by a mask for pattern formation of the uppermost layer wiring used in the wiring layer during the manufacture of a semiconductor wafer. Unlike the second embodiment, the semiconductor wafer is not provided with the identification target 7 for each wafer, and the identification mask 12 is provided in the region corresponding to one of the dummy wafers 11 in the mask of the wafer. Its characteristics. In the same manner as in the second embodiment described above, the mask 9 has a circuit region in the pattern 1. Then, in the dummy wafer u constituting the pattern region for identification, the L-shaped pattern as the identification target 12 is formed by the uppermost wiring layer of the conductor treatment. The identification target 12' is shown in Fig. 6(a) and (b) when the wiring S of the semiconductor wafer is manufactured 312XP/invention specification (supplement)/97-02/96146071 20 200832537. It is made using a wiring mask. The identification 12R for forming the hiding layer 12 is formed on the entire surface of the pattern (10) for forming the dummy wafer 11. Here, at least on the identification stem, it is possible to easily use the optical microscopy to detect the fusion of the protective film 13 as an organic system on the wiring layer.

Sik亞胺。Sik imine.

構成作為第2辨識用圖案之辨識用標靶之虛擬晶片 如上述之式’在半導體晶圓之製造時之配線層之圖 ^作時’使用佈線用之光罩而製作。另夕卜 12之大小最好成為較大，可以成為程度，只要是 :以利用光學式檢測手段檢測之形狀，可以成為任意 狀0 最上層佈線層形成辨識用 之圖案’並不只限於最上 等。 另外，在上述實施形態中是在 圖案，但是只要可以光學式辨識 層佈線層，亦可以使用下層佈線 (實施形態4) 來/ _態4°圖8是擴大說明圖，用 末表不本务明之實施形態之半導體晶圓上體 形成區域（以下稱為半導體晶片） 、·^置 圖中表示如圖7所示之半導上之、 晶片6’在本實施形態中’上述辨識 +V體 晶片之周緣相當之區域’以在構成襯墊：：金 字狀之中空圖案22之方式所得到之中空圖案而^成十 依照此種構造時，在與容易產生大幅位置偏移H片周 312ΧΡ/發明說明書(補件)/97-02/96146071 2\ 200832537 緣相當之區域，形成辨識用標輕，可以進行更高精確度之 定位’並在組裝時可以有效地謀求位置精確度之提高。 另外，該辨識用標靶，只要在襯墊之圖案製作步驟變更 光罩，就可以形成。另外，因為在襯墊之圖案形成中空圖 ‘ 案，所以不會造成佔用面積之增大，可以形成在襯墊上。 . 另外，如圖1〇所示，在結合時使熔融金屬流入到成為該 中空圖案22之區域，可以不會使電氣連接性降低地連 接，和不會造成電阻之增大。另外，可以提高與連結線 _ 23之接合強度。 (實施形態5) 其次說明本發明之實施形態5。圖u是擴大說明圖， 用來表示本發明之實施形態之半導體晶圓上之半導體晶 片6 ’圖12為其B-B剖面圖。 圖中表示如圖7所示之半導體晶圓1上之1個之半導體 裝置形成區域（半導體晶片）6,在本實施形態中，上述辨 _識用私靶形成在與上述晶片之周緣相當之區域，上述辨識 用才下革巴由^ 3襯墊上之帶狀之將保護膜工3之除去後保護 •膜除去區域24構成。在構成襯墊21之金屬和保護膜u •，界=和在保濩膜和基板表面之界面，具有正交部，以 1正交部作為辨識餘之中心進行檢測，可以達成 確度之提高。 ％ 工時之增大，可以容易而 依照此種構造時不會造成製造 且以高可靠度進行辨識。 (產業上之可利用性） 312XP/發明說明書(補件)/97__614_ 200832537 如乂上所δ兄明之方式， &化時亦可u % ~ & …本毛明^，即使在晶片之微 細化时π了以進行高精 具妯i隹粁古#隹又心刀幻和在撿拾步驟可以容 易地切4確度之撿拾，所以可以 微細晶片之半導#曰n u处m斗 牡办成Lbi寻之 日日圓及使用其之半導體裝置之製造方 【圖式簡單說明】 ::為表示本發明之實施形態1之半導體晶圓之圖。 \(a)、（b)為表示本發明之實施形態1之半導體晶圓 之切吾彳步驟之位置確認方法之圖。 圖3為表示本發明之實施形態2所使用之光罩之圖。 圖4是本發明之實施形態2之半導體晶圓之剖面圖。 圖5(a)、（b)是說明圖，用來表示本發明之實施形態2 之晶片之撿拾方法。 圖6(a)、(b)為表示本發明之實施形態3所使用之光罩 之圖。 圖7(a)、（b)為表示本發明之實施形態3之半導體晶圓 之圖。 圖8為表示本發明之實施形態4之半導體晶片之圖。 圖9是圖8之A-A剖面圖。 圖10為表示結合後之狀態之圖。 圖11為表示本發明之實施形態5之半導體晶片之圖。 圖12是圖11之a-A剖面圖。 圖13為表示先前技術之半導體晶圓之圖。 【主要元件符號說明】 312XP/發明說明書(補件)/97-02/96146071 23 200832537 1 半導體晶圓 2〜5 先前技術之辨識標靶 6 晶片（半導體裝置形成區域） 7 切割辨識用標靶 7a 標靶 7b 標靶 8 切斷台 9 光罩 10 圖案 11 撿拾辨識用圖案（虛擬晶片） HR 虛擬區域 12 辨識用標靶 12R 辨識用圖案 13 聚醯亞胺膜（有機系之保護膜） 14 無機保護膜 15 (佈線間）層間絕緣膜 16 層間絕緣膜 17 矽基板 18 擴展薄片 21 襯墊 22 中空圖案 23 連結線 24 保護膜除去區域 312XP/發明說明書(補件)/97-02/96146071 24A dummy wafer constituting a target for identification of the second identification pattern is produced by using a mask for wiring when the wiring layer of the semiconductor wafer is manufactured as described above. Further, it is preferable that the size of the size 12 is large, and it can be as long as it is: the shape detected by the optical detecting means can be an arbitrary pattern. The pattern for forming the uppermost wiring layer is not limited to the top. Further, in the above embodiment, the pattern is used. However, as long as the layer wiring layer can be optically recognized, the lower layer wiring (Embodiment 4) can be used. / _ state 4° Fig. 8 is an enlarged explanatory view. The semiconductor wafer upper body formation region (hereinafter referred to as a semiconductor wafer) in the embodiment of the present invention, and the semiconductor wafer 6' shown in FIG. 7 on the semiconductor track as shown in FIG. The area corresponding to the peripheral edge of the wafer is a hollow pattern obtained by constituting the spacer::a hollow pattern 22 in the shape of a gold, and in accordance with such a configuration, it is easy to generate a large positional shift H piece circumference 312 ΧΡ / Invention specification (supplement) /97-02/96146071 2\ 200832537 The area where the edge is equivalent, the identification light is formed, and the positioning with higher accuracy can be performed', and the positional accuracy can be effectively improved during assembly. Further, the identification target can be formed by changing the mask in the pattern forming step of the spacer. In addition, since the hollow pattern is formed in the pattern of the spacer, the increase in the occupied area is not caused, and it can be formed on the spacer. Further, as shown in Fig. 1A, the molten metal flows into the region which becomes the hollow pattern 22 at the time of bonding, and the electrical connection can be prevented from being lowered without causing an increase in electric resistance. In addition, the bonding strength with the connecting wire _ 23 can be improved. (Embodiment 5) Next, Embodiment 5 of the present invention will be described. Figure 5 is an enlarged explanatory view showing a semiconductor wafer 6' on a semiconductor wafer according to an embodiment of the present invention, and Figure 12 is a cross-sectional view taken along line B-B thereof. The semiconductor device forming region (semiconductor wafer) 6 on the semiconductor wafer 1 shown in FIG. 7 is shown in the figure. In the present embodiment, the private target for identification is formed on the periphery of the wafer. In the region, the above-mentioned identification is formed by removing the protective film 3 from the protective film 3 in a strip shape on the liner. The metal constituting the spacer 21 and the protective film u, the boundary = and the interface between the protective film and the substrate surface have orthogonal portions, and the one orthogonal portion is used as the center of the identification, and the accuracy can be improved. The increase in the number of man-hours can be easily made without causing manufacturing and identification with high reliability. (Industrial Applicability) 312XP/Invention Manual (Replenishment)/97__614_ 200832537 If you use the method of δ brother in the 乂, you can also u % ~ & ... 本毛明 ^, even in the wafer When the time is π, the high-precision 妯i隹粁古# 隹 心 心 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡 捡The manufacturing day of the Japanese yen and the semiconductor device using the same are shown in the drawings. The following is a drawing of the semiconductor wafer according to the first embodiment of the present invention. (a) and (b) are diagrams showing a method of confirming the position of the cutting step of the semiconductor wafer according to the first embodiment of the present invention. Fig. 3 is a view showing a photomask used in the second embodiment of the present invention. Figure 4 is a cross-sectional view showing a semiconductor wafer according to a second embodiment of the present invention. Figs. 5(a) and 5(b) are explanatory views showing a method of picking up a wafer according to a second embodiment of the present invention. Fig. 6 (a) and (b) are views showing a photomask used in the third embodiment of the present invention. Fig. 7 (a) and (b) are views showing a semiconductor wafer according to a third embodiment of the present invention. Fig. 8 is a view showing a semiconductor wafer according to a fourth embodiment of the present invention. Figure 9 is a cross-sectional view taken along line A-A of Figure 8. Fig. 10 is a view showing a state after bonding. Fig. 11 is a view showing a semiconductor wafer according to a fifth embodiment of the present invention. Figure 12 is a cross-sectional view taken along line a-A of Figure 11; Figure 13 is a diagram showing a prior art semiconductor wafer. [Description of main component symbols] 312XP/Invention Manual (Supplement)/97-02/96146071 23 200832537 1 Semiconductor wafer 2 to 5 Prior identification target 6 Wafer (semiconductor device forming region) 7 Cutting identification target 7a Target 7b Target 8 Cutting table 9 Mask 10 Pattern 11 Pickup identification pattern (virtual wafer) HR Virtual area 12 Identification target 12R Identification pattern 13 Polyimine film (organic protective film) 14 Inorganic Protective film 15 (inter-wiring) interlayer insulating film 16 interlayer insulating film 17 矽 substrate 18 expanded sheet 21 liner 22 hollow pattern 23 connecting line 24 protective film removing area 312XP / invention manual (supplement) / 97-02/96146071 24

Claims (1)

200832537 十、申請專利範圍：200832537 X. Patent application scope: 區域 種半$肢晶圓，被畫定成為多個之半導體裝置形成 如此之半導體晶圓， 、在上述半，體晶圓表面之指定數之上述半導體裝置形 、A或之每個，具備有至少一個之辨識用標輕 (target)； >上述辨識用_可以湘光學式檢測手段檢測，並根據 该檢測到之位置可以辨識半導體晶圓上之位置。 2. 如申請專利範圍第丨項之半導體晶圓，其中， 上逑辨識用標乾在每—個之半導體裝置（晶片）形成區 域’至少配置1個。 3. 如申請專利範圍第丨項之半導體晶圓，其中， 上述辨識用標乾由半導體處理之最上佈線層所形成。 4. 如申請專利範圍第2項之半導體晶圓，其中， 更在扣疋數之半導體裝置形成區域之每一個，具備形成 •有個之辨識用標靶之虛擬（dummy)半導體裝置形成區域 (虛擬晶片）。 ^ 5·如申請專利範圍第3項之半導體晶圓，其中， • 在上述辨識用標靶之上層，保護膜被除去。 6·如申請專利範圍第5項之半導體晶圓，其中， 上述保5蒦膜為聚酿亞胺膜。 7.如申請專利範圍第丨項之半導體晶圓，其中， 上述辨識用標靶形成在與上述半導體裝置形成區域之 周緣相當之區域。 2XP/發明說明書(補件)/97-02/961460Ή 25 200832537 8·如申請專利範圍第7項之半導體晶圓，其中， 上述辨識用標革巴被配置在襯塾之近旁。 9·如申請專利範圍第8項之半導體晶圓，其中， 上述辨識用標靶在襯墊或襯墊近旁由構成上述襯墊之 材料之圖案所構成。 10·如申請專利範圍第5項之半導體晶圓，其中， 、上述辨識用標靶為包含襯墊上之帶狀之保護膜除去區 域。 11.如申請專利範圍第2項之半導體晶圓，其中， 上述辨識用標靶在每一個之半導體裝置形成區域成為 不同，以可以個別辨識之方式所形成。 … 12·如申請專利範圍第2項之半導體晶圓，其中， 上述辨識用標乾在同一線上至少設置有2個。 13·如申請專利範圍第12項之半導體晶圓，其中， 上述辨識用標靶在每一線，隔開指定之間隔設 2個。 少啕 14.如申請專利範圍第！至13項中任一項之半導體曰 圓，其中， 曰曰 上述辨識用標輕為具有與上述晶片之切割線相當之線 之平行之邊之矩形圖案。 ^-種半導體舉置之製造方法，係使用有中請專利範 圍弟1至13項t任-項之半導體晶圓；如此之半導體麥 ，之=造方法’其在將上述半導體晶圓分割成為與上料 導體裝置形成區域對應之各個之晶片之切割(d i c i⑻步 312XP/發明說明書(補件)/97-02/96146071 26 200832537 驟，係包含有： 光學式檢測上肖縣之 依妝上述辨識用標革巴而 依照上述切割線進行切割之步刀=線之步驟；和 法 含有： 識用⑼決定切割線之步驟，係包 檢測上述辨識用標乾之第！點之步驟. 檢，上賴識用標乾之第2點之步驟；， 算出以:述第2點之座標之步驟，· 標之差分之步驟，·和 传之測定座標和邏輯上之座 校正步驟’根據上述差分校正切割線。 17.如申請專利範圍第15 法，其中，撿拾在上述切割步中，置之製造方 述半導趙裝置形成區域二η為與各個之上 驟，係包含有： 々 之半ν體晶圓之步 光學式地檢測上述辨㈣錄之步驟 依照上述辨識用標靶決定撿拾位置之步驟。 法利範圍第17項之半導體裝置之製造方 法其中，決疋上述撿拾位置之步驟，係包含有： 檢測上述辨識用標靶之第1點之步驟； 檢測上述辨識用標靶之第2點之步驟；’ 312XP/發明說明書(補件)/97-02/96146071 以上述第1點作為基準點，㈣定上述第2點之座標之 27 200832537 步驟；:出：上，則定結果所獲得之測定邏輯 才示之差分之步驟；和 :正步驟’根據上述差分校正撿拾位置。 19.如申請專利範圍第18 法，其申， 上述辨識用圖案，伤赫> ^ ^ ^ 口系係被構建成可以分別識別每一個半導 體裝置形成區域， 丁宁 而依每一個上述半導艚 V體衣置形成區域分別進行檢杳 檢查步驟，盥 — 項之半導體裝置之製造方 之 將檢查結果和各個辨 ;以及， 案一起記憶在記憶器之步 巴Ltr割步財被分割成為與上述半導體裝置形成:二應之各個晶片之半導體晶圓’進行撿拾之步驟， 曰^上34記憶||，避開在上述檢查步驟中成人 ^ 曰曰片而進行撿拾之步驟。 "秸之 312ΧΡ潑明說明書(補件)/97__舰 28A semiconductor wafer of a plurality of regions is formed into a plurality of semiconductor devices to form such a semiconductor wafer, and the semiconductor device, A or each of the specified number of the surface of the wafer is provided At least one identification target is used; > the above identification is detected by the optical detection means, and the position on the semiconductor wafer can be identified based on the detected position. 2. The semiconductor wafer according to the ninth aspect of the invention, wherein the upper surface of the semiconductor device (wafer formation area) is disposed at least one. 3. The semiconductor wafer of claim 3, wherein the identification stem is formed by a semiconductor-treated uppermost wiring layer. 4. The semiconductor wafer according to claim 2, wherein each of the semiconductor device forming regions of the number of turns has a dummy semiconductor device forming region in which the identification target is formed ( Virtual chip). ^5. The semiconductor wafer according to item 3 of the patent application, wherein: • the protective film is removed on the upper layer of the above-mentioned identification target. 6. The semiconductor wafer according to claim 5, wherein the above-mentioned film is a polyimide film. 7. The semiconductor wafer according to the above aspect of the invention, wherein the identification target is formed in a region corresponding to a periphery of the semiconductor device forming region. 2XP/Invention Manual (Repair)/97-02/961460Ή 25 200832537. The semiconductor wafer of claim 7, wherein the identification standard bag is disposed near the lining. 9. The semiconductor wafer according to claim 8, wherein the identification target is formed by a pattern of a material constituting the spacer in the vicinity of the spacer or the spacer. 10. The semiconductor wafer according to claim 5, wherein the identification target is a strip-shaped protective film removal region on the spacer. 11. The semiconductor wafer according to claim 2, wherein the identification target is different in each of the semiconductor device formation regions, and is formed to be individually identifiable. [12] The semiconductor wafer of claim 2, wherein the identification stem is provided on at least two of the same lines. 13. The semiconductor wafer according to claim 12, wherein the identification target is provided at a predetermined interval between each of the lines. Lesser 14. If you apply for a patent range! The semiconductor circle of any one of the preceding claims, wherein the identification mark is a rectangular pattern having a parallel side of a line corresponding to a cutting line of the wafer. ^-The method of manufacturing a semiconductor device is to use a semiconductor wafer having a range of 1 to 13 items in the patent range; such a semiconductor chip, which is a method of forming a semiconductor wafer into The cutting of each wafer corresponding to the forming region of the feeding conductor device (dic i (8) step 312XP / invention manual (supplement) / 97-02/96146071 26 200832537) includes: optical detection of the above The step of recognizing the stepping knife=line according to the above-mentioned cutting line by using the standard leather; and the method includes: the step of determining the cutting line by using (9), and the step of detecting the first point of the above-mentioned identification using the labeling. The step of using the second point of the standard is calculated; the step of calculating the coordinates of the second point, the step of the difference between the targets, and the measurement of the coordinate and the logical seat correction step 'according to the above difference Correcting the cutting line. 17. The method of claim 15 wherein, in the cutting step, the manufacturing method of the semi-guided device forming region η is associated with each of the above steps, and the system includes: ν body wafer The step of optically detecting the above-mentioned discriminating (four) recording step is to determine the pick-up position according to the above-mentioned identification target. The method for manufacturing the semiconductor device according to the seventh aspect of the invention, wherein the step of determining the pick-up position includes: a step of detecting the first point of the identification target; a step of detecting the second point of the identification target; '312XP/invention specification (supplement)/97-02/96146071 using the first point as a reference point, (4) The coordinates of the above-mentioned point 2 of the above-mentioned point 27, 200832537;; out: the step of determining the difference between the measurement logic obtained by the result; and: the positive step 'pick up the position according to the above differential correction. 19. If the patent application scope The 18th method, the application, the above identification pattern, the wounded > ^ ^ ^ mouth system is constructed to identify each semiconductor device forming region, and each of the above-mentioned semi-conducting V body-forming regions Perform the inspection and inspection steps separately, and the manufacturer of the semiconductor device will check the results and the individual identification; and, together with the case, remember the Ltr step in the memory. The step of dividing into a semiconductor wafer formed of the above-described semiconductor device is performed, and the step of picking up the semiconductor wafer is performed, and the step of picking up the adult film in the above-described inspection step is avoided. " 312 ΧΡ ΧΡ 说明书 说明书 说明书 说明书 说明书 说明书 97 97 97 97 97 97 97 97 97
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