JPH04369851A - Manufacturing method and device for semiconductor device - Google Patents

Abstract

PURPOSE:To provide a technique of manufacturing a semiconductor device, where the control of a wafer process can be effectively and accurately carried out without being affected by the surface state of a semiconductor wafer. CONSTITUTION:The discrimination data Wa of a semiconductor wafer, the arrangement data Wx of semiconductor devices X formed on the front side of the semiconductor wafer W, and data such as al-ignment marks M used for drawing patterns and the like are formed on the rear side of the semiconductor wafer W, and then the control of a wafer process is controlled basing on the data formed on the rear side of the wafer for recording.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing semiconductor devices, and in particular to a technology that is effective when applied to a wafer process in the manufacturing process of semiconductor devices.

0002

[Background Art] As semiconductor integrated circuits become more highly integrated and demand diversifies, the number of required types of semiconductor devices such as ASIC LSIs increases, while the manufacturing quantity per type decreases. are doing. For this reason, in ASIC LSIs, a standardization method such as the well-known master slice is adopted depending on the number of types and quantities to be manufactured. In the manufacturing process of semiconductor integrated circuits using semiconductor wafers, electron beam exposure technology, which will be described later, is used to expose semiconductor chip patterns of a plurality of types onto semiconductor wafers.

That is, in the manufacturing process of semiconductor integrated circuits, etc., in the exposure process for transferring a desired integrated circuit pattern onto a semiconductor wafer, instead of using light exposure technology, Published, "Electronic Materials" November 1986 issue special issue P110-P114,
As described in the literature, an electron beam exposure technique is used in which a resist coated on a semiconductor wafer is exposed by drawing a pattern with an electron beam. After exposure to electron beams, the resist is developed and used as a mask to process integrated circuit patterns on semiconductor wafers.

[0004] The electron beam exposure technique described above allows semiconductor chip patterns of a plurality of types to be drawn directly on a semiconductor wafer without creating a mask, which is required in conventional light exposure.

[0005] Further, a wafer transfer device for the purpose of sorting and aggregating a plurality of wafers by reading an identification symbol processed on the main surface of a semiconductor wafer is being considered.

[0006]

[Problems to be Solved by the Invention] In the above-mentioned prior art, the following problems have come to light.

As semiconductor integrated circuits become more highly integrated, AS
For IC LSIs, there has been a noticeable increase in the number of required types and a decrease in quantity. In particular, in the case of LSIs for large computers, the number of types manufactured is large and the quantity is small, and most of the required LSI types are used only once per computer. In such a case, not only are a plurality of types of semiconductor wafers mounted on the same semiconductor wafer, but the number of semiconductor wafers per application is as small as about five.

Conventionally, in addition to changing patterns, manufacturing process conditions have also been changed depending on the combination of wafers and the types of patterns to be processed on the wafers.

[0009] For this reason, the above-mentioned ASIC LSI
On production lines, the number of wafer lots increases, and conversely the number of wafers in a lot decreases, making wafer lot management and processing operations more complicated.

[0010] In the above-mentioned ASIC LSI manufacturing line, particularly in the exposure process, the required product type is obtained by changing the wiring between elements on the semiconductor chip. In this case, electron beam exposure is effective, but not only does the drawing pattern have to be changed within the wafer depending on the product type, but because the number of wafers in a lot is small, an operator is required to work on the electron beam exposure equipment all the time. Drawing preparations such as transferring drawing data become a throughput bottleneck, making work errors more likely. Even when conventional light exposure equipment is used, masks have to be replaced more frequently, making it easier for work errors to occur.

[0011] When semiconductor wafers are processed, inspected, and the like, the throughput is reduced due to the production of a wide variety of products in small quantities. In this case, in order to improve processing capacity by providing identification marks on the wafers, reading them, and sending the information to the processing and inspection departments, such production control information must be stored in large-scale computers. Attempts are being made to store information and issue instructions to each device from there. This idea requires support not only for the control system on the large-scale computer side but also on the control system for each manufacturing process device, and there are many problems in realizing it.

In addition, as in the past, wafer I is formed on a part of the surface of the semiconductor wafer on which semiconductor devices are formed, that is, the main surface.
When forming D, type information, and even alignment marks, there are naturally restrictions on the amount and type of information that can be written on the main surface in order to coexist with the semiconductor device. Furthermore, this information is processed and formed as irregularities on the main surface, but as the manufacturing process progresses, thin film deposition and etching cause these irregularities to become flattened, making it difficult to read. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device manufacturing technique that enables efficient and accurate control of wafer processes in high-mix, low-volume production of semiconductor devices.

Another object of the present invention is to provide a semiconductor device manufacturing technique that allows efficient and accurate wafer process control without being affected by the surface condition of the semiconductor wafer.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0016]

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions will be as follows:
It is as follows.

That is, the method for manufacturing a semiconductor device of the present invention can be applied, for example, to an identification symbol containing the type name of the semiconductor device processed and formed on the main surface of the semiconductor wafer, an identification symbol corresponding to the type name, or an identification symbol of the semiconductor wafer itself. Symbols, alignment marks, etc. are processed on the back side of semiconductor wafers, and these are read to control manufacturing processes such as exposure and inspection of semiconductor wafers, and to identify lots of semiconductor wafers to be supplied to the manufacturing process. It is designed to perform rearrangement, control of supply order, etc.

Furthermore, the semiconductor device manufacturing apparatus of the present invention includes:
a recognition unit that recognizes at least one of the identification information, process control information, and alignment mark of the semiconductor device formed on the back surface of the semiconductor wafer on which the semiconductor device is formed on the main surface, and the identification information of the semiconductor wafer; The processing section or the inspection section performs a processing or inspection operation on the main surface of the wafer, and the processing section or the inspection section collects the identification information and process control information of the semiconductor device obtained from the recognition means, the alignment mark, and the semiconductor wafer. Processing or inspection operations are controlled based on at least one piece of identification information.

[0019]

[Operation] According to the semiconductor device manufacturing technology of the present invention described above, an identification symbol containing the type name of the semiconductor device formed on the back surface of the semiconductor wafer, an identification symbol corresponding to the type name, or an identification symbol of the semiconductor wafer itself Furthermore, information such as alignment marks is not affected by the progress of various manufacturing processes such as thin film formation and etching on the main surface, so that accurate reading is possible at all times. In addition, since the back side of the semiconductor wafer does not coexist with semiconductor devices, the entire back side can be freely used for forming the various types of information, and a large amount of diverse information can accompany the semiconductor wafer. becomes possible.

[0020] This makes it possible to attach to the semiconductor wafer, for example, not only various identification information regarding the semiconductor wafer itself, but also identification information regarding each of the plurality of semiconductor devices formed on the main surface of the semiconductor wafer.
Using this information, it is possible to accurately manage and control a variety of processes, such as lot rearrangement of multiple semiconductor wafers, control of supply order, and alignment correction during pattern transfer using alignment marks formed on the back side. This makes it possible to efficiently control the wafer process in high-mix, low-volume production of semiconductor devices formed on the main surface of a semiconductor wafer.

[0021]

Embodiment 1 Hereinafter, a method and apparatus for manufacturing a semiconductor device, which is a practical example of the present invention, will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the main parts when the method and apparatus for manufacturing a semiconductor device according to the present invention are applied to an electron beam lithography process. That is, the semiconductor device manufacturing apparatus of this embodiment is configured as an electron beam lithography apparatus. Moreover, FIG. 2 is an example of a flowchart when applied to the formation of a metal wiring film or an insulating film in the manufacturing process of a semiconductor device.

As illustrated in FIG. 1, the electron beam lithography apparatus of this embodiment includes an electron beam lithography section A (processing section) and a lot forming section B (recognition section).

The electron beam lithography section A is composed of an X-Y table and the like, and includes a sample stage 1 on which a semiconductor wafer W is placed, and a sample stage 1 provided directly above the sample stage 1, and a semiconductor wafer W on the sample stage 1. An electron beam source 3 that irradiates an electron beam 2 to a sample, and an electron optical system 4 that is placed in the path of the electron beam 2 between the electron beam source 3 and the sample stage 1 and that controls the electron beam 2. We are prepared. Although not particularly shown, the sample stage 1, electron optical system 4, electron beam source 3, etc. are housed in a vacuum chamber, and the semiconductor wafer W is taken in and out of the vacuum chamber through a load lock chamber (not shown).

The electron optical system 4 is controlled by a drawing control section 5, and the drawing control section 5 is provided with a buffer memory 6 made of a semiconductor memory or the like and storing drawing data and the like.

Furthermore, the drawing control section 5 has an input/output control section (
A control computer 8 that controls the entire system is connected via an I/O) 7, and a data storage unit (drawing data) consisting of a large-capacity hard disk device, etc., in which drawing data regarding multiple types of semiconductor wafers W is stored. 9 is connected. The control computer 8 includes a central processing unit (CPU) 8a and a control terminal 8b consisting of a display, a control console, etc.
It is composed of etc.

The electron beam lithography section A is connected to the lot organization section B via an interface control section (I/O) 10.

On the other hand, the lot organizing section B includes a reading section 11 comprising a light source 11a, an optical system 11b, a sensor 11c, etc.
A signal processing section 12 consisting of a memory 12a in which judgment standard data etc. are stored, a comparator 12b, etc., a lot organization control computer (CPU) 13 that performs overall control, a lot data storage section 14, and an electron beam lithography section. The interface control unit (I
/O)15. Lot organization control computer 13
The computer is comprised of a central processing unit (CPU) 13a and a control terminal 13b consisting of a display, a control console, and the like.

In this case, on the back surface of the semiconductor wafer W, that is, on the back side of the main surface on which desired semiconductor devices are formed, there is, for example, a mark consisting of alphanumeric characters, bar codes, etc., as illustrated in FIG. Identification information Wa of the semiconductor wafer W, furthermore, arrangement information Wx within the semiconductor wafer W of a plurality of semiconductor devices (chips) X regularly arranged and formed on the main surface side of the semiconductor wafer W, furthermore, the main Positioning marks M, etc., which are used for positioning in pattern drawing for forming a plurality of semiconductor devices X on the surface side, etc., are formed.

[0030] Furthermore, the identification information Wa, the array information Wx, etc. are sufficiently large to be visible to the operator, and are, for example,
Each character is formed to a size of 3 mm square or more. Furthermore, the array information Wx corresponding to each of the semiconductor devices X is formed directly behind the formation position of the semiconductor device X on the main surface side of the semiconductor wafer W.
Even after the semiconductor device X is separated into individual chips by cutting, the array information Wx remains attached to the back surface of the semiconductor device X.

The reading section 11 of this embodiment reads the above-mentioned identification information Wa and arrangement information Wx written on the back surface of the semiconductor wafer W, and furthermore, if necessary, the alignment mark M, etc. is read optically, and the sensor 11c
The image data obtained is sent to the signal processing unit 12, and the signal processing unit 12 compares the image data with the reference data stored in the memory 12a in the comparator 12b, thereby determining the type of semiconductor wafer W and the plurality of types. It performs an operation of recognizing the arrangement state of semiconductor devices X and transmitting the information to the lot organization control computer 13.

The lot organization control computer 13 includes a reading unit 11
Based on the identification information Wa of each semiconductor wafer W obtained through the signal processing unit 12 and the arrangement information Wx within the semiconductor wafer W, an optimal lot consisting of one or more semiconductor wafers W is selected. Calculate the composition,
An operation is performed to store the obtained lot organization data in the lot data storage section 14. The lot organization section B is connected to the electron beam lithography section A via the interface control section 15, and is capable of exchanging information as described below.

Note that the lot forming section B and the electron beam lithography section A do not necessarily have to be mechanically integrated. This is because the processing capacity of the lot organizing section B is sufficiently larger than that of the electron beam lithography section A, and is advantageous in terms of cost, such as when a plurality of electron beam lithography sections A are provided. The above lot processing can be handled by off-line processing. However, in order to perform the following processing, control data can be transferred on-line between the control computers that control the components described above during designation. Although a storage medium such as a magnetic floppy disk may be used instead of online data transfer, the work efficiency will be reduced accordingly.

An example of the method for manufacturing a semiconductor device and the operation of the device in this embodiment will be described below.

In the case of this embodiment, a case will be described in which electron beam lithography processing is performed in the flow chart shown in FIG. 2, for example.

First, in the lot organizing section B, arbitrary lots k1 and k2 are formed before the resist coating process and recorded on the back surfaces of a plurality of semiconductor wafers W loaded in a cassette (not shown) or the like. Identification information Wa, array information Wx, etc. are read by the reading section 11 and signal processing section 12, and depending on the contents of the identification information Wa and array information Wx of each semiconductor wafer W, information is determined as appropriate for later electron beam lithography processing. The combination is determined and a new lot k consisting of one or more semiconductor wafers W is formed, and information on this new lot k is stored in the lot data storage section 14.

The semiconductor wafers W organized into lots k are then transported to the target electron beam lithography section A.

On the other hand, in the electron beam lithography section A, when a new lot k newly formed in the above-mentioned lot formation section B arrives, the information regarding the lot k is sent to the lot formation section via the interface control sections 10 and 15. It is read from the lot data storage section 14 of section B. Then, based on this read data, necessary drawing data is read from the attached data storage section 9 and transferred all together to the buffer memory 6 made of a semiconductor memory or the like. Simultaneously with this transfer of the drawing data, the semiconductor wafers W constituting the lot k are loaded all together into a load lock chamber (not shown) on the sample stage 1.

Then, the semiconductor wafers W are automatically placed on the sample stage 1 one after another, and the lithography control unit 5 uses the lithography data already transferred to the buffer memory 6 as described above to perform the electron beam process. After drawing the target pattern on the semiconductor wafer W by appropriately controlling the source 3 and the electron optical system 4, the drawing operation is continued by replacing the semiconductor wafer W with the next semiconductor wafer W, and by repeating this operation, different drawing data can be created. A plurality of types of semiconductor wafers W are continuously processed using the same without the need for loading/unloading operations via a load lock chamber.

As described above, according to the electron beam lithography apparatus of this embodiment, the semiconductor wafer W is placed on the back surface of the semiconductor wafer W in which a plurality of types of semiconductor devices
Various information such as identification information Wa regarding the individual semiconductor devices X and arrangement information Wx regarding the individual semiconductor devices X are recorded and formed.
This information is read out in the lot organization section B to accurately change the lot organization of the plurality of semiconductor wafers W, control the supply order, etc., so that the pattern writing process in the electron beam lithography section A can be carried out efficiently. can.

Particularly, great effects can be obtained in high-mix, low-volume production.

Further, even after the semiconductor wafer W is individually separated into a plurality of semiconductor devices X, the arrangement information Wx regarding each semiconductor device X is attached to the back surface of the semiconductor device X, so that various steps in the subsequent steps are performed. Management and control are also possible.

[0043]

Embodiment 2 FIG. 4 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device manufacturing apparatus according to another embodiment of the present invention. In the case of the second embodiment, a case will be described in which the present invention is applied to an electron beam lithography apparatus.

Stage 20 consisting of an X-Y table, etc.
A lens barrel 36 that houses an electron optical system having a structure as described later is connected to the housing 30 that houses the.

The semiconductor wafer W is placed on a transport jig 20a on a stage 20, which is composed of an XY stage or the like, which is movable in a horizontal plane. For example, an electron beam sensitive resist or the like is applied to the surface of the semiconductor wafer W.

A lens barrel 36 is located above the stage 20, and an electron beam source 21 is provided at the top of the lens barrel 36 so that an electron beam 21a is emitted toward the semiconductor wafer W. It is configured.

Inside the lens barrel 36, the path of the electron beam 21a from the electron beam source 21 to the stage 20 includes a blanking electrode 22, which controls whether or not the electron beam 21a is emitted.
An irradiation lens 23 that converges the electron beam 21a, through which the electron beam 21a converged by the irradiation lens 23 passes.
For example, a first mask 2 in which a rectangular opening pattern is formed.
4, deflector 25, beam shaping lens 26, second mask 27 in which a desired aperture pattern is formed, this second mask 2
A reduction lens 28 that reduces the cross-sectional shape of the electron beam 21a that has passed through the electron beam 21a, a rotating lens 28a that corrects rotation of the electron beam 21a in the direction around the optical axis, and a projection that focuses the electron beam 21a on the semiconductor wafer W. lens 2
9. An electron optical system including a position deflector 29a for controlling the irradiation position of the electron beam 21a on the semiconductor wafer W is provided.

The interiors of the housing 30 and the lens barrel 36 are evacuated to a desired degree of vacuum by a vacuum pump 31. Further, a part of the housing 30 is provided with a stage drive section 32 that drives the stage 20, a laser length measuring device 33 that precisely measures the amount of displacement of the stage 20, and the like. The structure is such that any part of the semiconductor wafer W can be positioned on the optical axis of the electron optical system provided in the lens barrel 36.

[0049] Also, a part of the housing 30 includes a stage 20.
A well-known vacuum load-lock chamber 34 is connected via a gate valve 35, which allows semiconductor wafers W placed on the housing 30 to be taken in and out of the housing 30 without impairing the degree of vacuum within the housing 30.

In this case, the stage 20 and the transport jig 2
A through window 20b is formed in a part of the mounting area for the semiconductor wafer W at 0a, and the stage 2
0 is composed of a light source 37a that emits a laser beam, an optical system 37b that guides the laser beam to the back surface of the semiconductor wafer W and captures the reflected light, and a sensor 37c that detects the captured reflected light. A reading section 37 is arranged. With such a configuration, the above-mentioned identification information Wa formed on the back side of the semiconductor wafer W to be imaged placed on the stage 20, and the arrangement information Wx of the semiconductor devices X.
, alignment mark M, etc., are optically read by the reading unit 37.

Then, by reading the identification information Wa and the arrangement information Wx recorded on the back surface of the semiconductor wafer W as described above, a control computer (not shown) or the like reads the drawing data and the plurality of semiconductor devices X on the main surface side. Determine the drawing order, drawing conditions, etc.

In addition, when the surface of the semiconductor wafer W is coated with a resist or the like as described above, the position detection accuracy of the alignment marks (not shown) formed on the main surface side of the semiconductor wafer W may be reduced or detected. Although this may cause problems such as difficulty, in the case of this embodiment, the position information of the alignment mark M formed on the back surface of the semiconductor wafer W is compared with the position information of the alignment mark (not shown) on the main surface side. Then, a correction value can be calculated as appropriate, and a pattern can be drawn by correcting the processing position, so that alignment errors caused by the quality of the surface condition of the semiconductor wafer W can be reduced.

As described above, according to the electron beam lithography apparatus of this embodiment, a wealth of information such as the identification information Wa and arrangement information Wx recorded and formed on the back surface of the semiconductor wafer W, as well as the alignment marks M, etc. By reliably reading
The pattern drawing operation can be controlled accurately and efficiently.

[0054]

Embodiment 3 FIG. 5 illustrates a case where a method and apparatus for manufacturing a semiconductor device, which is still another embodiment of the present invention, is applied to an inspection process of a semiconductor wafer W.

Each inspection device T includes an inspection section 40 that performs a functional inspection of individual semiconductor elements (not shown) formed on a semiconductor wafer W using predetermined test data and programs.
, an inspection control section 41 that controls the operation of the inspection section 40 based on the test data and programs stored in the storage section 42 , and a control computer (
CPU) 43. Although not particularly illustrated, the control computer 43 includes a console, a display, and the like that are operated by an operator.

A plurality of inspection devices T having such a configuration are connected to a host computer (CPU) H via a local area network L, and are stored in a data storage section D provided under the host computer H. Stored information such as various test data and test programs can be transferred to the storage unit 42 and used as necessary.

A lot forming section B having the same configuration as in each of the above-described embodiments is connected to the plurality of inspection devices T. In this case, the lot organizing section B collects the identification information Wa and arrangement information Wx recorded and formed on the back surfaces of the plurality of semiconductor wafers W arriving in arbitrary lots k1 and k2 from the previous process from the outside, as well as alignment information. It reads a wealth of information such as the mark M, organizes a lot so as to increase the efficiency of inspection processing of semiconductor wafers W in each inspection device T, and supplies it to the inspection device T. The information is stored in the lot data storage section 14 and accessed by each inspection device.

That is, in a plurality of inspection devices T,
The lot organization information corresponding to the lot k arriving from the lot organization section B is stored in the lot data storage section 1 of the lot organization section B.
4, request the data storage section D for necessary test data and programs, and have them transferred to the storage section 42, thereby avoiding the need to transfer data from the data storage section D more frequently than necessary. A plurality of semiconductor wafers W forming each lot k based on data, programs, etc.
It is possible to perform test processing efficiently.

Furthermore, based on the position information of the alignment mark M read from the back surface of the semiconductor wafer W, the inspection position can be accurately specified regardless of the state of the main surface side of the semiconductor wafer W.

Therefore, the time required for testing is shortened, and the number of semiconductor wafers W that can be tested per unit time can be increased. Furthermore, there is no need to bother the operator each time to manage data transfer, and the number of man-hours required in the testing process can be reduced.

[0061] Above, the invention made by the present inventor has been specifically explained based on practical examples, but the present invention is not limited to the above practical examples, and can be modified in various ways without departing from the spirit thereof. Needless to say, it is.

[0062]

[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions are briefly explained as follows.
It is as follows.

That is, according to the semiconductor device manufacturing method of the present invention, wafer process control in, for example, high-mix low-volume production of semiconductor devices can be efficiently controlled based on the abundant information recorded on the back surface of the semiconductor wafer. The effect is that it can be carried out well and accurately.

Furthermore, according to the semiconductor device manufacturing method of the present invention, wafer process control can be performed, for example, without being affected by the surface condition of the semiconductor wafer, based on the abundant information recorded on the back surface of the semiconductor wafer. This has the effect of being able to carry out tasks efficiently and accurately.

Furthermore, according to the semiconductor device manufacturing apparatus of the present invention, wafer process control in high-mix, low-volume production of semiconductor devices, for example, can be efficiently controlled based on the abundant information recorded on the back surface of the semiconductor wafer. The effect is that it can be carried out well and accurately.

Furthermore, according to the semiconductor device manufacturing apparatus of the present invention, wafer process control can be performed, for example, without being affected by the surface condition of the semiconductor wafer, based on the abundant information recorded on the back surface of the semiconductor wafer. This has the effect of being able to carry out tasks efficiently and accurately.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing main parts when a method and apparatus for manufacturing a semiconductor device of the present invention are applied to an electron beam lithography apparatus.

FIG. 2 is a flowchart when the method and apparatus for manufacturing a semiconductor device, which is an embodiment of the present invention, is applied to forming a metal wiring film or an insulating film.

FIG. 3 is a plan view schematically illustrating an example of the state of a main surface and a back surface of a semiconductor wafer used in a method and apparatus for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device manufacturing apparatus according to another embodiment of the present invention.

FIG. 5 is a block diagram illustrating a case where a method and apparatus for manufacturing a semiconductor device, which is still another embodiment of the present invention, is applied to a semiconductor wafer inspection process.

[Explanation of symbols]

1 Sample stage 2 Electron beam 3 Electron beam source 4 Electron optical system 5 Drawing control section 6 Buffer memory 7 Input/output control section (1/O) 8 Control computer 8a Central processing unit (CPU) 8b Control terminal 9 Data storage section (drawing Data) 10 Interface control unit (1/O) 11 Reading unit 11a Light source 11b Optical system 11c Sensor 12 Signal processing unit 12a Memory 12b Comparator 13 Lot organization control computer (CPU) 13a Central processing unit (CPU) 13b Control terminal 14 Lot Data storage unit 15 Interface control unit (1/O) 20 Stage 20a Transport jig 20b Penetration window 21 Electron beam source 21a Electron beam 22 Blanking electrode 23 Irradiation lens 24 First mask 25 Deflector 26 Beam shaping lens 27 Second mask 28 Reduction lens 28a Rotating lens 29 Projection lens 29a Position deflector 30 Housing 31 Vacuum pump 32 Stage drive section 33 Laser length measuring device 34 Vacuum load lock chamber 35 Gate valve 36 Lens barrel 37 Reading section 37a Light source 37b Optical system 37c Sensor 40 Inspection section 41 Inspection control section 42 Storage section 43 Control computer (CPU) A Electron beam lithography section (processing section) B Lot organization section (recognition section) D Data storage section H Host computer (CPU) M Positioning mark L Local area network P Exposure device T Inspection device W Semiconductor wafer Wa Identification information Wx Array information X Semiconductor device (chip)

Claims (8)

[Claims] 1. At least one of the identification information, process control information, and alignment mark of a semiconductor device formed on the main surface of the semiconductor wafer through a desired process and the identification information of the semiconductor wafer on the back surface of the semiconductor wafer. A method of manufacturing a semiconductor device, characterized in that the semiconductor device is processed and formed as needed, and in the process, at least one of the identification symbol, process control information, and alignment mark is read and used for control management of the process. 2. The identification information processed on the back surface of the semiconductor wafer includes alphanumeric characters, katakana characters, etc.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the vertical and horizontal dimensions of the characters are each about 3 mm or more to make them visible. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the alignment mark processed on the back surface of the semiconductor wafer is used for alignment during transfer of a semiconductor integrated circuit pattern to the main surface. 4. The identification information processed on the back surface of the semiconductor wafer is formed directly behind each of a plurality of semiconductor devices formed at different positions on the main surface, and is formed on the main surface of each semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising array position information on the semiconductor device. 5. Recognizing at least one of the identification information of the semiconductor device, the process control information, the alignment mark, and the identification information of the semiconductor wafer formed on the back surface of the semiconductor wafer on which the semiconductor device is formed on the main surface. a recognition unit that processes or inspects the main surface of the semiconductor wafer; and a processing unit or inspection unit that processes or inspects the main surface of the semiconductor wafer; A semiconductor device manufacturing apparatus characterized in that the processing or inspection operation is controlled based on at least one of information, alignment marks, and identification information of the semiconductor wafer. 6. The recognition unit includes a mechanism for transferring the semiconductor wafers between a plurality of wafer carriers or within a single wafer carrier in which the plurality of semiconductor wafers are respectively housed, 6. The semiconductor device manufacturing apparatus according to claim 5, wherein the rearrangement of the plurality of semiconductor wafers or the order in which the individual semiconductor wafers are supplied to the processing section or the inspection section is controlled based on the identification information. . 7. Identification information of the semiconductor device formed on the back surface of the semiconductor wafer at a stage position where desired processing is performed on the main surface of the semiconductor wafer to form a semiconductor device. and recognition means for recognizing at least one of process control information and alignment marks and identification information of the semiconductor wafer, the identification information of the semiconductor device obtained from the back side of the semiconductor wafer, the alignment marks and A semiconductor device manufacturing apparatus characterized in that the processing is controlled using at least one of the identification information of the semiconductor wafer. 8. The manufacturing device is an exposure device that transfers a semiconductor integrated circuit pattern onto the main surface of the semiconductor wafer, and the semiconductor integrated circuit pattern is transferred using the alignment mark formed on the back surface of the semiconductor wafer. 8. The semiconductor device manufacturing apparatus according to claim 7, further comprising determining or correcting a pattern transfer position.