JP2001168153A - Substrate processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate processing apparatus for processing many substrates one after another whereby the process quality control effectively adapted to a many-model and small-amount production can be performed. SOLUTION: The substrate processing apparatus for applying specified processes to a plurality of semiconductor wafers W one after another comprises an wafer ID reader 5 for reading a substrate's ID designated to each semiconductor wafer W, substrate processing unit means 3, 10, 11, 15 for processing the semiconductor wafers W, based on specified processing conditions, an inspecting range setting unit 46 for previously storing the wafer W inspecting range for inspecting the processing result by the substrate processing units in relation to the wafer ID, and substrate inspecting units 9, 12, 16 for taking out the inspecting range stored by the inspecting range setting unit 46, based on the wafer ID read by the wafer ID reader 5 and inspecting the wafer W about its inspecting range.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a substrate processing apparatus such as a semiconductor device manufacturing apparatus for forming a circuit pattern on a semiconductor wafer.

[0002]

2. Description of the Related Art As is well known, a photolithography technique is used in a semiconductor device manufacturing process. In photolithography technology, a resist solution is applied and formed on the surface of a substrate to be processed such as a semiconductor wafer,
This is exposed to a predetermined pattern and further developed.
Subsequently, a predetermined circuit pattern is formed on the wafer by performing an etching process.

[0003] Generally, the semiconductor wafer is composed of 1
It is supplied in a state where 25 sheets are stored in a cassette.
One lot is taken as a cassette, and one lot is sequentially taken out of the cassette and processed.

[0004]

In the conventional semiconductor device manufacturing apparatus as described above, the minimum unit for managing the wafer processing quality is each lot, and the SEMI, which is a standard of the semiconductor manufacturing apparatus, is not used. Various standards are defined assuming management on a lot basis.

[0005] However, in the near future, demand for high-mix low-volume production is expected to increase sharply. In this case, the management of one lot may be too large. Particularly, in the case of a large wafer such as a 300 mm size, since a very large number of semiconductor chips can be obtained from one wafer, it is possible to support a large number of types with one cassette. In some cases, the process conditions must be changed.

However, in the conventional apparatus, the minimum unit of process management is one lot, that is, one cassette unit, and it is difficult to meet such a demand.

[0007] In particular, in the case where the types manufactured in units of one wafer to several wafers in one cassette are different, it may not be possible to perform an inspection using a dummy wafer or the like for each type. For this reason, in the case of high-mix low-volume production as described above, an actual wafer (Act for acquiring product chips) is used.
Inspection using a ual wafer) is required.

The present invention has been made in view of such circumstances, and in a substrate processing apparatus that sequentially processes a large number of substrates one by one, it is possible to perform process quality management effectively corresponding to high-mix low-volume production. It is an object to provide a substrate processing apparatus.

[0009]

According to a first aspect of the present invention, there is provided a substrate processing apparatus for sequentially performing a predetermined processing on a plurality of substrates to be processed,
A substrate ID reading unit that reads a unique substrate ID provided on each of the substrates to be processed, a substrate processing unit that processes the substrate to be processed based on predetermined process conditions, and inspects a processing result by the substrate processing unit. Inspection range storage means for storing an inspection range of the substrate to be processed in advance in association with the substrate ID, and an inspection stored by the inspection range storage means based on the substrate ID read by the substrate ID reading means. A substrate processing apparatus comprising: a substrate inspection unit that extracts a range and inspects a substrate to be processed in the inspection range.

According to such a configuration, in an apparatus for sequentially processing a plurality of substrates, for example, a substrate processing apparatus for performing photolithography processing on a semiconductor wafer, different inspection ranges can be set for each substrate to be processed. . Therefore, it is possible to effectively cope with a case where the type and process conditions to be manufactured in units of one to several sheets are changed and the inspection range of the inspection apparatus is changed accordingly.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor wafer processing apparatus according to an embodiment of the present invention will be described below.

FIG. 1 is a schematic diagram showing the overall configuration of the semiconductor wafer processing apparatus 1, and FIG. 2 is a block diagram showing the system configuration.

The semiconductor wafer processing apparatus 1 includes, for example,
It comprises a coating and developing device 2 and an exposure device 3 (DEV).
In the figure, an arrow (α) indicates a flow of a semiconductor wafer W (hereinafter, referred to as “wafer”) in the processing apparatus 1.

That is, first, in the coating and developing apparatus 2, the wafers W are sequentially taken out from a cassette CR in which 25 wafers 300 of 300 mm size are stored, for example. The unloading of the wafer W is performed by a sub-arm (not shown), and then the wafer W is transferred to a main arm (not shown) and transported along a predetermined path α.

The wafer W taken out of the cassette CR
The wafer ID is read by a wafer ID (recognition code) reading unit (LD) indicated by 5 in FIG. The wafer ID is formed, for example, along the edge where the orientation flat 7 is formed, as shown by 6 in FIG.
TITLE (not shown) provided separately from
R).

Next, the wafer W is passed through a base reflectance inspection apparatus 9. The base reflectance is an important parameter that affects the resist film thickness and the amount of exposure. Thereafter, the wafer W is coated with a resist liquid by the resist liquid coating unit 10 (COT). This resist liquid application unit 1
At 0, the wafer W is held on a spin chuck (not shown), and a predetermined minute amount (for example, 4
ml) of the resist solution. Next, the spin chuck is rotated and the wafer W is rotated at a high speed, so that the resist liquid is diffused to spread over the entire surface of the wafer W by centrifugal force. Here, the thickness of the resist solution can be controlled by the rotation speed (rotation speed) of the resist solution diffusion of the wafer W, which is one of the process conditions. In order to satisfy the demand for thin film, there is a tendency to increase the speed.

The resist solution coating unit 10 (CO
The wafer W taken out of T) is placed in the heating unit 11
(HP), the solvent is volatilized from the resist solution, and the resist solution is dried. Since the volatilization amount of the solvent has a very large effect on the thickness of the formed resist film, the temperature, humidity and heating time of the inside of the heating unit 11 are very important process conditions.

Thereafter, the wafer W is cooled by a cooling unit (not shown), and unnecessary resist on the peripheral portion is removed by a peripheral resist removing device (not shown). Before or after the peripheral resist removing device or inside the peripheral resist removing device, a film thickness inspection device 12 for detecting a resist film thickness is provided.

After the thickness of the resist film is detected, the wafer W is transferred to the exposure apparatus 3 (EXP). The exposure apparatus 3 irradiates a resist film formed on the wafer W with exposure light through a predetermined pattern of an exposure mask, and transfers a mask pattern of the exposure mask to the resist film on the wafer W. In this exposure apparatus, important process conditions include the focal length, the position of the wafer, the intensity of the exposure light, and the exposure time.

The wafer W after the exposure is returned to the coating and developing apparatus 2 again, and is subjected to a so-called post-exposure bake for reducing the deformation of the resist pattern due to the heat treatment and the standing wave effect. It is introduced into the development processing unit 15 (DEV) via the sub arm and the main arm. This development processing is performed, for example, according to a paddle method. In the paddle method, the developing process is performed by filling the developing solution on the wafer W for a predetermined time. Of the process conditions of the developing unit 15, the developing solution discharge speed and the liquid filling time greatly affect the development progress. Then, immediately after a predetermined liquid filling time has elapsed, pure water is sprayed onto the wafer W immediately, and the developing solution is washed away, thereby stopping the development.

The wafer W after the development processing is heated and dried and then discharged to the cassette CR. Before that, the wafer inspection apparatus 16 inspects the defect inspection apparatus 16 for the presence of a serious defect. The defect inspection device 16 includes, for example, a defocus inspection for detecting a pattern displacement generated in the exposure device 3, a development defect detection inspection for detecting a defect in a development process, and a scratch for detecting a minute flaw generated on the surface of the wafer W. Detection inspection, particle detection inspection for detecting particles attached to the wafer W, comet detection inspection for detecting the comet generated by bubbles or foreign matter in the resist solution on the surface of the wafer W after resist application, and the comet from the surface of the wafer W A splash back detection inspection for detecting a splash back in which the solvent of the resist solution is re-adhered to the wafer W, a common defect detection inspection for detecting a common defect appearing in the same shape on the same position on the surface of the wafer W, Scum detection inspection to detect remaining resist residues, wafers before photolithography process By holding (clamping) the edges, NO detects that not clamped ring test to detect the scar remaining in wafer edge, resist coating processing and developing treatment RESIST, NO DEVEL
OP inspection, line width measurement inspection for measuring the line width of the resist film formed on the wafer W, inspection for comparing the overlay accuracy of the wafer W and the photomask exposed by the exposure apparatus 3 with a standard value. It is configured such that all or a part of the inspection such as the overlay inspection can be selectively performed. The defect inspection apparatus 16 can also perform a coating unevenness detection inspection for detecting coating unevenness of a resist solution after resist coating. ,

These series of inspections are divided into a macro inspection and a micro inspection.
The micro inspection can detect a defect of 0.1 μm or more, for example, in a micro inspection.

Next, a control system of the semiconductor wafer processing apparatus will be described.

First, as shown in FIG. 1, this apparatus comprises a control unit 20 for each processing unit connected to each of the processing units (10, 11, 15) and an inspection apparatus (9, 1).
A control unit 21 for each inspection device connected to (2, 16);
The control unit 22 for the exposure apparatus connected to the exposure apparatus 3
And a central control unit 23 to which the control units 20, 21, and 22 are connected, and an information storage unit 24 and a control program storage unit 25 connected to the central control unit 23.

FIG. 2 is a block diagram for explaining this system in more detail.

The central control unit 23 has, for example, an input unit 27, a CPU 28, a RAM 29 and a display unit 30,
The information storage unit 24 and the control program storage unit 25 are connected to a bus 31 to which these are connected. These storage units may be, for example, fixed storage devices such as hard disks, but the form is not particularly limited.

The input section 27 and the display section 30 are connected to, for example, an operation panel provided on the front surface of the coating and developing apparatus 2, and a wafer processing recipe (process condition) is input through the input section 27 and the display section 30. ) Is input and set. The recipe is a whole recipe and each processing unit (10, 11, 15,
3) A recipe for each inspection apparatus (9, 12, 16), and a recipe for each processing unit and each inspection apparatus, that is, setting of process conditions, is set for each processing unit 10, 11, 15 through the operation panel. , Every three.

The information storage unit 24 includes a recipe-process ID storage unit 33 for storing a recipe (process condition) of each processing unit in association with a process ID, an entire recipe storage unit 34 for storing the entire recipe, a wafer A wafer ID for storing the ID and the processing history information of the wafer; a processing history information storage unit 35; and a wafer ID for storing the wafer ID in association with an inspection result by an inspection apparatus described later.
The inspection result information storage unit 36 stores a wafer ID and a wafer ID that stores the wafer ID and the inspection range referenced by the ID in association with each other
And an inspection range storage unit 37.

The process ID is a unique code for identifying the processing unit, each inspection device and its process conditions. The overall recipe is a combination of the recipes of the respective processing units as described above, and is specified by the combination of the process IDs. This whole recipe may be stored in association with the wafer ID.

The inspection range is set according to the type of product, for example, according to the user's request. In this embodiment, the base reflectance inspection, the resist film thickness, the oxide film, the interlayer insulating film, the wiring width Set for inspection of each interval, inspection of overlay, defect, and defocus. Taking the base reflectivity, the resist film thickness, the oxide film, and the interlayer insulating film as examples, it is formed at a predetermined position in a part of a scribe line (Scribe Line) in a peripheral portion of the chip (between the chips). An inspection mask pattern is used. Also, the condition of the mask pattern is a condition pattern (layout pattern) that is the worst (user / manufacturer arbitrary designation) from the process (mask rule). The inspection location is represented by an XY coordinate system, and is stored in association with the wafer ID.

The control program storage section 25 includes a recipe-process ID setting section 38 and an overall recipe setting section 39.
A wafer processing execution command section 40, a wafer ID-processing history storage command section 41, a wafer ID-inspection result storage command section 42, a wafer ID-various information output command section 43, a process condition evaluation section 44, It has a process condition correction unit 45 and a wafer ID-inspection range setting unit 46.

The recipe-process ID setting unit 38 includes:
A recipe (process condition) input for each of the processing units 10, 11, 15, and 3 is assigned a process ID and stored in the recipe-process ID storage unit 33. The whole recipe setting section 39 sets the whole recipe of the wafer processing as a combination of the process IDs and stores it in the whole recipe storage section 34. The wafer processing execution command unit 40 includes:
Based on the overall recipe, each of the processing units 10, 1
1, 15, 3 control units 20, 21 and each inspection device 9, 1
A command is issued to the control units 22 and 16 to perform wafer processing and inspection according to the process conditions referred to by the process ID.

The wafer ID / processing history storage command section 41 receives the wafer ID from the wafer ID reading device 5 and sends the wafer ID to each of the processing units 10, 11, 16 and the inspection devices 9, 1.
The wafer IN / OUT information is received from each of the wafer IDs 2 and 16 and stored in the wafer ID-processing history information storage unit 25 as history information. Further, the wafer ID-inspection result storage command unit 42 stores the inspection result in each inspection apparatus in the wafer ID-inspection result storage unit 36 in association with the wafer ID. The wafer ID-various information output command unit 43 converts the information stored in the information storage unit 24 in association with the wafer ID into, for example, the process condition evaluation unit 4.
4 is output. The process condition evaluation unit 44 evaluates a process condition in each processing apparatus referred to in the processing history of the wafer based on the inspection result. The process condition correction unit 45 corrects the process condition if necessary based on the evaluation result.

The wafer ID-inspection range setting section 46 includes:
The inspection range in each of the inspection devices 6, 12, 16 is set in association with the wafer ID. For example, the coordinates of a mask pattern formed on a scribe line are specified. Inspection locations are, for example, at least two locations in the base reflectance inspection,
In the inspection of the resist film thickness, it is preferable to set at least one position.

As shown in the figure, the wafer ID reading device 5, the control unit 20 of each of the processing units 10, 11, and 15, the control unit 21 of each inspection device, and the control unit 22 of the exposure device 3 It is connected to the bus 31 via an interface (not shown).

Next, the operation of the substrate processing apparatus 1 will be described.

First, a processing recipe for the wafer W is set.
That is, the recipe in each of the processing units 10, 11, 15, and 3, and the overall processing recipe are set. A recipe for each processing unit is assigned a process ID, and the entire recipe is referred to by the combination of the process IDs. The entire recipe may be stored in advance in association with a known wafer ID.

Further, each of the inspection devices 9, 12, 1
The inspection range in No. 6 is set in association with the wafer ID. That is, an arbitrary coordinate on the wafer W, for example, along a scribe line is specified through, for example, the operation panel.

Next, the coating and developing device 2 and the exposure device 3 are operated based on the entire recipe, and the processing of the wafer is started. That is, the wafer W is taken out from the cassette CR, and the wafer ID is read by the wafer ID reading device. Then, each processing unit 10, 11, 1
Steps 5 and 3 sequentially process wafers based on the process conditions referred to by the process ID. Here, when the whole recipe is associated with the wafer ID, the whole recipe is specified from the wafer ID, and the process ID is extracted from the whole recipe.

Each of the inspection devices 9, 12, and 16 also operates based on the process conditions to inspect the wafer W. At this time, the control unit 22 of the inspection apparatus acquires an inspection range from the wafer ID-inspection range storage unit and performs inspection of the inspection range.

Each of the processing units 10, 11, 15, and 3 and the inspection devices 9, 12, and 16 cause the I
An N signal is issued, and when the wafer processing is completed and the wafer is ejected, an OUT signal is issued. This IN / OUT information is associated with the wafer ID, and is acquired as history information together with the process ID. Further, the inspection results by the inspection devices 9, 12, and 16 are also stored in association with the wafer ID.

When a series of processing of the wafer W is completed,
Various kinds of information referred to by the wafer ID of the wafer W are output according to a command from the wafer ID-various information output command unit 43.

The evaluation section 44 receives the output information and evaluates the process conditions in each of the processing units 10, 11, 15, and 3. For example, when a defect is detected by the defocus inspection, the line width measurement inspection, and the overlay inspection in the defect inspection device 16, the process condition of the exposure device 3 is evaluated as inappropriate. For example, when a position shift equal to or more than a predetermined threshold value of the pattern is detected by the defocus inspection, the focusing performed by the exposure device 3 is evaluated as inappropriate. In addition, when a pattern shift of a predetermined value or more is detected by the defocus inspection, the focusing performed by the exposure device 3 is evaluated as inappropriate.

When the evaluation section 44 outputs such an evaluation, the process condition correction section 45 corrects the process conditions of each processing unit to be evaluated based on the evaluation. For example, in the above case, the process condition of the exposure apparatus 3, that is, the exposure condition is corrected. The corrected process conditions are stored in the recipe-process ID storage unit 33.

Therefore, after this, the same process ID
The corrected process conditions are applied to the wafer W processed with reference to FIG.

According to such a configuration, in a semiconductor device manufacturing apparatus which has a plurality of processing units and sequentially performs a predetermined process on a semiconductor wafer, an individual wafer ID is read, and various information relating to the processing of the wafer is read. Is the wafer I
D is stored and output. Further, each inspection range can be specified for each wafer W based on the wafer ID. According to such a configuration, it is possible to manage the processing in wafer units, not in lot units. Therefore, there is an effect that a processing apparatus suitable for high-mix low-volume production can be constructed.

Further, based on the inspection result associated with the wafer ID, the same process condition of the wafer is appropriately evaluated and corrected if necessary. This process condition is overwritten and stored in association with the process ID.
As a result, the corrected process conditions are applied to the processes that refer to the same process ID. Further, as described above, since an appropriate inspection range can be individually specified for each wafer W, the reliability of the inspection result and the correction result is high. According to such a configuration, it is possible to evaluate and correct the process conditions each time the wafer is processed, so that there is an effect that the quality can be easily ensured in small-scale production of many kinds.

The present invention is not limited to the above-described embodiment, but can be variously modified without changing the gist of the invention.

For example, in the above-described embodiment, as the processing units of the coating and developing apparatus 2, only the resist liquid coating unit 10, the heating unit 11, and the developing processing unit 15 are shown for convenience of explanation, but the present invention is not limited to this. Instead, various processing units including a transport system are actually provided. Then, the same control, process condition setting, evaluation and correction are performed on these various processing units.

In the above embodiment, the inspection devices 9, 12, and 16 are connected in-line in the device. However, the inspection devices 9, 12, and 16 may be placed outside the substrate processing apparatus 1.

Further, in the above embodiment, the evaluation and correction results of the process conditions are used only by one processing apparatus 1, but the present invention is not limited to this. As shown in FIG. 4, various types of information, process condition evaluations, and process condition correction results associated with wafer IDs obtained by one processing apparatus are transferred to another processing apparatus 1 'for use. Is also good. In this case, it is preferable that the information storage unit 24 is shared.

According to such a configuration, when the same wafer processing is performed in parallel by a plurality of processing apparatuses, the processing quality can be more effectively improved.

Further, in the above embodiment, Actua
l Scribe Li at the periphery of the chip on the wafer
Inspection is performed using a mask pattern that uses a part of ne. However, the present invention is not limited to this. Measurement pattern (TEG) with embedded test pattern
Alternatively, a mark for superposition may be used in addition to a confirmation mark (alignment mark) for position correction at the time of exposure.

[0054]

As described above, according to the present invention, in a substrate processing apparatus for sequentially processing a large number of substrates, there is provided a substrate processing apparatus capable of performing process quality control effectively corresponding to high-mix low-volume production. You can do it.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a substrate processing apparatus according to an embodiment of the present invention.

FIG. 2 is also a system configuration diagram.

FIG. 3 is a perspective view for explaining a relationship between a wafer and a wafer ID.

FIG. 4 is a schematic configuration diagram showing a modification.

[Explanation of symbols]

W: semiconductor wafer CR: cassette α: wafer transfer path 1: semiconductor wafer processing device (substrate processing device) 2: coating / developing device (substrate processing device) 3: exposure device (substrate processing device) 5: ID reader (substrate) 7: Orientation flat 9: Base reflectance inspection device (substrate inspection device) 10: Resist liquid application unit (substrate processing device) 11: Heating unit (substrate processing device) 12: Film thickness inspection device (substrate inspection device) 15: Development processing unit (substrate processing means) 16: Defect inspection device (substrate inspection means) 16: Development processing unit (substrate processing means) 20: Control unit of each processing unit 21: Control unit of each inspection device 22: Exposure Device control unit 23 Central control device 24 Information storage unit 25 Control program storage unit 27 Input unit 28 RAM 29 CPU 30 Display unit 31 bus 33 recipe-ID storage unit (process condition storage unit) 34 entire recipe storage unit 35 wafer ID-processing history information storage unit 36 wafer ID-inspection result information storage unit 37 wafer ID-inspection Range storage unit 38 Recipe-process ID setting unit (process condition storage unit) 39 Overall recipe setting unit 40 Wafer processing execution command unit 41 Wafer ID-processing history storage command unit 42 Wafer ID-inspection result storage command unit 43: Wafer ID-various information output command unit 44: Process condition evaluation unit (evaluation unit) 45: Process condition correction unit (correction unit) 46: Wafer ID-inspection range setting unit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kunie Ogata 5-3-6 Akasaka, Minato-ku, Tokyo Tokyo Electron Limited F-term (reference) 4M106 AA01 CA38 DJ21 DJ38 DJ40 5F046 AA18 DA29 DD03 JA22 JA27 LA18

Claims (2)

[Claims] 1. A substrate processing apparatus for sequentially performing a predetermined processing on a plurality of substrates to be processed, wherein: a substrate ID reading unit configured to read a unique substrate ID provided on each of the substrates to be processed; Substrate processing means for processing a substrate based on predetermined process conditions; and inspection range storage means for storing an inspection range of the substrate to be processed for inspecting a processing result by the substrate processing means in advance in association with the substrate ID. A substrate inspection unit that extracts an inspection range stored by the inspection range storage unit based on the substrate ID read by the substrate ID reading unit, and inspects a substrate to be processed in the inspection range. Substrate processing equipment. 2. The substrate processing apparatus according to claim 1, wherein the substrate processing unit has a plurality of processing units for sequentially performing different processing on a substrate to be processed. A substrate processing apparatus comprising one or more substrate inspection units useful for inspecting a processing result by one or more arbitrary processing units among the plurality of processing units.