JP2874714B2 - Semiconductor analysis / processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor analysis / processing apparatus, and more particularly, to means for relatively moving an analysis / processing section of a semiconductor analysis / processing apparatus to a target portion of a semiconductor integrated circuit. The present invention relates to a semiconductor analysis / processing apparatus having features.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor analyzing / processing apparatus such as an EB (electron beam) tester, an excimer laser, and an FIB (focus ion beam), an analyzing / processing unit such as an EB gun and a lens is used at the time of analysis / processing. And moving relative to a semiconductor integrated circuit placed on a stage (table), aligning a lens point of an analysis / processing unit with a target position of the semiconductor integrated circuit, and performing analysis / processing. ing. In the case of the EB tester, the sample stage is fixed and the lens (gun) moves. In the case of excimer laser and FIB, the lens (gun) is fixed and the sample stage moves. Therefore, the conventional semiconductor analysis / processing apparatus has an automatic search and movement system for automatically searching for the target position of the semiconductor integrated circuit and relatively moving the lens point to the target position of the semiconductor integrated circuit. .

In this type of conventional automatic search and move system, search and move to a target location on an LSI chip when performing LSI failure analysis and the like are performed as follows.

First, layout data and dimensions of a semiconductor integrated circuit, a minimum grid interval, interlayer connection information, and the like are input to a CAD tool to perform preprocessing, link an actual chip with layout information, and link a target location on the layout data. Is designated, the automatic search and movement system automatically searches for a target location of the semiconductor integrated circuit and moves the lens point to the same location on the LSI chip.

[0005]

A first problem of the prior art is that it is difficult to reduce the time required for searching for a target portion, including the preprocessing time.

[0006] As a circuit becomes large-scale and highly integrated, the amount of data handled in a link system with layout data and a circuit diagram becomes enormous, and in some cases, a pre-processing time may take one day or more. This is because processing may not be possible depending on the machine environment or the like.

The memory capacity and disk capacity required for pre-processing are, for example, several hundreds to 1 G with a gate array of several hundred kilogates.
Requires bytes.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor analysis / processing apparatus which can speed up the search and movement of a target portion on an LSI chip, including the preprocessing time.

Another object of the present invention is to provide a semiconductor analysis / processing apparatus capable of greatly reducing the amount of data handled when searching for a target portion on an LSI chip.

[0010]

According to the first aspect of the present invention, there is provided a semiconductor analyzing / processing apparatus for analyzing / processing a semiconductor integrated circuit on which a marking as position information is formed, wherein the semiconductor integrated circuit includes: , And an analysis / processing for analyzing / processing the semiconductor integrated circuit on the table.
Processing means, reading means for reading position information near a target location on a layout drawing or the like, and automatically searching for a marking formed near the target location on the semiconductor integrated circuit based on the position information, and performing the analysis / processing. A semiconductor analyzing / processing apparatus characterized by having a search / moving means for relatively moving means to the marking.

According to a second aspect of the present invention, there is provided a library for comparing position information near a target location on the layout drawing or the like with actual position information on the semiconductor integrated circuit. A semiconductor analysis / processing apparatus according to claim 1 is obtained.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

First, a semiconductor integrated circuit analyzed / processed by the semiconductor analyzing / processing apparatus according to the embodiment of the present invention shown in FIGS. 1 to 3 will be described.

FIG. 4 is a plan view of a main part of a first example of a semiconductor integrated circuit analyzed / processed by the semiconductor analyzing / processing apparatus of the present invention, FIG. 5 is an enlarged view of a portion A in FIG. 4, and FIG. A in FIG.
It is sectional drawing in the -A 'line.

Referring to FIGS. 4 to 6, 1-1,1-
Reference numerals 2 and 1-3 indicate first wiring layers, respectively.
-2, 2-3, and 2-4 indicate first through holes, respectively, and 3-1 indicates a second wiring layer (power supply line).
3-3 and 3-4 respectively indicate a second wiring layer (signal line), 4-1 indicates a third wiring layer (power supply line), and 4-2 indicates a third wiring layer (signal line). Reference numeral 5 denotes a target portion (failure portion), and 6-1 denotes a bar code pattern formed by an antireflection film on grid points of power supply lines arranged in a grid. This barcode pattern contains location information (for example,
Actual size coordinates or XY coordinates).

As is apparent from FIG. 6, reference numeral 8 denotes an insulating interlayer film formed between the second wiring layer 3 and the third wiring layer 4, and reference numeral 7 denotes a cover film covering the third wiring layer 4.

FIGS. 7A to 7E are cross-sectional views showing respective steps for forming a barcode of the semiconductor integrated circuit shown in FIGS.

First, FIG. 7A is a cross-sectional view immediately after the third wiring layer is formed, and 6-2 shows an antireflection film before patterning.

FIG. 7B shows a state in which a photoresist 9 for forming a bar-coded anti-reflection film 6-1 is formed on the anti-reflection film 6-2 as a mask.

FIG. 7C shows that the anti-reflection film 6-2 is etched using the photoresist 9 as a mask to form a bar-coded anti-reflection film 6-1.

FIG. 7D shows the photoresist 9 removed.

FIG. 7E shows that the cover film 7 is formed on the bar-coded antireflection film 6-1.

Thus, the semiconductor integrated circuit shown in FIGS. 4 to 6 is obtained.

Next, a second example of a semiconductor integrated circuit analyzed / processed by the semiconductor analysis / processing apparatus of the present invention will be described in detail with reference to the drawings.

FIG. 8 is a sectional view of a second example of a semiconductor integrated circuit analyzed / processed by the semiconductor analyzing / processing apparatus of the present invention, and is a cross-sectional view at the same portion as FIG.

Referring to FIG. 8, reference numeral 4-3 denotes a third wiring layer 4--3.
1 shows a barcode pattern formed. In the first example of the semiconductor integrated circuit described above, the bar code pattern is formed by patterning the wiring of the third wiring layer and then patterning the antireflection film again. In this example, when patterning the wiring of the third wiring layer, a bar code pattern 4-3 is formed on the third wiring layer at the same time.

The semiconductor integrated circuit of this embodiment has an effect that the manufacturing process can be shortened as compared with the semiconductor integrated circuit of the first embodiment.

FIG. 1 shows an EB according to a first embodiment of the present invention.
FIG. 9 is a flow chart when the automatic search and move system of the tester automatically searches and moves to a target location using the semiconductor integrated circuit of the first or second example.

In the present embodiment, first, the analysis / processing operator causes the EB tester to read a bar code pattern near a target location on a layout drawing or the like using a laser scanner or the like (not shown). Then, the automatic search and movement system searches for the same bar code pattern on the actual chip and automatically moves.

FIG. 2 shows an EB according to a second embodiment of the present invention.
FIG. 9 is a flow chart when the automatic search and move system of the tester automatically searches and moves to a target location using the semiconductor integrated circuit of the first or second example.

In the present embodiment, first, as in the embodiment shown in FIG. 1, the EB tester reads a bar code pattern near a target location such as a layout drawing using a laser scanner or the like. Then, the library refers to a library that compares the position information (coordinate information) held by the barcode pattern prepared in advance with the position information (coordinate information) on the actual chip, and automatically determines the origin position on the chip. It is made to move.

FIG. 3 shows an EB according to a third embodiment of the present invention.
FIG. 9 is a flow chart when the automatic search and move system of the tester automatically searches and moves to a target location using the semiconductor integrated circuit of the first or second example.

In the present embodiment, first, as in the embodiment shown in FIGS. 1 and 2, the EB tester reads a barcode pattern near a target location such as a layout drawing using a laser scanner or the like. Then, the automatic search and movement system reads the barcode near the current position on the actual chip, refers to the coordinate information library, calculates the relative positional relationship between the two, and automatically moves to the target.
The coordinate information library has, as XY table coordinate information, bar code patterns and actual size coordinates of chips or grid point coordinates of power supply lines.

Although the size of the coordinate information library depends on the number of power supplies, the size of the coordinate information library is extremely small as compared with layout data and the like, and the amount of data is greatly reduced.

Although the first to third embodiments are directed to an automatic search / movement system of an EB tester, the present invention is not limited to this. Of course, the present invention is not limited to this. It is also applicable to the automatic search and movement system.

[0036]

As described above, according to the semiconductor analyzing / processing apparatus of the present invention, it is possible to greatly reduce information necessary for searching and moving a predetermined position (marking position) of a semiconductor integrated circuit. it can.

Therefore, according to the semiconductor analyzing / processing apparatus of the present invention, the search and movement of the semiconductor integrated circuit to the target location can be performed much faster and more accurately than in the past.

[Brief description of the drawings]

FIG. 1 is a flowchart for automatically searching and moving to a target location using the semiconductor integrated circuit shown in FIG. 4 to FIG. 6 or FIG. 8 in the EB tester automatic search and movement system according to the first embodiment of the present invention; It is.

FIG. 2 is a flowchart for automatically searching and moving to a target location using the semiconductor integrated circuit shown in FIG. 4 to FIG. 6 or FIG. 8 in the EB tester automatic search and movement system according to the second embodiment of the present invention; It is.

FIG. 3 is a flowchart for automatically searching and moving to a target location using the semiconductor integrated circuit shown in FIG. 4 to FIG. 6 or FIG. 8 in the EB tester automatic search and movement system according to the third embodiment of the present invention; It is.

FIG. 4 shows the analysis / processing performed by the semiconductor analysis / processing apparatus of the present invention.
FIG. 3 is a plan view of a main part of a first example of a semiconductor integrated circuit to be processed.

FIG. 5 is an enlarged view of a portion A in FIG. 4;

FIG. 6 is a sectional view taken along line AA ′ of FIG. 5;

7 (a) to 7 (e) are cross-sectional views in respective steps for forming a bar code of the semiconductor integrated circuit shown in FIGS. 4 to 6. FIG.

FIG. 8 shows the analysis / processing performed by the semiconductor analysis / processing apparatus of the present invention.
FIG. 9 is a cross-sectional view of a second example of a semiconductor integrated circuit to be processed;
FIG. 7 is a cross-sectional view of the same part as in FIG. 6.

[Explanation of symbols]

 1-1 First Wiring Layer 1-2 First Wiring Layer 1-3 First Wiring Layer 2-1 First Through Hole 2-2 First Through Hole 2-3 First Through Hole 2-4 First Through Hole 3 -1 2nd wiring layer (power supply line) 3-2 2nd wiring layer (signal line) 3-3 2nd wiring layer (signal line) 3-4 2nd wiring layer (signal line) 4-1 3rd wiring layer (Power supply line) 4-2 Third wiring layer (signal line) 4-3 Barcode pattern formed on third wiring layer 5 Target location (defect location) 6-1 Barcode pattern formed on antireflection film 6-2 Anti-reflection film (before patterning) 7 Cover film 8 Insulating interlayer film 9 Photoresist

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-315207 (JP, A) JP-A-5-175093 (JP, A) JP-A-4-288811 (JP, A) 171709 (JP, A) JP-A-4-334010 (JP, A) JP-A-4-340214 (JP, A) JP-A-6-204101 (JP, A) JP-A-5-313350 (JP, A) JP-A-5-109591 (JP, A) JP-A-3-95628 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name)

Claims (2)

(57) [Claims] 1. A semiconductor analysis / processing apparatus for analyzing / processing a semiconductor integrated circuit on which marking as position information is formed, comprising: a table for holding the semiconductor integrated circuit; and the semiconductor integrated circuit on the table. And reading means for reading position information near a target location on a layout drawing or the like, and automatically searching for a marking formed near the target location on the semiconductor integrated circuit based on the position information. And a searching / moving means for relatively moving the analyzing / processing means to the marking. 2. The semiconductor analysis device according to claim 1, further comprising a library for comparing position information near a target point on the layout drawing or the like with actual position information on the semiconductor integrated circuit. / Processing equipment.