JP5621395B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device , for example, a means for eliminating the need for non-product chips used for position reference in a semiconductor wafer.

  Conventionally, after completing the primary test (PT) in the wafer state of the semiconductor wafer, the divided semiconductor chips are divided into individual pieces by the dicing process, and only the semiconductor chips determined to be non-defective products in the primary test are picked up. Die bonding.

  Here, a manufacturing process of a conventional semiconductor device will be described with reference to FIGS. FIG. 18 is an explanatory view of a wafer process in a conventional method for manufacturing a semiconductor device. As shown in FIG. 18A, a reference is set at a predetermined position of a wafer reticle 51 in which semiconductor chip patterns 52 are arranged in a matrix. A chip pattern 53 is set. The setting position of the reference chip pattern 53 is arbitrary, but is usually arranged at a corner. The reference chip pattern 53 has a specific circuit pattern different from a normal product chip.

  Next, as shown in FIG. 18B, the pattern of the wafer reticle 51 is printed on the entire surface of the semiconductor wafer 60 by step-and-repeat. FIG. 18C is a conceptual plan view of the semiconductor wafer 60 on which the pattern of the wafer reticle 51 is baked.

  FIG. 19 is a plan view showing the relationship between the wafer and the reference chip, and the reference chip 61 is printed at the corner of each transfer unit. In the figure, a chip effective area for the reference chip 61 in the wafer 60 is determined as indicated by a stepped thick line frame.

FIG. 20 is an explanatory diagram of a method for determining a reference chip and a chip effective area in the wafer primary test. First,
a ₁ . Alignment is performed so that a notch 63 formed in advance in the wafer 60 for alignment is positioned in front of the wafer 60 (just below in the drawing) in the primary test apparatus. Then
b ₁ . The wafer center is obtained from arbitrary three points A, B, and C around the wafer 60. Then
c ₁ . Move to the preset coordinates from the wafer center to obtain the upper left reference chip. Then
d ₁ . The effective area for performing the primary test is identified by the effective area information for the reference chip 61 set in the wafer process.

  FIG. 21 is an explanatory diagram of the wafer primary test and PTMAP. As shown in FIG. 21A, the primary test is performed on all the semiconductor chips 62 in the effective area of the wafer 60. In the drawing, a state is shown in which three semiconductor chips arranged vertically are tested using one probe card 64 at the same time.

  FIG. 21B is a conceptual explanatory diagram of PTMAP. As a result of the primary test, the non-defective chip 65 determined to be non-defective and the defective chip 66 determined to be non-defective are mapped to create a PTMAP. At this time, the reference chip 61 having a circuit pattern different from the product chip is mapped as a defective chip.

FIG. 22 is an explanatory diagram of the state of the wafer in the dicing process, and shows a state in which the semiconductor wafer 60 is supported on the wafer support sheet 71 fixed to the wafer ring 70. First,
a ₂ . In the dicing apparatus, alignment is performed so that the notch 63 of the semiconductor wafer 60 comes to the front. Then
b ₂ . Horizontal indexing is performed from any two semiconductor chips A and B arranged in the same row, and the angle deviation θ of the semiconductor wafer 60 is corrected by the alignment device. Then
c ₂ . Dicing is performed in order from the end of the semiconductor wafer 60.

  The dicing length is set so as to cut about 3 mm longer on one side than the wafer size so as to cover the entire semiconductor wafer 60 (round cut). In addition, in order to perform position correction, there is a case where the set semiconductor chip is subjected to extra dicing by one line in the vertical and horizontal directions in consideration of misrecognition of one line deviation from the actual semiconductor chip.

  FIG. 23 is an explanatory diagram of a specific dicing process. The rotary dicing blade 72 is used to cut the semiconductor wafer 60 supported on the wafer support sheet 71 fixed to the wafer ring 70 in order from the end. To go.

  FIG. 24 is an explanatory diagram of the collating process with PTMAP in the die bonding process. Here, the reference chip 61 on the semiconductor wafer 60 and the reference chip on PTMAP are collated, and only the product chip corresponding to the non-defective chip 65 as a result of the primary test is picked up, and die bonding is performed. The reference chip 61 is not picked up because it is regarded as a defective chip on PTMAP.

  FIG. 25 is an explanatory diagram of a specific die bonding process. As shown in FIG. 25A, the expanding jig 81 is raised with respect to the wafer ring 70 that supports the semiconductor wafer 60 that has been diced. The wafer support sheet 71 is extended. Alternatively, the wafer ring 70 may be lowered with respect to the expanding jig 81.

  As shown in FIG. 25 (b), when the wafer support sheet 71 is extended, the distance between the dicing lines is increased and the semiconductor chips 62 are separated from each other. In this way, in the state in which the wafer support sheet 71 is extended, the wafer center position and the position of the reference chip 54 cannot be specified from arbitrary three points of the semiconductor wafer 60.

  Next, as shown in FIG. 25C, the non-defective chip 65 to be picked up is pushed up by the push-up needle 82 and the suction collet 83 is lowered to suck the non-defective chip 65 by vacuum suction. To raise. Thereafter, it is die-bonded as it is or accommodated in a transfer tray.

FIG. 26 is a flowchart summarizing the manufacturing process of the conventional semiconductor device described above.
s ₁ . In the wafer process, the reticle pattern is printed on the entire surface of the wafer by step and repeat. At this time, a reference chip pattern is applied to the effective chip area in the reticle. Then
s ₂ . By the wafer primary test (PT), the primary test is performed on the entire wafer effective area to determine the quality of the product chip. At this time, a map (PTMAP) about the pass / fail result is created based on the reference chip (start chip) determined based on the rule. Then
s ₃ . Dicing is performed so that the entire effective chip area is cut by dicing. Then
s ₄ . Perform die bonding. At this time, the reference chip is identified visually and by a die bonder camera, collated with PTMAP, and only good chips are die-bonded.

JP-A-57-095644

  However, in the wafer process, a reference chip different from the product chip is arranged for alignment or the like, and the pattern of the product chip cannot be arranged in that portion, and the effective number of product chips is correspondingly increased. There exists a problem that it falls and manufacturing cost rises.

  Further, there is a problem in that the position of the wafer center and the position of the reference chip cannot be specified from any three points of the wafer when the wafer support sheet is extended only by arranging the reference chip. Note that even if the chip identification camera of the die bonder tries to identify the reference chip, the chip identification camera identifies the chip in units of chip outline, and cannot identify a reference chip having the same chip outline as the product chip.

  Accordingly, an object of the present invention is to make it unnecessary to use a reference chip different from a product chip and to easily identify a start chip that is a reference for verification in a process after dicing.

From one aspect disclosed, a confirmation pattern is formed on a scribe line adjacent to a corner of a specific chip in each block on a semiconductor wafer including a plurality of chips and a plurality of blocks serving as a unit to be burned by a reticle. A step of supporting the semiconductor wafer on a support, and a step of dicing the semiconductor wafer with a first dicing line protruding from the end of the semiconductor wafer to a first length on the support. the confirmation pattern is the risk Lai brine is detected, the second dicing line which projects into the second length said support on which is different from the semiconductor wafer edge and the first length, wherein the semiconductor wafer A step of dicing, and the second dicing line is in contact with the specific chip, and at least Has a pair, is provided a method of manufacturing a semiconductor device characterized by having an intersection mutually orthogonal.

According to the disclosed method for manufacturing a semiconductor device, a reference chip different from a product chip is not required, and a start chip that is a reference for verification in a process after dicing can be easily identified.

1 is a conceptual plan view of a wafer reticle according to an embodiment of the present invention. It is a notional top view of the semiconductor wafer of an embodiment of the invention. It is explanatory drawing of the dicing line in embodiment of this invention. It is a flowchart of the manufacturing process of the semiconductor device of embodiment of this invention. It is explanatory drawing of the wafer process in the manufacturing method of the semiconductor device of Example 1 of this invention. It is a top view which shows the chip | tip effective area | region in Example 1 of this invention. It is explanatory drawing of the determination method of the confirmation pattern and chip | tip effective area | region in the wafer primary test of Example 1 of this invention. It is explanatory drawing of the wafer primary test and PTMAP in Example 1 of this invention. It is explanatory drawing of the detection method of the confirmation pattern in the dicing process of Example 1 of this invention. It is explanatory drawing of (theta) correction | amendment of the semiconductor wafer in Example 1 of this invention. It is explanatory drawing of the dicing state in Example 1 of this invention. It is explanatory drawing of the collation process with PTMAP in the die-bonding process of Example 1 of this invention. It is a notional top view of the semiconductor wafer after the dicing process in Example 2 of the present invention. It is a notional top view of the semiconductor wafer after the dicing process in Example 3 of the present invention. It is a notional top view of the semiconductor wafer after the dicing process in Example 4 of the present invention. It is a notional top view of the semiconductor wafer after the dicing process in Example 5 of the present invention. It is explanatory drawing of the start chip | tip detection process in Example 5 of this invention. It is explanatory drawing of the wafer process in the manufacturing method of the conventional semiconductor device. It is a top view which shows the relationship between a wafer and a reference | standard chip. It is explanatory drawing of the determination method of the reference | standard chip | tip and chip | tip effective area | region in a wafer primary test. It is explanatory drawing of a wafer primary test and PTMAP. It is explanatory drawing of the state of the wafer in a dicing process. It is explanatory drawing of a specific dicing process. It is explanatory drawing of the collation process with PTMAP in a die-bonding process. It is explanatory drawing of a specific die bonding process. It is the flowchart which summarized the manufacturing process of the conventional semiconductor device.

  Here, a semiconductor wafer according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a conceptual plan view of a wafer reticle. All chip patterns provided on the wafer reticle 1 are product chip patterns 2, and a confirmation pattern 4 is formed on a scribe line 3 adjacent to a corner of any product chip pattern 2. In addition, in the figure, the example provided in the upper left corner is shown as a typical position.

  FIG. 2 is a conceptual plan view of a semiconductor wafer. A confirmation pattern 7 is printed at the corner of each transfer unit together with the semiconductor chip 6. In the figure, a stepped thick line frame is a chip effective area for the confirmation pattern 7 in the semiconductor wafer 5.

FIG. 3 is an explanatory diagram of a dicing line. The semiconductor wafer 5 is fixed on a wafer support sheet 9 fixed to a wafer ring 8 and is diced with a dicing blade or the like. At this time, the protrusion length from the wafer end of at least one pair of dicing lines 11 and 12 orthogonal to each other that cut the confirmation pattern 7 in contact with the reference start chip 10 is the protrusion length from the wafer end of the other dicing lines 13 and 14. Set to be different from the length.

  In this case, the different length may be set to the protruding length at one wafer end or the protruding length of both wafer ends. Further, the protruding lengths of the two pairs of dicing lines sandwiching the start chip 10 from the wafer end may be set to be different from the protruding lengths of the other dicing lines 13 and 14 from the wafer end.

FIG. 4 is a flowchart of the manufacturing process of the semiconductor device according to the embodiment of the present invention.
S ₁ . In the wafer process, the reticle pattern is printed on the entire surface of the wafer by step and repeat. At this time, a confirmation pattern is given to the scribe line in the effective chip area in the reticle.

Then
S ₂ . By the wafer primary test (PT), the primary test is performed on the entire wafer effective area to determine the quality of the product chip. At this time, first, the wafer center is obtained from arbitrary three points on the outer periphery of the semiconductor wafer, moved to the designated coordinates, and the confirmation pattern of the corner of the reticle pattern determined based on the rule is detected. Next, a primary test is performed, and a map (PTMAP) of the pass / fail result is created based on the confirmation pattern of the corner of the reticle pattern determined based on the rule.

Then
S ₃ . Dicing is performed so that the entire effective chip area is cut by dicing. At this time, after correcting the inclination θ from two points of the product chip, the wafer center is obtained from any three points on the outer periphery of the semiconductor wafer, moved to the designated coordinates, and the reticle pattern determined based on the rule is obtained. Detect corner confirmation patterns. Next, dicing is performed so that the protruding length from the wafer end of at least one pair of dicing lines orthogonal to each other that cuts the confirmation pattern in contact with the reference start chip is different from the protruding length from the wafer end of the other dicing lines.

Then
S ₄ . Perform die bonding. At this time, a reference start chip arranged at a ruled position from the intersection of other dicing lines with different lengths is detected visually or by a camera of a die bonder, and the start chip and PTMAP are collated. As a result of collating with PTMAP, only non-defective chips are die bonded.

  Thus, in the embodiment of the present invention, the product chip adjacent to the confirmation pattern provided on the scribe line is used as the start chip without using a reference chip having a circuit pattern different from that of the product chip. The effective number of chips does not decrease.

  In addition, since the start chip in the die bonding process is confirmed by the difference in protrusion length from the wafer edge of the dicing line, it is easy to confirm the position of the start chip even when the wafer support sheet is extended. Can do.

  Based on the above, next, the manufacturing process of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 5 is an explanatory diagram of a wafer process in the method for manufacturing a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 5A, a wafer reticle 21 in which semiconductor chip patterns 22 are arranged in a matrix is illustrated. A confirmation pattern 23 is set at a predetermined position on the scribe line. The setting position of the confirmation pattern 23 is arbitrary, but is usually arranged at the corner of the reticle pattern. The semiconductor chip pattern 22 has a circuit pattern for manufacturing a product chip.

  Next, as shown in FIG. 5B, the pattern of the wafer reticle 21 is printed on the entire surface of the wafer 30 by step-and-repeat. FIG. 5C is a conceptual plan view of the semiconductor wafer 30 on which the pattern of the wafer reticle 21 is baked. For each transfer unit corresponding to the wafer reticle 21, a scribe adjacent to the semiconductor chip 31 that is the upper left product chip. A confirmation pattern 32 is printed on the line.

  FIG. 6 is a plan view showing a chip effective area, in which a confirmation pattern 32 is burned on a scribe line adjacent to the upper left semiconductor chip 31 for each transfer unit, as shown by a stepped thick line frame in the drawing. Then, the chip effective area for the confirmation pattern 32 at the position determined based on the rule in the semiconductor wafer 30 is determined.

FIG. 7 is an explanatory diagram of a method for determining a confirmation pattern and a chip effective area in the wafer primary test. First,
a ₁ . Alignment is performed so that a notch 33 formed in advance in the semiconductor wafer 30 for alignment is positioned in front of the semiconductor wafer 30 (just below in the drawing) in the primary test apparatus. Then
b ₁ . The wafer center is obtained from arbitrary three points A, B, and C around the semiconductor wafer 30. Then
c ₁ . The confirmation pattern 32 of the upper left block is obtained by moving from the wafer center to a preset coordinate. Then
d ₁ . The effective area for performing the primary test is identified by the effective area information with respect to the confirmation pattern 32 set in the wafer process.

  FIG. 8 is an explanatory diagram of the wafer primary test and PTMAP. As shown in FIG. 8A, the primary test is performed on all the semiconductor chips in the effective area of the semiconductor wafer 30. In the figure, a state is shown in which three semiconductor chips arranged vertically are tested using one probe card 34 at the same time.

  FIG. 8B is a conceptual explanatory diagram of PTMAP. As a result of the primary test, a non-defective chip 35 determined as a non-defective product and a defective chip 36 determined as a non-defective product are mapped to create a PTMAP. At this time, a map is created using the semiconductor chip 31 adjacent to the confirmation pattern 32 as a reference start chip.

FIG. 9 is an explanatory diagram of a method for detecting a confirmation pattern in the dicing process, and shows a state in which the semiconductor wafer 30 is supported on a wafer support sheet 41 fixed to the wafer ring 40. First,
a ₂ . In the dicing apparatus, alignment is performed so that the notch 33 of the semiconductor wafer 30 comes to the front. Then
b ₂ . The wafer center is obtained from arbitrary three points A, B, and C around the semiconductor wafer 30. Then
c ₂ . The confirmation pattern 32 of the corner of the upper left transfer unit is detected by moving from the wafer center to preset coordinates.

FIG. 10 is an explanatory diagram of θ correction of a semiconductor wafer.
a ₃ . In the dicing apparatus, alignment is performed so that the notch 33 of the semiconductor wafer 30 comes to the front. Then
b ₃ . Horizontal indexing is performed from any two semiconductor chips A and B arranged in the same row, and the angle shift θ of the semiconductor wafer 30 is corrected by the alignment device. Then
c ₃ . Dicing is performed in order from the end of the semiconductor wafer 30.

  FIG. 11 is an explanatory diagram of the dicing state. In the normal round cut, dicing is performed so that the wafer size + about 3 mm on one side is exceeded, but the dicing lines 42 and 43 of the scribe line where the confirmation pattern is detected are only on one side. Dicing is performed longer than the other dicing lines 44 and 45. For example, if the diameter of the semiconductor wafer 30 is 300 mm, the inner diameter of the wafer ring 40 is 400 mm, and the normal round cut is diced so as to exceed the wafer size + 3 mm on one side. However, the dicing lines 42 and 43 of the scribe line where the confirmation pattern is detected are diced so that the upper side and the left side are about 30 mm longer than the wafer size. At this stage, the confirmation pattern 32 disappears.

  FIG. 12 is an explanatory diagram of the collating process with PTMAP in the die bonding process. The start chip 37 in which the confirmation pattern 32 is formed on the adjacent scribe line on the wafer 30 is changed depending on the length of the dicing lines 42 and 43. Discriminate visually.

  Thereafter, although not shown in the drawings, the wafer support sheet 41 is extended by raising the expanding jig with respect to the wafer ring 40 that supports the wafer 30 that has been diced. Alternatively, the wafer ring 40 may be lowered with respect to the expanding jig.

  Next, only the product chip corresponding to the non-defective chip 35 is pushed up by the push-up needle, the suction collet is lowered, and the non-defective chip 35 is sucked by vacuum suction, and then the suction collet is raised and die-bonded.

  As described above, in the first embodiment of the present invention, in order to determine the start chip, not only the reference chip different from the product chip but the confirmation pattern is provided in the adjacent scribe line. Will not decrease.

  In addition, since the start chip in the die bonding process is identified by the difference in the length of the dicing line, it is easy to identify the dicing line, and the position of the start chip can be easily visually confirmed even when the wafer support sheet is extended. Can be determined.

  Next, with reference to FIG. 13, the manufacturing process of the semiconductor device according to the second embodiment of the present invention will be described. However, the configuration is the same as that of the first embodiment except that the dicing line is different. Only the top view of the semiconductor wafer after a dicing process is shown.

  FIG. 13 is a conceptual plan view of the semiconductor wafer after the dicing process in the second embodiment of the present invention. The dicing lines 42 and 43 adjacent to the start chip 37 are 30 mm on both sides of the semiconductor wafer 30 and the other dicing lines 44 are arranged. , 45 longer.

  Also in the second embodiment of the present invention, since the dicing lines 42 and 43 adjacent to the start chip 37 are different in length from the other dicing lines 44 and 45, it is easier to specify the dicing lines. As a result, even when the wafer support sheet is extended, the position of the start chip 37 can be easily determined visually.

  Next, the manufacturing process of the semiconductor device according to the third embodiment of the present invention will be described with reference to FIG. 14. However, the configuration is the same as that of the first embodiment except that the dicing line is different. Only the top view of the semiconductor wafer after a dicing process is shown.

FIG. 14 is a conceptual plan view of the semiconductor wafer after the dicing process according to the third embodiment of the present invention. Two pairs of dicing lines 42 ₁ , 42 ₂ , 43 ₁ , and 43 ₂ sandwiching the start chip 37 are shown. 30 mm on one side of the semiconductor wafer 30 and longer than the other dicing lines 44 and 45.

Also in the third embodiment of the present invention, the dicing lines 42 ₁ , 42 ₂ , 43 ₁ , and 43 ₂ adjacent to the start chip 37 are different in length from the other dicing lines 44 and 45. Accordingly, the position of the start chip 37 can be more easily visually determined even when the wafer support sheet is extended.

  Next, the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIG. 15. However, the configuration is the same as that of the first embodiment except that the dicing line is different. Only the top view of the semiconductor wafer after a dicing process is shown.

FIG. 15 is a conceptual plan view of the semiconductor wafer after the dicing process in the fourth embodiment of the present invention. The pair of dicing lines 42 ₁ , 42 ₂ , 43 ₁ , and 43 ₂ sandwiched by the start chip 37 are shown in FIG. 30 mm on both sides of the semiconductor wafer 30 and longer than the other dicing lines 44 and 45.

Also in the fourth embodiment of the present invention, since the dicing lines 42 ₁ , 42 ₂ , 43 ₁ , and 43 ₂ adjacent to the start chip 37 are different in length from the other dicing lines 44 and 45, the dicing line is specified. In addition, even when the wafer support sheet is extended, the position of the start chip 37 can be more easily determined visually.

  Next, the manufacturing process of the semiconductor device according to the fifth embodiment of the present invention will be described with reference to FIGS. 16 and 17. However, the other configuration is the same as that of the first embodiment except that the state of the dicing line is different. It is. FIG. 16 is a conceptual plan view of the semiconductor wafer after the dicing process in the fifth embodiment of the present invention. The dicing lines 42 and 43 adjacent to the start chip 37 are connected to the other dicing lines 44 and 45 on one side of the semiconductor wafer 30. Make it shorter. That is, the dicing lines 42 and 43 are diced so that the normal side is over 3 mm on one side and the other side is over 30 mm, and the other dicing lines 44 and 45 are diced so as to be over 30 mm on both sides of the wafer.

  FIG. 17 is an explanatory diagram of the detection process for the start chip according to the fifth embodiment of the present invention. By scanning the notch of the wafer support sheet 41 on the outer periphery of the semiconductor wafer 30 with the camera 46 installed in the die bonder, the short dicing lines 42 and 43 can be specified. Thereby, the semiconductor chip adjacent to the intersection of the short dicing lines 42 and 43 can be specified as the start chip 37.

  In the fifth embodiment of the present invention, since the dicing line is specified using the camera 46 instead of visual observation, the position of the start chip 37 can be automatically specified.

1, 21 Wafer reticle 2 Product chip pattern 3 Scribe line 4, 23 Confirmation pattern 5, 30 Semiconductor wafer 6 Semiconductor chip 7, 32 Confirmation pattern 8, 40 Wafer ring 9, 41 Wafer support sheet 10, 37 Start chip 11, 12, 42 _{1, 42} 2, 43 _1, 43 ₂ dicing lines 13,14,44,45 dicing line 22 semiconductor chip patterns 31 semiconductor chip 33 notch 34 probe card 35 good chips 36 defective chips 46 camera 51 wafer reticle 52 Semiconductor chip pattern 53 Reference chip pattern 60 Semiconductor wafer 61 Reference chip 62 Semiconductor chip 63 Notch 64 Probe card 65 Non-defective chip 66 Defective chip 70 Wafer ring 71 Wafer support sheet 72 Rotary dicing blade 81 Expanding jig 82 Push-up needle 83 Adsorption collet

Claims (4)

Forming a confirmation pattern on a scribe line adjacent to a corner of a specific chip in each block on a semiconductor wafer including a plurality of chips and arranging a plurality of blocks serving as a unit to be baked by a reticle;
Supporting the semiconductor wafer on a support;
A step of dicing the semiconductor wafer with a first dicing line projecting from the edge of the semiconductor wafer to a first length on the support;
The confirmation pattern is the risk Lai brine is detected, the second dicing lines said semiconductor wafer edge protrudes into the first second length said support on which is different from the length, the semiconductor wafer And a step of dicing,
The method of manufacturing a semiconductor device, wherein the second dicing line is in contact with the specific chip, is at least a pair, and has intersecting points perpendicular to each other. 2. The method of manufacturing a semiconductor device according to claim 1, wherein dicing is performed so that two sets of the second dicing lines perpendicular to each other sandwiching the specific chip are formed. In the step of dicing the semiconductor wafer at the second dicing line, the step of dicing the second length to be shorter than the first length ;
The method of manufacturing a semiconductor device according to claim 1, further comprising a step of scanning the first length and the second length with a camera provided in a die bonder. Identifying the position of the intersection of the second dicing lines from the difference between the first length and the second length;
Determining a position of the specific chip as a reference from the detected intersection point ;
A step of checking the position of a chip determined to be a non-defective product or a defective product in the wafer test with reference to the specific chip ;
4. The method of manufacturing a semiconductor device according to claim 1, further comprising: taking out only a chip determined to be a non- defective product and performing die bonding. 5.

Images