TW200822376A - Bump electrode including plating layers and method of fabricating the same - Google Patents

Bump electrode including plating layers and method of fabricating the same Download PDF

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Publication number
TW200822376A
TW200822376A TW096133202A TW96133202A TW200822376A TW 200822376 A TW200822376 A TW 200822376A TW 096133202 A TW096133202 A TW 096133202A TW 96133202 A TW96133202 A TW 96133202A TW 200822376 A TW200822376 A TW 200822376A
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Taiwan
Prior art keywords
layer
bump
electrode
semiconductor device
forming
Prior art date
Application number
TW096133202A
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English (en)
Inventor
Hyung-Sun Jang
Yong-Hwan Kwon
Un-Byoung Kang
Chung-Sun Lee
Woon-Seong Kwon
Original Assignee
Samsung Electronics Co Ltd
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Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200822376A publication Critical patent/TW200822376A/zh

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200822376 25593pif.doc 九、發明說明： 韓國智慧財產局的韓國專利申請 10-2006-0098646，申請日2〇〇6年1〇月1〇日，以與本^ 不相抵觸的引用方式併入本文中。 /'又 .【發明所屬之技術領域】 本發明大體而言是有關於一種半導體裝置，且更特^
而言’本發明於_種突塊及突塊電 ^^ 【先前技術】 去。 通常，半導體裝置是藉由突塊電極而連接至外部 路。特Μ言，當以突塊電極與接合線做時時，具 塊電，之半導體裝置會展現減少的錢雜訊、增加的概= 電極密度以及㈣的封裝外形。使用突塊雜之_造给 例包含捲帶式封裝⑽)方法、_覆晶封裝(cot)方^ 以及玻璃覆㈣裝(COG)方法，其通f用於安裝 」 =如’液晶顯示器_)、電裝顯示 機= 光裝置(OLED))之驅動單元。 」汉頁钱發 目前’突塊電極是由料(SGlder)或金製造，1每 =現局電導性以及良好的延展性。然而，使錫^ =包含錯)會遭遇與環境相關的缺陷。另外 （二通 較多。 在使祕田^塊電極技術時則通常花費 【發明内容】 根據本發明之態樣，提供一種 200822376 25593pif.doc 在襯墊電極上方形成晶種層；在 罩幕層具有對準襯墊電極上方“^曰^形成罩幕層， 口内電鍍障壁電鑛層；在障壁電靜上層土方之開 Η 塊1鍍層為罩幕來勤i晶種^ 根據本發明之另一態樣，提供 曰曰種層 突塊電極的方法。形成方法包含 且^體裝置之 板；在襯墊電極上方形成晶種曰、種I電極的基 障壁_;在4=上== :層在撕層上方形成突軸層“X二ΐ; 根據本發明之又一態樣，提供 突塊電極的方法。形成方法包裝置之 板;在襯墊電極上方形成晶種層;在晶種声：方 =層襯墊電極上方的開口;在開:内· 底声麟上方打底麵—金打底層；在金打 底層上方讀金電鏡層；移除光阻層；以及 爲^ 罩幕來数刻晶種層。 、’包鏡層為 根之另-態樣，提供—種半導 -極。突塊電極包含:形成於基 ’ 襯，方的晶種層;位於晶種層上方的二 於 以及位於障壁麵層上方的突塊電紗。Μ鑛層， 【實施方式】 9 現將麥有隨附圖式更全面地描述本發明，在隨附圖式 200822376 25593pif.doc 中展示本發明之例示性具體例。鈇 為清晰起見，誇示;;i=;，。在圖式中， 同的參考數字指示==厂予度。此外’在圖式中相 例之用於描触縣㈣之—❹個實施 〇之$脰衣置的犬塊電極的形成方法的剖面示意圖。 泰圖1Α於半導體基板10〇上形成襯墊電極no， ji t錢形成於基板1〇0上及/或形成於基板100中 層（未函不）。襯墊電極110可例如為銘(A1)層或銅(Cu) 〜於基板1〇〇上方形成保護層115，且保護層ιΐ5具有 t减塾電極11Q _口。保護層115可例如為氮化石夕薄 膜二氧化石夕薄膜、氮氧化石夕薄膜或由兩種或兩種以上此等 材料製成之多層薄膜。此外，於保護層⑴上可形成聚人 物層（未圖示）。 口 接著’於半導體基板1⑽、襯墊電極11Θ以及保護層 的上方形成晶種層120。在此實施例中，晶種層12() 包含晶種接合層12ι以及潤濕層122,此等層順序地堆疊， 且幸父f地展現相對於稍後形成之突塊電鍍層之高蝕刻選擇 症°晶種接合層121可提昇襯墊電極110與潤濕層122之 間的附著力，且可例如由鈦(Ti)、鈦化鎢(TiW)、氮化鈦 (丁iN)、絡(Cr)、鋁(A1)或兩種或兩種以上此等材料之合金 200822376 25593pif.doc 構成。潤濕層122充當在隨後過程中形成之障壁電鍍層之 晶種’且可例如由Cu、鎳(Ni)、飢化鎳(Niv)或兩種或 以上此等材料之合金構成。在展魏好雜之低成本實施 例中’晶種接合層121為Ti帛膜，且潤濕層122為cu。 ^種接合層121以及潤濕層122可例如藉錢鍍順序地形 參看圖1B，於晶種層12〇上形成罩幕層19〇。
190具有對準襯墊電極11〇上方的開口隱，而開口^ 暴露出部分的晶種層120。罩幕層刚可例如為光阻芦。a 芩看圖ic，利用電鍍方式，於暴露在開口 19〇&曰 晶種層120上形成障壁電鍍層13〇。亦即，例如 气板⑽可浸在含有具有障齡相電鍍紐的電錢= (未圖不）中。具有晶種層m的半導體基板⑽界定: 處理的陰極，且陽極(未_)獨立料定於雜盆内。= 流流，陽極以及陰極以將障壁金屬電附著在晶種層电 上，糟此形成障壁電鍍層130。 κ "的電财法使得在各種_襯墊雷接 上的層厚度可m在非麵的纽中，最初執 表面活化處理，例如鋅酸鹽(zineate)處理，藉此將_: =吸附在襯墊電極的表面上。此時，在接地襯墊電極電性 、接至半導體基板的情況巾，與襯㈣極材料的電 聯地產生的電子不能麟吸附鋅離子群，相反地會茂出 至半導體基板。如圖2A及圖2B的攝影影像所示，由於錄 離子群不能充分地錢在接地襯—極上，故電鍍層的妒 200822376 25593pif.doc 成在通用襯墊電極(general pad electr〇de)(圖2A)與接地襯 墊電極(groundpad electrode)(圖2B)之間極不相同'。因此'， 難以在不同類型襯墊電極上將電鍍層形成為均—厚度。 在本實施例中，障壁電鍍層130是利用不需要=曰 層！20或襯墊電㈣〇進行表面活化處理，例如辞酸=處 理’的電鑛所形成。因此，形成在半導體基板刚上
種類型襯墊電極11G上，可形成具有均—厚度的障壁 層 130 。 X 如將難結合圖3A至圖4解釋，障壁電鐘層13〇較 Ί 叫2更細厚度，且技岐，障壁電鍍層 ▲30具旁5 μπ1或更大的厚度。此外，考虔到盥突 度相關的較倾計約束，障㈣顯13 '較佳^有冋 =或更小的厚度。障壁麵層⑽可為Μ薄，ϋ 广或兩種或兩種以上此等薄膜製成的合) ^較佳的是’障壁電鍍層13G為Μ 鋅 其可降低處喊本域做好_著力及抗侵H 突餘：ί圖1D,在此貫施例中’於障壁電鍍層130上形成 方式所形成的打底電鐘層.，其可改電=電鍍 週期來執二。 式的電流密度高，且歷時較短時間 塊接15G_電鍍方式形成於突 於iiir 類似於障壁電鑛層⑽，於位 、版基板100上的各種類型襯墊電極11〇上，可形成 10 200822376 25593pif.doc =厚度的突塊電麟15G。突塊.麵層i5Q (Au)薄膜。 大 =電縣150能可靠地接合在障壁電鍍層i3〇上。 ^辟^奸14G能防止或最小化由於突塊電鍍層⑼
削之_應力差所可能產生之在其分界表 面處告生的缝。突塊接合層14G 的材料相同的㈣構成。 ”大見电锻居150 ^佳地’障壁電鑛層13〇具有足夠的厚度(例如，4帅 白:下ί Γ防止突塊電鑛層150的溶液滲入罩幕圖案190 觸晶種層12G。因此，至少—部分是因為晶種 岸150 於犬塊電鍍溶液巾，且此又可阻礙突塊電鍍 腔日^成長及形成。在晶種層㈣的潤濕層122為 別有問題^塊電鐘層15G為金薄膜的情況中，此可能為特 鏡層3 Γ二突τ=鍍層150的厚度T-15。大於障壁電 遠技/帝予又丁-130。因此，可使最終形成的突塊電極 毛路板上時，能充分地按壓突塊電鍍層150且使苴 接可靠地連接半導體裝置與電路板。此外，突塊 ^ s 40可防止或最小化突塊電鍍層15〇自障壁電
Ui)起皺。 m ^看圖1F，移除罩幕圖案190，以暴露晶種層120。 層=圖將突塊電鍍層15〇用作餘刻經暴露的晶種 产辟帝6、罩幕。因此，獲得包含順序地堆疊的晶種層120、 “鍍層130、大塊接合層“ο以及突塊電鍍層15〇的 11 200822376 25593pif.doc 犬塊電極。 晶種層120較佳展現相對突塊電鍍層15〇以辟命 鍍層130的高姓刻選擇性，以藉此避免在韻刻晶種層^ 期間，敍刻到突塊電鑛層150以及障壁電鍍I 130。此可 使犬塊電鐘層Γ5Θ以及障壁雷梦；no的p 4 ώ 士 度的變化能夠最小化。鐘層的尺寸及表面粗趟 铁而在ii中’為更好地理解本發明，將呈現較佳實施例。 ;、、、、而，本發明並不限於以下實施例。 <實施例1> 在基板上形成鋁襯墊電極，且 襯墊電極的粗雄层。拉基,.m ^ 电位上开乂成恭路 &^層接者，使用濺鍍，在襯墊電極及仵驾 :上’順序地堆疊Ti薄膜及Cu薄膜。 襯塾電極的對(―幻 使_，在暴露於 使錘雷雜β 士 、、 t成錄琶鐘層， 域電鍍層具有約丨μιη的厚度 鍍，本锂+力念昆L W ι X 使用电解打底電 _讀層上喊金打底電鍍層。接著，使 在孟打底電鍍層上形成金電鍍層 包、，又 的厚度。 便至私鍍層具有17 μιη <實施例2> 藉由與實施例丨相同的方 在於：形忐1古·， « 〜攻大塊电極’不同之處 办成具有2μπι厚度的鎳電鍍層。 <實施例3> θ 藉由與實施例1相同的方法形成突塊電極，不同之處 12 200822376 25593pif.doc 在於：形成具有3 μιη厚度的鎳電鍍層。 <實施例4> 藉由與實施例1相同的方法形成突塊電極，不同之處 在於：形成具有4 μπι厚度的鎳電鍍層。 <實施例5> 藉由與實施例1相同的方法形成突塊電極，不同之處 在於：形成具有5 μιη厚度的鎳電鍍層。 <實施例6> 藉由與實施例1相同的方法形成突塊電極，不同之處 在於：形成具有6 μιη厚度的錄電鍍層。 根據實施例1、3、4及5形成的突塊電極之上表面的 影像分別說明於圖3Α至圖3D中。在此等影像(詳言之， 圖3Α及圖3Β)中，由參考字元“F”指示缺陷。 實施例1至6的突塊電極的缺陷形成率展示於以下表 1中及圖4的曲線圖中。藉由檢查多個晶片中突塊電極的 組態，且計算相對於晶片的總數目含有異常突塊電極(缺陷) 的晶片的數目，而獲得缺陷形成率。 表1 條件 缺陷形成率 實施例1 Νι Ιμπι 52.8% 實施例2 Ni 2μπι 21.2% 實施例3 Ni 3μπι 2.5% 實施例4 Ni 4μιη 0.2% 實施例5 Ni 5 μιη 0.0% 實施例6 Ni 6 μπι 0.0% 13 200822376 25593pif.doc 茶看表1及圖4’當錄電鍛層的厚度為小於4 μπϊ時， 在金電鍍層150的邊緣部分處形成缺陷F(亦可參見圖3Α 及圖3Β)的發生率增加。如先前所述，若鎳電鍍層過薄， 則金笔鍛洛液可能滲入而接觸且溶解下面的銅薄膜，而阻 礙金電鍍層的正常成長。 相反地，若鎳電鍍層的厚度為4 μιη或更大，則在金 電鍍層的邊緣部分展現最小缺陷。此外，若鎳電鍍層的厚 度為5 μπι或更大，則在金電鍍層的邊緣部分展現無缺陷 形成。 根據上文所述之一或多個實施例，突塊電極可僅部分 也…I··冓成如此可降低成本。此外，可藉由電鍍形成障 壁電，層以及突塊電鍍層，以使得在各種類型概塾電極上 之此等層的厚度可均一。此外， 有足夠厚度(例如，4 μπι或更大），以防二ft而具 声的缺ma、- / ) 止或減少突塊電鍍 二币、㈢7成’祕改良突塊電鍍層的電斜形。又，突 塊电鍍層的厚度可大於障壁雷 大 導I*壯W早土电鍍層的厚度，藉此改良在半 t衣置與電路板之間的連接的可靠性。
層可形成於障壁電鍍層與突 、大鬼接S 鍍層與障壁電鍍層之間的接合可C工：：良突塊電 比障壁電鍍層厚之情況中更亦如=尤/、在大塊電鍍層 雖然已參考本發明之例雜具 本發明’但應理解熟習此技蓺 :、不及描述 利範圍界定之本發明之精神;後附之申請專 細節上進彳亍各觀變。 _邮況下，可在形式及 14 200822376 25593pif.doc :【圖式簡單說明】 圖1A至圖1G為用於描述根據本發明之— 例之半導财置喊塊電_形成方法的個實施 、圖2A及圖2B為說明使用非電鍍技術分別形成= 襯墊電極以及接地襯墊電極上之電鍍層的攝影影像。、 圖3 A至圖3 D為根據本發明之具體例具有不同 厚度之突塊電極之上表面的攝影影像。 i、又層
圖4為展示劣等突塊電極缺陷形成率相 厚度的關係的曲線圖。 i錢層之 :【主要元件符號說明】 100 :半導體基板 110 :襯墊電極 115 :保護層 120 ·晶種層 121 ·晶種接合層 122 :潤濕層 130 :障壁電鍍層 140 :突塊接合層 150 :突塊電鍍層 190 :罩幕圖案 190a :開口 T__130 :厚度 Τ_150 ·厚度 15

Claims (1)

  1. 200822376 25593pif.doc 十、申請專利範圍： 1·-種半導魏置的突塊電_形成方法，包括·· 促供一基板，該基板具有~概塾電極； 在該襯墊電極上方形成一晶種層； 、在該晶種層上方形成-罩幕層，該罩幕層具有對準該 概塾電極上方的一開口； 在違aa種層上方的該開口内電鍍一障壁電鍍層； 在该障壁電鍍層上方電鍍一突塊電鍍層； 移除該罩幕層；以及 以該突塊電鍍層為罩幕來蝕刻該晶種層。 2. 如申請專利範圍第丨項所述之半導體|置的突塊電 極的形成方法’更包括在電鍍該突塊電鍍層之前，在該障 壁電鑛層上形成一突塊接合層。 3. 如申請專利範圍第2項所述之半導體裝置的突塊電 極的形成方法，其巾該突塊接合相及該突塊電鍍層是由 相同材料構成。 4:如中叫專利㈣第2項所述之半導體裝置的突境電 々t/成方法其中該突塊接合層藉由打底電鍍而形成。 5·如申明專利氣圍冑1項所述之半導體裝置的突塊電 的形成方法，其中該突塊電鍍層比該障壁電鍍層厚。 極的專T圍第5項所述之半導體裝置的突塊電 辟+/ ,，更包括在電鍍該突塊電鍍層之前，在該障 土电鍍層上形成一突塊接合層。 7·如申明專利範圍第1項所述之半導體裝置的突塊電 16 200822376 25593pif.doc 極的rfn’其-巾轉㈣鍍層的厚度為至少4_。 π專利範圍第7項所述之半導體裝置突 極的形成方法，苴由牙映辟不 卞彳版衣直的大塊電 /、中該卩早壁黾鍍層的厚度為至多 15 μπι 〇 極的开〜太\利範圍第1項所述之半導體裝置的突塊電 ΟΜ)鈀ΓΑ I ，其中該障壁電鍍層包括選自鎳(Ni)、鈀 之族群及兩種或兩種以上此等材料之合金所組成 翻第1項所叙半導《置的突塊 祕的形成f法，其中該突塊電鑛層包括金(Au)。 月專利範圍第1項所述之半導體裝置的突塊電 .卜=—一，，其中該晶種層包括依序地堆疊於該襯墊電 極上方的一晶種接合層以及一潤濕層。 專利範圍第11項所述之半導體裝置的突塊 二/方去’其中該晶種接合層包括選自鈦(Ti)、氮 化鶴陶、路⑼、_)以及兩種或兩種 此寻材之合金所組成之族群其中之一。 I3·如申％專利|巳圍帛u項所述之半導體裝置的突塊 屯亟的开y成方去，其中該潤濕層包括選自銅(Cu)、鎳(Ni)、 叙化鎳(NiV)以及兩種或兩種以上此等材料之合金所組 之族群其中之一。 1=·一種半導體裝置的突塊電極的形成方法，包括·· 提供一基板，該基板具有一襯墊電極； 在該襯墊電極上方形成一晶種層； 在該晶種層上方形成一罩幕層，該罩幕層具有對準該 17 200822376 25593pif.doc 襯塾電極上方的一開口； 在該晶種層上方的該開口内形成一障壁電錢與， 在5亥障壁電鍍層上方形成-突塊接合層；曰’ 在該突塊接合層上方形成一突塊電鑛 移除該罩幕層。 久 如申請專利範圍第14項所述之半導 電極的形射法，其t職塊接合 挽的突掩 相同材料構成。 ㈣大塊%、 16.如申請專利範圍第]4項所述之半 ^極的形成方法，其中該突塊接合層是藉由打底魂 17·如申請專利範圍第14項所述之 電極的形成方法，1中哕穸挣L V體衣薏的突魂 18.如申请專利範圍第14項所述之半導體 =。 電極的形成方法，盆中兮陸 、又勺突土急 ,^雜壁電鑛層的厚度為至少4 带極的μ專利簡第18項所述之半導體裝置的突块 n、>成方法，其中該障壁電鏡層的厚度為至多 ▲ 電極二申3利=7 塊電鍍層為罩幕，餘ί；該晶=除該罩幕層之後，以該突 雷搞」二:'專利乾圍第Μ 頁所述之半導體裝置的突塊 帝朽、方去，其中該晶種層包括依序地堆疊於該襯墊 Μ1上方的1種接合層以及_潤濕層。 1種半&體裝置的突塊電極的形成方法，包括： 18 200822376 25593pif.doc 杈，一基板，該基板具有-襯墊電極；. 在該襯墊電極上方形成一晶種層； 在该開口内電鍍一錄電鍍層； 在該鎳電鑛層上方打底電鑛一金打底層； _ 在該金打底層上方電鍍-金電鑛層； 移除該光阻層；以及 .以該金麵層為罩幕__晶種層。 22項所述之半導體裝置的突塊 ==其中該晶種層包括依序地堆疊於該襯墊 电極上方的一鈦(Ti)層以及一銅(Cu)層。 電極專，㈣22項所^之半導體裝置的突塊 ' ^ 一中該鎳電鍍層的厚度為至少4 μιη。 專利範圍第24項所述之半導體裝置的突塊 、》成方次，其中該鎳電鍍層的厚度為至多15 μπι。 26. —種半導體装置的突塊電極，包括： 一襯墊電極，形成於一基板上方； 一晶種層，位於該襯墊電極上方； —障壁紐層，位於該晶種層上方；以及 —突塊電鍍層’位於該障壁電鍍層上方。 27. 如申請專利範圍第26項 電極，其中該障壁電鑛層的厚度為至欠二衣-的錢 汉如申請專概圍第27_狀半導體裝置的突塊 19 200822376 25593pif.doc 電極，其中該障壁電鍍層的厚度為至多15 μπι。 29. 如申請專利範圍第26項所述之半導體裝置的突塊 電極，更包括一突塊接合層，其位於該突塊電鍍層與該障 壁電鍍層之間。 30. 如申請專利範圍第29項所述之半導體裝置的突塊 電極，其中該突塊接合層以及該突塊電鍍層是由相同材料 構成。 31. 如申請專利範圍第26項所述之半導體裝置的突塊 電極，其中該突塊電鍍層比該障壁電鍍層厚。 32. 如申請專利範圍第31項所述之半導體裝置的突塊 電極，更包括一突塊接合層，位於該突塊電鍍層與該障壁 電鍍層之間。 20
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