200820392 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板之結構及其製造方法，尤 指一種適用於細線化（Fine Pitch)封裝基板之結構及其製造 5 方法。 【先前技術】 iw著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、尚性能的研發方向。為滿足半導體封裝件高積集度 10 (^tegrati〇n)以及微型化（Miniaturization)的封裝要求，提供 多數主被動元件及線路連接之電路板，亦逐漸由單層板演 變成多層板，以使在有限的空間下，藉由層間連接技術 (Interlayer connecti〇n)擴大電路板上可利用的佈線面積而 配合高電子密度之積體電路（Integrated circuh)需求。 15 α增層⑺遍，)方式製作之多層封裝基板，是在基板 (例如電路板）的—面或雙面，使介電層與金屬層順序增層， 而構成高密度之金屬佈線圖形。常見之封裝基板增層結構 的製作方法如圖1A至1F所示。 請參閱圖1A，首先提供一封裝基板101，其至少一表 面具有複數個電性連接塾102、以及—介電層1〇3。該電性 連接塾102之材料-般為銅。該介電層1〇3係全面性的覆蓋 於該封裝基板1〇1上，其材料一般為ABF(Ajin〇m〇t〇 Build up Film )。本實施例之電性連接墊1〇2係選擇性的連 揍至導通孔109，並且被介電層1〇3所覆蓋。 200820392 由於電性連接墊102之結構大致相同，故後續僅顯示其 二 中一電性連接墊1〇2作為代表說明。接著，對該介電層103 進行表面粗化，也就是以蝕刻溶液（如過錳酸酸鉀溶液）蝕刻 粗化该介電層103表面，得到如圖1B所示之結構。 5 隨後，如圖1C所示，於該介電層103上形成複數個介電 層開口 104以暴露出被介電層103覆蓋之電性連接墊1〇2。接 著，再依序於封裝基板101上形成一晶種層1〇5、以及一阻 層106。該阻層106具有複數個阻層開口 1〇7,且此阻層開口 % ι〇7之位置對應於介電層開口 1〇4。然後，以電鍍方式於阻 10層開口 107内形成一金屬層108，其結構如圖1D所示。最後， 如圖1E所示，移除阻層1〇6、以及阻層1〇6覆蓋之晶種層 玉〇5，即完成一層增層線路層。重複上述步驟，依所需要之 層數層疊上去即可製作多層封装基板，例如圖巧所示之結 構。 15 在封裝基板的增層製程中，形成晶種層105之前的介電 層1〇3(如ABF)必須先行粗化處理，以增加咬合力。如此由 v 晶種層1〇5與金屬層1〇8所構成的線路（參閱圖1D)，方才具 有良好的附著力。 目别，介電層103之表面粗化方式，係利用等向性化學 如蝕刻自平坦表面向下挖深。也就是說，介電層1〇3表面的坑 洞（苓閱圖1B)是利用過錳酸鉀溶液咬蝕掉部分介電層所形 成，因此介電層103表面的起伏不明顯。然而，封裝基板的 線路愈細，線路和介電層之間的咬合面積就越小，容易造 成兩者間的咬合力不足，甚至導致線路剝落。此故，當封 6 200820392 裝基板之線路趨向細線化（Fine Pitch)時，以化學蝕刻方式 粗化之介電層表面已無法提供足夠的咬合力，來避免線路 剝離。 隨著構裝技術的發展，細線化（Fine Pitch)成為封裝基 5板產業積極開發之方向之一，以增加可利用的佈線面積。 因此，如何增加封裝基板增層結構中層與層間的附著力， 實為亟待解決之課題。 【發明内容】 10 有鑑於此，本發明提供一種封裝基板之製造方法，其 7私包括·（A)提供一模板以及一基板，其中該模板表面具 有複數個凸出部，該基板表面具有複數個電性連接塾、以 及一介電層，且該介電層覆蓋該等電性連接墊；將該模 板壓印於該介電層上，在該介電層表面形成複數個溝紋， 15且該溝紋不穿透該介電層；（c)將該模板自該介電層移開； ⑼餘刻该介電層具有該等溝紋之表面，使該介電層表面及 忒等溝紋之内表面粗化，並於該介電層形成複數個介電層 開口 ’以路出該等電性連接墊；以及⑻於該介電層與該介 電層開口上成一圖案化金屬層，其中該圖案化金屬層包括 有-線路層以及複數個導電結構，該線路層係疊置於該介 電層具有邊等溝紋之表面，該導電結構係穿過該介電層開 以H線路層電性連接至該介電層下方之該等電性連接 200820392 換句活。兄’本發明之製造方法係先以機械方 電層進行預粗化，也就是以模板壓印於介電層上，使;;i 2表面產生垂直方向之凹陷。再以化學蝕刻方式對該介電 5 10 15 =仃表面粗化’使介電層表面以及溝紋的内表面被蝕刻 形成粗糙面。藉此方法，可增加介電層與線路層之間咬人 面積、’，而且溝紋的内表面會形成側向敍刻的粗链面，因： 大中田增加了介電層與線路層之間的附著力。此故，藉由 ==二=採用細線距⑻狀之封裝基^，其 綠路依然具有良好之附著力。 而且，藉由本發明之方法，後續形成於介電層上之 ^層^防焊層，其與介電層之間的咬合面積也會增加。因 此，提高封裝基板之增層結構中層與層之間的附著力。 此封裝基板之製造方法之步驟⑼中，㈣該介電層、 以及形成複數個介電層開口之先後次序不限定。較佳，係 依序先於該介電層具有該等溝紋之表面形成該介電層開 露出該等電性連接塾；再_該介電層具有 及該開口之内表面粗化：::層=等溝紋之内表面 使該介電層表面及該等溝紋之内表面粗 ，再於f介電層具有該等溝紋之表面形成複數個介電層 開口，以露出該等電性連接墊。 =本毛明之方法中’該介電層表面以模板壓印進行預 粗化％ ’該模板表面上凸出部的數量、位置配置、形狀、、 深度、及直徑不限定’可視製程需要或介電層之材料特性 20BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a package substrate and a method of fabricating the same, and more particularly to a structure suitable for a fine line (Fine Pitch) package substrate and a method of manufacturing the same. [Prior Art] Iw is booming in the electronics industry, and electronic products are gradually entering the development direction of multi-function and performance. In order to meet the high-integration degree of semiconductor package 10 and the miniaturization package requirements, most of the active and passive components and circuit-connected circuit boards are gradually evolved from single-layer boards to multi-layer boards. In a limited space, the interlayer wiring technology (Interlayer connection) is used to expand the wiring area available on the board to meet the demand for integrated circuits with high electron density. 15 α-layered (7) times, the multilayer package substrate produced by the method is formed on the surface or both sides of a substrate (for example, a circuit board), and the dielectric layer and the metal layer are sequentially layered to form a high-density metal wiring pattern. A common method of fabricating a package substrate buildup structure is shown in Figs. 1A to 1F. Referring to FIG. 1A, a package substrate 101 is provided, at least one of which has a plurality of electrical connections 102, and a dielectric layer 1-3. The material of the electrical connection port 102 is generally copper. The dielectric layer 1〇3 is entirely covered on the package substrate 1〇1, and the material thereof is generally ABF (Ajin〇m〇t〇 Build up Film). The electrical connection pads 1〇2 of the present embodiment are selectively connected to the via holes 109 and covered by the dielectric layer 1〇3. 200820392 Since the structure of the electrical connection pads 102 is substantially the same, only one of the two electrical connection pads 1〇2 is shown as a representative. Next, the dielectric layer 103 is roughened by surface etching, that is, the surface of the dielectric layer 103 is etched by an etching solution (e.g., potassium permanganate solution) to obtain a structure as shown in Fig. 1B. 5 Subsequently, as shown in FIG. 1C, a plurality of dielectric layer openings 104 are formed on the dielectric layer 103 to expose the electrical connection pads 1〇2 covered by the dielectric layer 103. Then, a seed layer 1〇5 and a resist layer 106 are formed on the package substrate 101 in sequence. The resist layer 106 has a plurality of resist layer openings 1〇7, and the position of the resist layer opening % 〇7 corresponds to the dielectric layer opening 1〇4. Then, a metal layer 108 is formed in the via 10 opening 107 by electroplating, and its structure is as shown in Fig. 1D. Finally, as shown in FIG. 1E, the resist layer 1〇6 and the seed layer layer 5 covered by the resist layer 1〇6 are removed, that is, a layer of the build-up layer is completed. By repeating the above steps, a multi-layer package substrate, such as the structure shown in the figure, can be fabricated by laminating the number of layers required. 15 In the build-up process of the package substrate, the dielectric layer 1〇3 (such as ABF) before the seed layer 105 is formed must be roughened first to increase the bite force. Thus, the line composed of the v seed layer 1〇5 and the metal layer 1〇8 (see Fig. 1D) has good adhesion. For the purpose of surface layering, the surface of the dielectric layer 103 is roughened by an isotropic chemistry such as etching from a flat surface. That is, the pits on the surface of the dielectric layer 1〇3 (see Fig. 1B) are formed by biting off a portion of the dielectric layer using a potassium permanganate solution, so that the surface of the dielectric layer 103 is not noticeably undulating. However, the finer the wiring of the package substrate, the smaller the nip area between the wiring and the dielectric layer, which tends to cause insufficient bite force between the two and even cause the line to peel off. Therefore, when the circuit of the packaged substrate 200820392 tends to be Fine Pitch, the surface of the dielectric layer roughened by chemical etching cannot provide sufficient biting force to avoid line peeling. With the development of the packaging technology, Fine Pitch has become one of the active development directions of the packaging base 5 industry to increase the available wiring area. Therefore, how to increase the adhesion between layers and layers in the build-up structure of the package substrate is an urgent problem to be solved. SUMMARY OF THE INVENTION In view of the above, the present invention provides a method for manufacturing a package substrate, which comprises: (A) providing a template and a substrate, wherein the template surface has a plurality of protrusions, the substrate surface having a plurality of An electrical connection layer and a dielectric layer, and the dielectric layer covers the electrical connection pads; the template is imprinted on the dielectric layer to form a plurality of grooves on the surface of the dielectric layer, 15 And the groove does not penetrate the dielectric layer; (c) the template is removed from the dielectric layer; (9) the dielectric layer has a surface of the groove, such that the surface of the dielectric layer and the like The inner surface of the groove is roughened, and a plurality of dielectric layer openings are formed in the dielectric layer to route the electrical connection pads; and (8) a patterned metal is formed on the dielectric layer and the dielectric layer opening a layer, wherein the patterned metal layer comprises a line layer and a plurality of conductive structures, the circuit layer being stacked on a surface of the dielectric layer having edges and the like, the conductive structure being opened through the dielectric layer The H circuit layer is electrically connected to the electrical connection below the dielectric layer 20082 0392 Change the sentence to live. The manufacturing method of the present invention is pre-roughened by a mechanical electric layer, that is, a template is imprinted on the dielectric layer to cause a vertical depression in the surface of i 2 . Further, the dielectric 5 10 15 = 仃 surface roughened by chemical etching causes the surface of the dielectric layer and the inner surface of the groove to be etched to form a rough surface. By this method, the bite area between the dielectric layer and the circuit layer can be increased, and the inner surface of the groove will form a laterally engraved thick chain surface, because: Dazhongtian adds a dielectric layer and a circuit layer. Adhesion between. For this reason, the green path still has good adhesion by using == two = using a fine-line (8)-shaped package base. Moreover, by the method of the present invention, the adhesion layer formed subsequently on the dielectric layer and the occlusal area between the dielectric layer and the dielectric layer are also increased. Therefore, the adhesion between the layers in the build-up structure of the package substrate is improved. In the step (9) of the method of manufacturing the package substrate, (4) the dielectric layer and the order in which the plurality of dielectric layer openings are formed are not limited. Preferably, the dielectric layer is formed on the surface of the dielectric layer having the grooves to expose the electrical connection; and the dielectric layer has a roughened inner surface of the opening: : the inner surface of the layer = equal groove is such that the surface of the dielectric layer and the inner surface of the grooves are thick, and a plurality of dielectric layer openings are formed on the surface of the dielectric layer having the grooves to expose the plurality of dielectric layers. Electrical connection pad. In the method of the present invention, the surface of the dielectric layer is pre-roughened by template imprinting. 'The number, positional arrangement, shape, depth, and diameter of the projections on the surface of the template are not limited to the requirements of the visual process. Electrical properties of the electrical layer 20
10 1510 15
20 200820392 力穿:Γ二唯:::㈣:電層時，模板表面上凸出部不可 形_為半球狀破=電::絕=規=板之凸出部 更佳為錐狀凸出部。而且，丄不規則狀之凸出部’ 材料口 在本發明之方法中，該模板之 Μ:: 電層即可，較佳為鋼板、不鏽鋼鋼板、 ’’呂口金板、銅板、或銅合金板，更佳為鋼板。 开Μ ’在本發明之方法中，該介電層表面以模板壓印 ^入h文的形狀、深度、及直徑與模板之凸出部相似。 該介電層表面溝紋之形狀較佳為半球狀、錐狀、柱狀、或 不規則狀之溝紋，更佳為錐狀溝紋。 在本發明之方法中，該介電層具有該等溝紋之表面進 ㈣刻以，化其表面時，其_方式係為等向性钱刻。餘 刻^用之藥水不限^，可視製程需要或介電層之材料特性 而疋，較佳之藥水為過錳酸酸鉀溶液。另外，該藥水的濃 度、以及蝕刻時間亦不限定，可視介電層之材料特性、以 及預定之表面粗造度而定。蝕刻完成後，該介電層溝紋之 内表面形貌不定，較佳係形成側向蝕刻的粗糙面。 另外，在本發明之方法中，該電性連接墊之材料不限 定，較佳為銅、或鋁，更佳為銅。該介電層之材料不限定， 較佳係選自 ABF(Ajinomoto Build-up Film)、雙順丁 醯二酸 & 亞 /二氮陕（BT，Bismaleimide triazine)、聯二苯環 丁二稀 (benzocylobutene ; BCB)、液晶聚合物（Liquid Crystal20 200820392 Force wear: Γ二唯::: (4): When the electric layer is used, the convex part on the surface of the template is invisible _ is hemispherical broken = electricity:: absolutely = gauge = the convex part of the board is better as a cone-shaped convex unit. Moreover, the irregular shaped portion of the material is in the method of the present invention. The template may be: an electric layer, preferably a steel plate, a stainless steel plate, a ''lukou gold plate, a copper plate, or a copper alloy. The plate is more preferably a steel plate. In the method of the present invention, the shape, depth, and diameter of the surface of the dielectric layer imprinted with the template are similar to those of the template. The shape of the surface groove of the dielectric layer is preferably a hemispherical shape, a tapered shape, a columnar shape, or an irregular groove shape, and more preferably a tapered groove pattern. In the method of the present invention, the surface of the dielectric layer having the grooves is (4) engraved, and when the surface is formed, the mode is an isotropic ink. The syrup used in the engraving is not limited to ^, depending on the process requirements or the material properties of the dielectric layer. The preferred syrup is potassium permanganate solution. Further, the concentration of the syrup and the etching time are not limited, and may depend on the material properties of the dielectric layer and the predetermined surface roughness. After the etching is completed, the inner surface of the dielectric layer groove is indefinite, and a rough surface which is laterally etched is preferably formed. Further, in the method of the present invention, the material of the electrical connection pad is not limited, and is preferably copper or aluminum, more preferably copper. The material of the dielectric layer is not limited, and is preferably selected from the group consisting of ABF (Ajinomoto Build-up Film), bis-butane azelaic acid & BT (Bismaleimide triazine), and diphenyl sulfonate (benzocylobutene; BCB), liquid crystal polymer (Liquid Crystal
Polymer) 聚亞醯胺（Polyimide ; PI)、聚乙稀 _ (Poly(phenylene ether))、聚四氟乙烯（P〇ly (tetra- 9 200820392 fiu〇r〇ethylene))、芳香尼龍（Aramide)、環 纖維所組成之群組，更佳^ab a及玻璃 士丄 ^ ^ ABFCAjinomoto Build-up Film) 〇 在：發明之方法中，該介電層開口之形成方法不限 疋，車“土係以雷射鑽孔或曝光、顯影形成介電層開口。惟 當利用雷射鑽孔的技術時，復需進行除膠渣（De-smear)作業 以移除因鑽孔所殘留於介電層開口内的膠渣。 在本發明之方法中，於該步驟（F)中該圖㈣金屬㈣ 料不限定，較佳為銅、錫、鎳、鉻、把、鈦、錫/錯或其合 金，更佳為銅。 10 在本^明之方法中，於該步驟（F)中該圖案化金屬層之 形成方法不限定，較佳係以下列步驟形成：首先於該介電 層及該介電層開口表面形成一晶種層；接著於該晶種層表 面形成一阻層，該阻層具有複數個阻層開口，且該阻層開 口對應至該介電層開口之位置；然後於該等阻層開口電鍍 15形成一金屬層；最後移除該阻層、以及被該阻層覆蓋之該 晶種層，即可形成一圖案化金屬層。 在上述圖案化金屬層之形成方法中，該晶種層主要係 作為後述進行電鍍製程所需之電流傳導路徑。其材料係選 自由銅、錫、鎳、鉻、鈦、銅/鉻合金以及錫/鉛合金中任一 20 種材料所組成之群組，較佳地係為使用銅材料，則以濺鍍、 洛鏡及無電電鑛之一者形成，較佳係以無電電鍍方式形 成。若該晶種層係以導電高分子作為晶種層，則以旋轉塗 佈（spin coating )、喷墨印刷（ink>jet pHnting )、網印（screen printing)或壓印（imprinting)等方式形成，其中該導電高 200820392 分子係選自由聚乙炔、聚苯胺以及有機硫聚合物中任 材料所組成之群組。該阻層 種 感光性高分子，例如：乾膜佳地係使用 *。另形成該等阻層開::;=#更佳地係使用乾 佳地係使用曝光以及顯影之方式。〈《㈣方法’較 再者，本發明亦提供—種封裝基板，包括·—基板， ==複數個電性連接塾；-介電層，係位於該基板 =電性連接墊之表面上，其中該介電層具有複數個介電 :開口以暴露該等電性連接墊'以及具有複數個不穿透該 :電層之狀，且該介電層表面及該等溝紋之内表面為粗 =，以及1屬層，其包括有一線路層以及複數個導電 “ ’其中該線路層係疊置於該介電層具有該等溝紋之表 面’該導電結構係穿過該介電層開口以供該線路層電性連 接至該介電層下方之該等電性連接墊。 κ 10 15 20 由於本發明之封褒基板之介電層表面具有溝紋且溝紋 $内表面被_形絲㈣，因此介電層與祕層之間咬 :面積粍力口’而且溝紋的内表面會形成側向蝕刻，進而提 昇介電層與線路層之間的咬合力。此故，本發明之封裝基 板，即使線路很細依然具有良好之附著力。 ，此外本發明之封裝基板復包括一防焊層設置於該介 電層上，且該防焊層具有複數個開口以供設置複數個焊料 凸:。此防焊層之材料不限定，較佳為綠漆或黑漆。則由 於介電層與防烊層之間的咬合面積增加，因此，介電層與 防焊層之間的附著力增加。或者，本發明之封裝基板復包 11 200820392 括另一介電層設置於該介電層上，以形成多層之增層結 構，則由於介電層與介電層之間的咬合面積增加，因此， 介電層與介電層之間的附著力增加。此故，藉由本發明之 封裝基板，可增加封裝基板之增層結構中層與層間的附著 5 力。 另外，在本發明之封裝基板中，該電性連接墊之材料 不限定，較佳為銅、或鋁，更佳為銅。該介電層之材料不 限定，較佳係選自 ABF(Ajinomoto Build_up Film)、雙順丁 醯二酸醯亞胺/三氮阱（BT，Bismaleimide triazine)、聯二苯環 10 丁二烯（benzocylobutene ; BCB)、液晶聚合物（Liquid CrystalPolymer) Polyimide (PI), Poly(phenylene ether), Polytetrafluoroethylene (P〇ly (tetra- 9 200820392 fiu〇r〇ethylene)), Aromatic Nylon (Aramide) , group of ring fibers, better ^ab a and glass gem ^ ^ ABFCAjinomoto Build-up Film) : In the method of invention, the method of forming the opening of the dielectric layer is not limited, the car "earth system" The dielectric layer is formed by laser drilling or exposure and development. However, when using the technology of laser drilling, a de-smear operation is required to remove the residual layer in the dielectric layer due to the drilling. In the method of the present invention, in the step (F), the metal (four) material of the figure (4) is not limited, preferably copper, tin, nickel, chromium, handle, titanium, tin/error or alloy thereof. More preferably, in the method of the present invention, the method for forming the patterned metal layer in the step (F) is not limited, and is preferably formed by the following steps: first, the dielectric layer and the dielectric Forming a seed layer on the surface of the layer opening; then forming a resist layer on the surface of the seed layer, the resist layer having a plurality of resist openings And the resist layer opening corresponds to the position of the opening of the dielectric layer; then forming a metal layer on the resist layer opening plating 15; finally removing the resist layer and the seed layer covered by the resist layer, ie A patterned metal layer can be formed. In the method for forming a patterned metal layer, the seed layer is mainly used as a current conduction path required for performing an electroplating process as described later. The material is selected from the group consisting of copper, tin, nickel, chromium, A group consisting of any of 20 materials of titanium, copper/chromium alloy and tin/lead alloy, preferably copper material, is formed by one of sputtering, mirror and electroless ore, preferably It is formed by electroless plating. If the seed layer is made of a conductive polymer as a seed layer, spin coating, inkjet printing (jet pHnting), screen printing or pressing Formed by imprinting, etc., wherein the conductive high 200820392 molecule is selected from the group consisting of polyacetylene, polyaniline and organic sulfur polymer. The resistive layer of photosensitive polymer, for example: dry film is good The land system uses *. The formation of the resist layer is further improved::;=# More preferably, the method of using exposure and development is performed by using the dry system. <(4) Method 'Moreover, the present invention also provides a package substrate, including a substrate , = = a plurality of electrical connections; - a dielectric layer on the surface of the substrate = electrical connection pad, wherein the dielectric layer has a plurality of dielectrics: openings to expose the electrically connected pads 'and Having a plurality of layers that do not penetrate the electrical layer, and the surface of the dielectric layer and the inner surface of the grooves are thick =, and a 1 layer, comprising a circuit layer and a plurality of conductive "' The layer is stacked on the surface of the dielectric layer having the grooves. The conductive structure passes through the opening of the dielectric layer for electrically connecting the circuit layer to the electrical connection pads under the dielectric layer. κ 10 15 20 Since the surface of the dielectric layer of the sealing substrate of the present invention has grooves and the inner surface of the groove is _-shaped (four), the bite between the dielectric layer and the secret layer: the area of the force port and the groove The inner surface forms a lateral etch, which in turn increases the bite force between the dielectric layer and the circuit layer. Therefore, the package substrate of the present invention has good adhesion even if the wiring is fine. In addition, the package substrate of the present invention further includes a solder resist layer disposed on the dielectric layer, and the solder resist layer has a plurality of openings for providing a plurality of solder bumps. The material of the solder resist layer is not limited, and is preferably green paint or black paint. Then, the occlusal area between the dielectric layer and the tamper resistant layer is increased, and therefore, the adhesion between the dielectric layer and the solder resist layer is increased. Alternatively, the package substrate package 11 200820392 of the present invention includes another dielectric layer disposed on the dielectric layer to form a multi-layered buildup structure, because the occlusal area between the dielectric layer and the dielectric layer is increased, The adhesion between the dielectric layer and the dielectric layer is increased. Therefore, with the package substrate of the present invention, the adhesion between the layers and the layers in the build-up structure of the package substrate can be increased. Further, in the package substrate of the present invention, the material of the electrical connection pad is not limited, and is preferably copper or aluminum, more preferably copper. The material of the dielectric layer is not limited, and is preferably selected from the group consisting of ABF (Ajinomoto Build_up Film), bis(Bismaleimide triazine), biphenyl ring 10 butadiene (Bimaleimide triazine). Benzyllobutene ; BCB), liquid crystal polymer (Liquid Crystal
Polymer)、聚亞醢胺（Polyimide ; PI)、聚乙浠醚 (Poly(phenylene ether))、聚四氟乙稀（Poly (tetra-fluoroethylene))、芳香尼龍（Aramide)、環氧樹脂以及玻璃 纖維所組成之群組。更佳為ABF(Ajinomoto Build-up Film)。 15 在本發明之封裝基板中，該溝紋之形狀不限定，較佳 為半球狀、錐狀、柱狀、或不規則狀之溝紋。且該等溝紋 之内表面形貌不定，較佳為側向蝕刻之粗糙面。 在本發明之封裝基板中，該金屬層之材料不限定，較 佳為銅、錫、鎳、鉻、把、鈦、錫/錯或其合金。 20 此外，在本發明之封裝基板中，復包括一晶種層設置 於該金屬層與該介電層、以及該金屬層與該電性連接墊之 間。該晶種層主要係作為後述進行電鍍製程所需之電流傳 導路徑。其材料係選自由銅、錫、鎳、鉻、鈦、銅/鉻合金 以及錫/鉛合金中任一種材料所組成之群組，較佳地係為使 12 200820392 用銅材料。 自由聚乙炔 該晶種層之材料以可為導電高分子，較佳係選 ♦苯胺以及有機硫聚合物所組成之群組。 10 15 【實施方式】 本=之實施例中該等圖式均為簡化之示意圖。惟該 Γ與本發明有關之元件，其所顯示支元件非為= 其實際實施時之元件數目、形狀等比 例為二選擇性之設計，且其元件佈局型態可能更複雜。 «、彡閱，為本發明_較佳實施例之封裝基板 k U面不思圖。首先’如圖2 A所示，提供一封裝基 板〇 1 至沙一表面具有複數個電性連接墊202。在本實 把例中„亥電性連接塾2〇2係選擇性地連接至導通孔㈣， 以電性連接封裝基板2G1下表面之電性連接墊搬。此導通 孔220連通該封裝基板2〇1之上、下表面，且該導通孔22〇内 =成有導電層22卜並以樹脂222填滿該導通孔22〇。在本 實施例中，該電性連接塾施、以及該導通孔，内壁之導 電層221導電層的材料均為銅。 20 在本實施例中，由於其餘電性連接墊2〇2的結構皆與A 區域之結構大致相同，故後續僅顯示A區域之電性連接墊 202作為代表說明。 接著，請參閱圖2B，其係於圖2八中的a區域放大來看。 如圖2B示，於封裝基板2〇1具有電性連接墊2〇2之表面形成 一介電層203以覆蓋該封裝基板2〇卜以及該電性連接墊2〇2 上。該介電層之材料可選自ABF(Ajin〇moto Build, 13 200820392Polymer), Polyimide (PI), Poly(phenylene ether), Poly (tetra-fluoroethylene), Aramide, Epoxy and Glass A group of fibers. More preferably ABF (Ajinomoto Build-up Film). In the package substrate of the present invention, the shape of the groove is not limited, and is preferably a hemispherical shape, a tapered shape, a columnar shape, or an irregular groove. Moreover, the inner surface of the grooves is indefinite, preferably a rough surface which is laterally etched. In the package substrate of the present invention, the material of the metal layer is not limited, and is preferably copper, tin, nickel, chromium, handle, titanium, tin/error or an alloy thereof. Further, in the package substrate of the present invention, a seed layer is further provided between the metal layer and the dielectric layer, and between the metal layer and the electrical connection pad. This seed layer is mainly used as a current conducting path required for the electroplating process to be described later. The material is selected from the group consisting of copper, tin, nickel, chromium, titanium, copper/chromium alloys, and tin/lead alloys, preferably made of copper material for 12 200820392. Free polyacetylene The material of the seed layer is a group of conductive polymers, preferably selected from the group consisting of aniline and organic sulfur polymers. [Embodiment] In the embodiment of the present invention, the drawings are simplified schematic diagrams. However, the components related to the present invention are not designed to have the same number of components, shapes, and the like, and the component layout pattern may be more complicated. «, read, is the package substrate of the present invention _ preferred embodiment k U face is not considered. First, as shown in Fig. 2A, a package substrate 〇 1 is provided to the surface of the sand having a plurality of electrical connection pads 202. In the present embodiment, the galvanic connection 塾2〇2 is selectively connected to the via hole (4) to electrically connect the electrical connection pads of the lower surface of the package substrate 2G1. The via hole 220 communicates with the package substrate 2 Above and below the 〇1, and the conductive via 22 is formed in the via hole 22, and the via hole 22 is filled with the resin 222. In this embodiment, the electrical connection and the conduction The material of the conductive layer of the conductive layer 221 of the inner wall is copper. 20 In this embodiment, since the structures of the remaining electrical connection pads 2〇2 are substantially the same as those of the A area, only the power of the A area is subsequently displayed. The connection pad 202 is taken as a representative. Next, please refer to FIG. 2B, which is enlarged in the area of a in FIG. 2A. As shown in FIG. 2B, the surface of the package substrate 2〇1 has the electrical connection pads 2〇2. A dielectric layer 203 is formed to cover the package substrate 2 and the electrical connection pad 2〇2. The material of the dielectric layer may be selected from ABF (Ajin〇moto Build, 13 200820392).
Film)、雙順丁醯二酸酸亞胺/三氮牌（bt，Bismaleimide w triazine)、聯二苯環 丁二稀（benzocylobutene，BCB)、液晶聚 合物（Liquid Crystal P〇lymer)、聚亞醯胺（polyimide，PI)、聚 乙烯醚（Poly(phenylene ether))、聚四氟乙烯（Poly (tetra-5 fluoroethylene))、芳香尼龍（Aramide)、環氧樹脂以及玻璃 纖維所組成之群組。在本實施例中，該介電層2〇3之材料為 ABF(Ajinomoto Build-up Film)。 然後’先以機械方式對該介電層203進行預粗化。如圖 2C所示’將一表面具有複數個凸出部2〇5之模板2〇4壓印於 10 該介電層203上，使該介電層203表面203a產生垂直方向之 凹陷。唯壓印時，需避免該模板2〇4之凸出部2〇5穿刺該介 電層203，以免暴露出或者甚至破壞該封裝基板2〇1上的電 性連接墊202或其他導電結構（圖中未示）。該模板之凸出 部205可為半球狀、錐狀、柱狀、或不規則狀之凸出部。而 15 本實施例採用之凸出部205形狀為錐狀凸出部，且可選擇以 不同深度及直徑來控制所欲形成之凹陷大小，但不可穿透 該介電層203。另外，該模板2〇4之材料只要硬度大於介電 層203即可，例如鋼板、或不銹鋼鋼板。在本實施例中，該 模板204之材料為鋼板。 20 雖本實施例以錐狀之凸出部2 〇 5為例說明，但該凸出部 205之形狀、深度、及直徑並非以此為限，可視製程需要或 介電層203之材料特性加以變化。另外，該模板2〇4上凸出 部205的數量、位置配置、與大小也可視情況改變。 14 200820392 ' · 隨後，將該模板204自該介電層203移開。如圖21)所 • 不°亥杈板204移開後，該介電層203表面203a形成複數個 不穿透該介電層203之溝紋206。此溝紋206之形狀、深度、 及直徑大致舆模板204之凸出部205相同。在本實施例中， 5 該介電層203表面形成錐狀之溝紋2〇6。 接著，再以化學蝕刻方式對該介電層2〇3進行表面粗 化。由於蝕刻用之藥水（圖中未示）會進入溝紋2〇6中往不同 方向餘刻（一般為等向性钱刻）。因此，介電層之溝紋 ί 内表面會形成側向蝕刻的粗糙面，其結構如圖2e所示。在 10本實施例中，該藥水之成分可視製程需要或介電層2〇3之材 料特性而定。本實施例採用之蝕刻藥水為過錳酸酸鉀溶 液。另外，該藥水的濃度、以及蝕刻時間也可視介電層203 之材料特性、以及預定之表面粗糙度而定。 完成上述步驟之後，如圖2F所示，於介電層2〇3上形成 15 複數個穿透介電層203之介電層開口 207。此介電層開口 2〇7 之位置需對應於電性連接墊202之位置，以暴露出介電層 C； 203下面的電性連接墊202。在本實施例中，該介電層開口 204係以曝光、顯影或雷射方式形成。 鈿述圖2E及圖2F所述钱刻該介電層203具有該等溝 、、文2 0 6之表面2 0 3、以及形成開口 2 0 7之步驟，亦可視製程 需要，先如圖2E，，於該介電層203具有該等溝紋2〇6之表 面203a形成開口 207，再如圖2F，，蝕刻該介電層2〇3具 有該等溝紋206及開口 207之表面203a，使該介電層表面 203a、該等溝紋2〇6之内表面、以及開口 2〇7之内表面粗 15 200820392 化。惟此後纟買製程係與本實施例相似，故在此不再為文資 ， 述此實施態樣，但並非以此限制本發明。 接著，於該介電層203、以及介電層開口 2〇7上形成一 晶種層208。在本實施例中，該晶種層2〇8為銅，其係以無 5電電鍍之方式形成。再於該晶種層208上形成一具有複數個 阻層開口 210之阻層209,且此阻層開口 210之位置對應於介 電層開口 207。在本實施例中，該阻層2〇9為液態光阻，其 開口 210係以曝光、顯影方式形成。隨之，以電鍍方式於阻 層開口 210内形成一金屬層211，可得到如圖2G結構。隨後， 1〇 再移除阻層209、以及被阻層209覆蓋之晶種層208，即可得 到如圖2H所示之結構。該金屬層211之材料可為銅、錫、鎳、 鉻、鈀、鈦、錫/鉛或其合金。在本實施例中，該金屬層2i i 之材料為銅。 該金屬層211包括有一線路層212以及複數個導電結構 15 213 °亥線路層212係豐置於該介電層2 〇 3具有該等溝紋2 〇 6 之表面，而該導電結構213係穿過該介電層開口 2〇7以供該 線路層211電性連接至該介電層2〇3下方之電性連接墊2〇2。 由於本實施例之介電層203先以機械方式進行預粗 化，再以化學蝕刻方式進行表面粗化，使介電層表面2〇3a 20 以及溝紋206的内表面形成粗糙面，而於線路成型後，可增 加包層203與線路層212之間咬合面積，而且溝紋206的内 表面會开> 成側向餘刻的粗糙面，更大幅增加了介電層與 線路層212之間的附著力。此故，藉由本發明之方法，即使 16 200820392 採用^線距（Fine Piteh)之封裝基板，其線路依然具有良好 之附著力，而可避免線路剝離。 、因此，本實施例可增加介電層203表面粗糙化的效果， 進而增加介電層203和線路層2Π之間的附著力。 5 .然後，如圖21所示，將本實施例圖2价斤示之封裝基板 2〇1之線路層212視為電性連接塾，依所需要之層數重複上 述步驟數次’以製作多層之結構。隨之，於最頂端之介電 層203b上塗覆綠漆作為防谭層214。再於防焊層2μ形成開 口以顯露防焊層214下面之部分線路層212以作為電性連接 10墊202a。取後，將複數個焊料凸塊215設置於防焊層214的 開口中與電性連接墊2〇2a電性導接，即完成本實施例之封 裝基板。 如圖2H所示，本實施例介電層與介電層之間、以及介 電層與防焊層之間的咬合面積也都增加。因此，藉由本實 15施例之方法所製造之封裝基板，可增加封裝基板之增層結 構中，介電層和線路層之間、介電層與介電層之間、以及 /1電層與防焊層之間的咬合力，進而提高封裝基板增層結 構中層與層間的附著力。 上述實施例僅係為了方便說明而舉例而已，本發明所 20主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 【圖式簡單說明】 圖1A至1F係習知之封裝基板製造方法之剖面示意圖。 17 200820392 圖2A至21係本發明一較佳實施例之封裝基板製造方法之剖 面示意圖。 【主要元件符號說明】 封裝基板101，201 電性連接塾102, 202, 202a 介電層 103, 203, 203b 介電層開口 104, 207 晶種層105, 208 阻層 106, 209 阻層開口 107, 210 金屬層108, 211 導通孔109, 220 模板204 凸出部205 溝紋206 線路層212 導電結構213 防焊層214 焊料凸塊21 5 導電層221 介電層表面203a 樹脂222 18Film), bismeimide w triazine, benzocylobutene (BCB), liquid crystal polymer (Liquid Crystal P〇lymer), poly Group of polyimide (PI), Poly(phenylene ether), Poly (tetra-5 fluoroethylene), Aramide, epoxy resin and glass fiber . In this embodiment, the material of the dielectric layer 2〇3 is ABF (Ajinomoto Build-up Film). The dielectric layer 203 is then pre-roughened mechanically. As shown in Fig. 2C, a template 2? 4 having a plurality of projections 2? 5 on one surface is imprinted on the dielectric layer 203, so that the surface 203a of the dielectric layer 203 is recessed in the vertical direction. In the case of embossing only, the embossing portion 2 〇 5 of the stencil 2 〇 4 is prevented from puncturing the dielectric layer 203 to avoid exposing or even destroying the electrical connection pads 202 or other conductive structures on the package substrate 2 〇 1 ( Not shown in the figure). The bulging portion 205 of the template may be a hemispherical, tapered, columnar, or irregular shaped projection. The protrusion 205 used in this embodiment is shaped like a tapered protrusion, and the depth of the recess to be formed can be controlled by different depths and diameters, but the dielectric layer 203 cannot be penetrated. Further, the material of the template 2〇4 may be any hardness as compared with the dielectric layer 203, such as a steel plate or a stainless steel plate. In this embodiment, the material of the template 204 is a steel plate. 20 Although the embodiment has a tapered projection 2 〇 5 as an example, the shape, depth, and diameter of the projection 205 are not limited thereto, and may be visually required or the material properties of the dielectric layer 203. Variety. Further, the number, positional arrangement, and size of the projections 205 on the template 2〇4 may be changed as appropriate. 14 200820392 ' Then, the template 204 is removed from the dielectric layer 203. As shown in Fig. 21), the surface 203a of the dielectric layer 203 forms a plurality of grooves 206 that do not penetrate the dielectric layer 203. The shape, depth, and diameter of the groove 206 are substantially the same as the projections 205 of the template 204. In this embodiment, 5 the surface of the dielectric layer 203 is formed with a tapered groove 2〇6. Then, the dielectric layer 2〇3 is subjected to surface roughening by chemical etching. Since the syrup used for etching (not shown) will enter the groove 2〇6 and engrave in different directions (generally isotropic). Therefore, the inner surface of the trench layer of the dielectric layer forms a laterally etched rough surface, and its structure is as shown in Fig. 2e. In the ten embodiment, the composition of the syrup may depend on the process requirements or the material properties of the dielectric layer 2〇3. The etching syrup used in this embodiment is a potassium permanganate solution. In addition, the concentration of the syrup and the etching time may also depend on the material properties of the dielectric layer 203 and the predetermined surface roughness. After the above steps are completed, as shown in FIG. 2F, a plurality of dielectric layer openings 207 penetrating the dielectric layer 203 are formed on the dielectric layer 2〇3. The position of the dielectric layer opening 2〇7 needs to correspond to the position of the electrical connection pad 202 to expose the electrical connection pad 202 under the dielectric layer C; In the present embodiment, the dielectric layer opening 204 is formed by exposure, development or laser. 2E and FIG. 2F, the dielectric layer 203 has the same trench, the surface of the surface 206, and the step of forming the opening 2 0 7 , which can also be regarded as a process requirement, as shown in FIG. 2E. Opening 207 is formed on the surface 203a of the dielectric layer 203 having the grooves 2?6, and as shown in FIG. 2F, the dielectric layer 2?3 has the grooves 206 and the surface 203a of the opening 207. The dielectric layer surface 203a, the inner surface of the grooves 2〇6, and the inner surface roughness 15200820 of the opening 2〇7 are made. However, the subsequent purchase process is similar to the present embodiment, and therefore is not a text here, and the embodiment is described, but the invention is not limited thereto. Next, a seed layer 208 is formed on the dielectric layer 203 and the dielectric layer opening 2〇7. In the present embodiment, the seed layer 2〇8 is copper, which is formed by electroless plating. A resist layer 209 having a plurality of resistive opening 210 is formed on the seed layer 208, and the resist opening 210 is located at a position corresponding to the dielectric layer opening 207. In the present embodiment, the resist layer 2〇9 is a liquid photoresist, and the opening 210 is formed by exposure and development. Accordingly, a metal layer 211 is formed in the barrier opening 210 by electroplating, and a structure as shown in Fig. 2G can be obtained. Subsequently, the resist layer 209 and the seed layer 208 covered by the resist layer 209 are removed, and the structure as shown in Fig. 2H is obtained. The material of the metal layer 211 may be copper, tin, nickel, chromium, palladium, titanium, tin/lead or alloys thereof. In this embodiment, the material of the metal layer 2i i is copper. The metal layer 211 includes a circuit layer 212 and a plurality of conductive structures 15 213 ° The circuit layer 212 is deposited on the surface of the dielectric layer 2 〇 3 having the grooves 2 〇 6 , and the conductive structure 213 is worn The dielectric layer opening 2〇7 is electrically connected to the circuit layer 211 to the electrical connection pad 2〇2 under the dielectric layer 2〇3. Since the dielectric layer 203 of the present embodiment is pre-roughened by mechanical means, the surface is roughened by chemical etching, so that the surface of the dielectric layer 2〇3a 20 and the inner surface of the groove 206 form a rough surface. After the line is formed, the occlusal area between the cladding layer 203 and the circuit layer 212 can be increased, and the inner surface of the groove 206 is opened to form a laterally rough surface, which further increases the dielectric layer and the circuit layer 212. Adhesion between. Therefore, with the method of the present invention, even if 16 200820392 uses a package substrate of Fine Piteh, the wiring still has good adhesion, and line peeling can be avoided. Therefore, the present embodiment can increase the surface roughening effect of the dielectric layer 203, thereby increasing the adhesion between the dielectric layer 203 and the wiring layer 2Π. 5. Then, as shown in FIG. 21, the circuit layer 212 of the package substrate 2〇1 shown in FIG. 2 is regarded as an electrical connection port, and the above steps are repeated several times according to the required number of layers. Multi-layer structure. Accordingly, green lacquer is applied as the anti-tank layer 214 on the topmost dielectric layer 203b. Further, an opening is formed in the solder resist layer 2μ to expose a portion of the wiring layer 212 under the solder resist layer 214 as the electrical connection 10 pad 202a. After the solder bumps 215 are disposed in the openings of the solder resist layer 214 and electrically connected to the electrical connection pads 2〇2a, the package substrate of the embodiment is completed. As shown in Fig. 2H, the nip area between the dielectric layer and the dielectric layer and between the dielectric layer and the solder resist layer of the present embodiment is also increased. Therefore, the package substrate manufactured by the method of the embodiment of the present invention can increase the build-up structure of the package substrate, between the dielectric layer and the wiring layer, between the dielectric layer and the dielectric layer, and/or the electrical layer. The biting force with the solder resist layer further improves the adhesion between the layers in the build-up structure of the package substrate. The above-described embodiments are merely examples for convenience of description, and the scope of the claims of the present invention is determined by the scope of the claims, and is not limited to the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1F are schematic cross-sectional views showing a conventional method of manufacturing a package substrate. 17 200820392 Figures 2A through 21 are schematic cross-sectional views showing a method of fabricating a package substrate in accordance with a preferred embodiment of the present invention. [Description of main component symbols] Package substrate 101, 201 is electrically connected to 塾102, 202, 202a dielectric layer 103, 203, 203b dielectric layer opening 104, 207 seed layer 105, 208 resist layer 106, 209 resist layer opening 107 , 210 metal layer 108, 211 via 109, 220 template 204 protrusion 205 groove 206 circuit layer 212 conductive structure 213 solder mask 214 solder bump 21 5 conductive layer 221 dielectric layer surface 203a resin 222 18