200806126 九、發明說明： 【發明所屬之技術領域】 本發明係關於用以製作細線路之導通孔以及縮小導通 孔距離製作細線路之方法，其係藉由較佳的線路圖案化技 5 術以縮小導通孔之孔環外徑，進而可縮小導通孔距離，以 達到更細小線路的需求。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 10 能、高性能研發趨勢，為滿足半導體封裝建高積集度 (Integration)及微型化（Miniaturization)的封裝需求，以供更 多主動、被動元件及線路載接，承載半導體晶片之電路板 籍由配合高線路密度之積體電路（Integrated circuit)需求， 以在相同電路板單位下容納更多數量的線路及元件。 15 為因應微處理器、晶片組與繪圖晶片等高效能晶片之 運算需求，電路板亦需要提昇其傳遞晶片訊號、改善頻寬、 > 控制阻抗等功能，來成就高I/O數封裝件的發展。然而，未 符合半導體封裝件輕薄短小、多功能、高速度及高頻化的 開發方向，電路板已朝向細線路及小孔徑發展，現有電路 2〇 板製程中的100微米之線路尺寸逐漸不符合需求。 在習知的電路板中，其製造的步驟如下，請參閱圖1A 至圖1E，係為傳統製造具有大孔環（Land)之導通孔之剖視 圖。而圖2則為具有此大孔環之導通孔之俯視圖。 如圖1A所示，提供一載板11，此載板11可以為例如銅 200806126 箔基板，且此載板11中具有複數個貫穿孔12。接著，如圖 4 1B所不，於此載板11表面中經由直接鍍覆的方式形成一導 - 電層13。再如圖1C所示，於此導電層13的表面中形成一銅 金屬層14。之後，如圖1D所示，在此貫穿孔12中灌入一絕 5緣樹脂15，再如圖1E所示，於載板11表面塗覆光阻，以及 以曝光顯影形成圖案化光阻18，其中為補償曝光之對位精 度誤差，於貫穿孔12上方之圖案化光阻18尺寸均大於貫穿 孔12之孔徑。最後，如圖1F所示，於上述的載板“表面上， • 蝕刻銅金屬層14及覆蓋於其下的導電層13以製作成線路。 10而可以得到如圖2所示，係為此製程中電路板的俯視圖。 由圖1E以及圖2中可以得知，載板i j表面上圍繞於導通 孔16的銅金屬層15，即為一孔環17(如圖2所示），由此製程 所製得的電路板，其孔環17的寬度通常都至少大於75微 米。當圍繞於導通孔周圍的金屬層所形成的孔環17，其寬 15度太見，右導通孔與導通孔之間的距離更近時會造成孔環 Π與孔壞17之間相接觸，而需預留適當的導通孔距離，故 • 無法提昇線路的佈線能力。 由於可縮小積體電路面積且具有高密度與多接腳化特 性等之封裝件以曰漸成為封裝市場上的主流，因此，在封 2〇 ^尺寸不斷縮小至幾乎與晶片同大（約僅為晶片之Μ倍） 時’如何開發與其搭配的細線路與高線路密度之電路板， 同時不致造成提高過多製造成本，無疑是半導體產業乃至 其他相關電子產業進人下―世代技術之重要研發課題。 200806126 【發明内容】 • 有鏗於此，本發明提供一種用以製作細線路之導渴 - 孔，其包括：一載板，其具有複數個貫穿孔，此等貫穿= 覆蓋有一導電層、一金屬層以及一填充材料以作為 5 孔，而金屬層係可配置於導電層與填充材料之間，且於= 板表面上環繞著填充材料，以形成一孔環，孔環之外π 大於貫穿孔之孔徑。 工 依據上述本發明之用以製作細線路之導通孔，例如可 馨由下述但不限於此之步驟製作。 10 本發明係亦提供—種料導通孔距離製作細線路之方 法，其步驟包括：首先可以提供一載板，且此載板 數個貫穿孔。接著，於具有此貫穿孔之載板的表面形成一 導電層。然後，於導電層的表面形成一金屬層。再於貫穿 孔内注人—填充材料’使貫穿孔形成-導通孔，此導通孔 15係可以連接上下表面的電路。然後，於載板的表面上形成 木化阻層’其中，貫穿孔表面之阻層其尺寸係不大於 ⑩ 貝牙孔之孔&。接著’名虫刻金屬層及覆蓋於此金屬層之導 電層。最後，移除阻層，即可為本發明縮小導通孔距離的 線路製程。 . 20 料明中的载板係只要可以作為線路饰局的承載板均 可’較佳為使用鋼箱基板（C〇pper 以偷伽 ;CCL)、 兩層或多層電路板。另在载板中的貫穿孔較佳地可以雷射 鑽孔或機械鑽孔之方式形成，此貫穿孔主要係在後續製程 中作為使載板的上表面及下表面的線路導通。 200806126 盆可山二=中在具有貫穿孔的載板上所形成的導電層， 自由銅'、二金：堆叠數層的金屬所組成’較佳地係選 5 15 之群組之-者、Λ、敛、銅-絡合金以及錫_錯合金所組成 在作為可錢錢，而導電層主要的目的 外二屬層時所需要的電流傳導，另 及化學沈積：：ΓΓ有嗔、蒸链、無電電鍍 形成導電層。 成。較佳地可以使用無電⑽的方式 本發明的步驟中，^彳曾 由金屬、人泰 S 电a形成金屬層時，同樣的可 钔鋰u堆豐數層的金屬所組成，較佳地可以使用 鋼、鎳、絡、鈦、錮/饮人入』 5 J以便用 用銅，此金屬層在後續錯合=°更佳地係可以使 連接墊之用。另外可以視需要作树路或電性 無電電鑛之方式开L r以形成的方式有以電鑛或 此金屬層。/絲係可則线電料方式形成 注入料在!穿孔内形成金屬層後，此貫穿孔内所 為絕㈣r P 〃要疋絕緣材料即可，較佳的材料係可 材料 更佳地則可以使用環氧樹脂㈣㈣作為填充 依據本發明製作細線路的 驟中，可以微影技術中的曝光 ^將阻層圖案化的步 先或者疋紫外光照射，—般而言，在傳統的製程中ί = 20 200806126 以i外光知、射，使阻層圖案化，但是本發明較佳地係可以 使用雷射光照射’可以更精確的達到所需要的圖案以及位 置。 在本發明中，將金屬層及覆蓋於其下之導電層圖案化 時，係主要使用姓刻的方式將所不需要的金屬層以及覆蓋 於此不而要的金屬層之導電層移除，豸而可以製作出所需 ㈣線路來’亚且’可以製作出細線路⑴狀卩滅)以及高 佈線密度之電路板。200806126 IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a via of a thin line and reducing the distance between the vias to form a thin line by a preferred line patterning technique The outer diameter of the via hole of the via hole is reduced, and the via hole distance can be reduced to meet the requirement of a finer circuit. [Prior Art] With the rapid development of the electronics industry, electronic products are gradually entering the trend of multi-function, high-performance research and development, in order to meet the packaging requirements of semiconductor package building integration and miniaturization. For more active and passive components and line loading, the board carrying the semiconductor wafer is required by a high circuit density integrated circuit to accommodate a larger number of lines and components in the same board unit. . 15 In order to meet the computing needs of high-performance chips such as microprocessors, chipsets and graphics chips, the board also needs to improve its transfer of chip signals, improved bandwidth, > control impedance to achieve high I/O number packages. development of. However, the development direction of semiconductor package is light, short, versatile, high speed and high frequency. The circuit board has been developed toward thin lines and small apertures. The size of the 100 micron line in the existing circuit 2 〇 process is gradually not met. demand. In the conventional circuit board, the manufacturing steps are as follows, referring to Figs. 1A to 1E, which are cross-sectional views of a conventionally manufactured via hole having a large hole. 2 is a top view of the via hole having the large aperture ring. As shown in FIG. 1A, a carrier 11 is provided. The carrier 11 can be, for example, a copper 200806126 foil substrate, and the carrier 11 has a plurality of through holes 12 therein. Next, as shown in Fig. 41B, a conductive layer 13 is formed on the surface of the carrier 11 via direct plating. Further, as shown in Fig. 1C, a copper metal layer 14 is formed in the surface of the conductive layer 13. Thereafter, as shown in FIG. 1D, a permanent resin 15 is poured into the through hole 12, and as shown in FIG. 1E, a photoresist is coated on the surface of the carrier 11, and a patterned photoresist 18 is formed by exposure and development. In order to compensate for the alignment accuracy error of the exposure, the size of the patterned photoresist 18 above the through hole 12 is larger than the aperture of the through hole 12. Finally, as shown in FIG. 1F, on the surface of the carrier plate described above, the copper metal layer 14 and the conductive layer 13 covering the underlying layer are etched to form a line. 10 can be obtained as shown in FIG. A top view of the circuit board in the process. As can be seen from FIG. 1E and FIG. 2, the copper metal layer 15 surrounding the via hole 16 on the surface of the carrier ij is a hole ring 17 (as shown in FIG. 2). The circuit board made by the process generally has a width of at least 75 μm. The hole ring 17 formed around the metal layer around the via hole is too wide, 15 degrees wide, and the right via hole and the via hole are formed. When the distance between them is closer, the hole ring Π and the hole 17 are in contact with each other, and the proper via hole distance is reserved, so that the wiring capacity of the line cannot be improved. Packages such as density and multi-pinning characteristics are becoming the mainstream in the packaging market, so how to develop when the size of the package is shrinking to almost the same size as the wafer (about twice the wafer) With its fine lines and high line density boards, It will undoubtedly lead to an increase in excessive manufacturing costs, which is undoubtedly an important research and development topic for the semiconductor industry and other related electronics industries. 200806126 [Invention] In this regard, the present invention provides a guide for making fine lines. a thirst-hole, comprising: a carrier plate having a plurality of through holes, the through layer being covered with a conductive layer, a metal layer and a filling material as 5 holes, and the metal layer being configurable in the conductive layer and filling Between the materials, and around the surface of the plate, a filling material is formed to form a hole ring, and the outside of the hole ring π is larger than the hole diameter of the through hole. According to the above-mentioned invention, the through hole for making the fine line, for example, can be sweet. The invention is made by the following steps, but is not limited to the following. 10 The present invention also provides a method for making a fine line of a material via hole, the steps of which include: firstly, a carrier plate is provided, and the carrier plate has a plurality of through holes. Forming a conductive layer on the surface of the carrier having the through hole. Then, forming a metal layer on the surface of the conductive layer, and filling the through hole 'The through hole is formed into a via hole, and the via hole 15 is a circuit capable of connecting the upper and lower surfaces. Then, a wooden resist layer is formed on the surface of the carrier, wherein the resist layer of the through hole surface has a size of not more than 10 The hole of the tooth hole & then the 'nickname of the metal layer and the conductive layer covering the metal layer. Finally, remove the barrier layer, which can be used to reduce the distance of the via hole in the line process of the invention. 20 As long as the carrier board can be used as a carrier board of the line decoration, it is preferable to use a steel box substrate (C〇pper to steal the gamma; CCL), two or more layers of circuit boards, and the through holes in the carrier board are preferably used. The ground can be formed by laser drilling or mechanical drilling, and the through hole is mainly used to make the line connecting the upper surface and the lower surface of the carrier plate in the subsequent process. 200806126 Pot Keshan 2 = medium in the through hole The conductive layer formed on the board, free copper ', two gold: stacked several layers of metal composition' is preferably selected from the group of 5 15 - Λ, 敛, convergence, copper-coalloy and tin-alloy The main purpose of the conductive layer The current conduction required for the outer two layers, and chemical deposition: ΓΓ 嗔, steamed chain, electroless plating to form a conductive layer. to make. Preferably, the method of the present invention can be used in the step of the present invention. When the metal layer is formed of a metal or a metal layer, the same layer of metal can be formed. Use steel, nickel, tantalum, titanium, niobium / drinker into the 5 J to use copper, this metal layer in the subsequent mismatch = ° better to make the connection pad. In addition, it is possible to open the Lr in the manner of a tree or an electric non-electrical ore to form an electric ore or metal layer. /Wire system can be formed by wire material forming the injection material in the through hole to form a metal layer, the through hole is absolutely (four) r P 〃 疋 insulation material, the preferred material can be better material can be used Epoxy Resin (4) (4) As a filling step in the fabrication of thin wires according to the present invention, the exposure in the lithography technique can be used to pattern the resist layer first or 疋 ultraviolet light, in general, in the conventional process ί = 20 200806126 The resist layer is patterned by the external light, but the invention is preferably irradiated with laser light to more accurately achieve the desired pattern and position. In the present invention, when the metal layer and the conductive layer covering the underlying layer are patterned, the unnecessary metal layer and the conductive layer covering the unnecessary metal layer are mainly removed by using a surname, In the meantime, it is possible to create a circuit board that requires (4) lines to make a fine line (1) and a high wiring density.
10 15 、在本發明中，在導通孔中的導電層與金屬層，具厚度 係為約15至25陣。更具體而言，於載板表面環繞於導通孔 上方之金屬層’亦即形成—孔環，其寬度則約為15至25_ 其係與導通孔中的導電層與金屬層的厚度大致相同。 本發明因為習知導通孔距離的設計無法製作較佳的知 =路’其主要的原因在於在載板表面上，圍繞於導通孔周 圍的金屬層所形成的孔環，其寬度太寬，若導通孔與_ 距雔更近時會造成孔環與孔環之間 通孔距離，藉由縮小孔環之設計，可以使得 =查與¥通孔之間的距離縮小，提昇線路的佈線能力， 進而達到可製作更細小的線路以及高饰線密度之電路板。 【實施方式】 係' 由特定的具體實施例說明本發明之實施; 式’热驾此技蟄之人式可由本說堂 了鉉士政⑽^ 丰Λ月曰所揭示之内容輕易由 了解本發明之其他優點與功 刀议本务明亦可藉由其他不戶 20 200806126 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 請參考圖3A至3E以及圖4A至4E，其中，圖3A至3E係 5 為製造縮小導通孔距離製作細線路之方法的剖視圖；而圖 4A至4E則分別為圖3A至3E之俯視圖。然而該等圖式均為簡 化之示意圖。惟該等圖示僅顯示與本發明有關之元件，其 所顯示支元件非為實際實施時之態樣，其實際實施時之元 件數目、形狀等比例為一選擇性之設計，且其元件佈局型 10 態可能更複雜。 如圖3A及4A所示，首先提供一個載板21，此載板21在 本例中係使用銅箔基板，此外在此載板中復以機械或雷射 鑽孔等方式將此載板21鑽設多個貫穿孔22，則形成如圖4A 所示的具有貫穿孔22之載板21。 15 接著，如圖3B及4B所示，可以利用濺鍍、蒸鍍、無電 電鍍或化學沈積之方式於圖3 A中的載板21表面及貫穿孔22 内的孔壁沉積一層導電層23，在本例中則使用無電電鍍之 > 方式沉積。其中，形成此導電層23主要的目的在於可以藉 由電流傳導的路徑，以在載板21表面上以及貫穿孔22的孔 20 壁上可以形成一具有如圖3C及4C所示之足夠厚度的金屬層 24。因此，雖然可以使用許多不同的金屬作為導電層23， 然而，本實施例則使用銅作為導電層23，以使其具有良好 的導通性。 如圖3C及4C所示，此金屬層24可以使用銅、鎳、鉻、 10 200806126 欽、鋼/鉻合金或錫/鉛合金，而本實施例則使用銅作為金屬 層24，並且以電鍍的方式形成。 10 15 接著’如圖3D以及4D所示，復以一填充材料25，例如 可以為環氧樹脂填滿如圖3C所示中的貫穿孔22，因此，可 以形成一個電鍍導通孔26，藉以電性導通載板21上下表面 的金屬層24。然後，在此具有導通孔26的載板21之上下表 面上分別形成一阻層27，而此阻層的材料為光阻。然後經 由微影技術，即曝光與顯影之方式將此阻層27圖案化，其 中，曝光的製程中，取代傳統的紫外光，係主要以雷射光 作為光源。而使用雷射光作為光源的原因係可以精確的製 作所需要的位置。而顯影則是將載板表面於曝光後所轉移 的圖案顯現出來。此圖案化後的阻層27，係大致上覆蓋住 且此阻層27的尺寸不大於載板21的貫穿孔以之孔徑，也就 ，說，此圖案化後的阻層27之寬度大致上與貫穿孔22的孔 徑相同，其俯視圖則如圖41)所示。 …最後’如圖3E以及4E所*，接著完成上述的步驟之 後，進行線路的佈局，也就是將如_中的載板以上下表 面的金屬層.24進行钕刻，同時對應於被㈣掉的金屬層24 之^電層23，亦一起移除，而部分顯露出載板21的表面， 此時，導通孔26表面附近财金屬層24，㈣謂的孔環μ， 此孔環則寬度僅料約15〜25_已，也就是說在進行 機械或雷射鐵孔時可以將導通孔與導通孔之間的距離更為 ^近，並且同時可以製作出更精確，更細線路㈣路佈局。 線路佈局完後，再移除阻層，可以得縣發明之縮小導通 20 200806126 孔距離製作細旅路之方法。 另，本發明係提供一種用以製作細線路之導通孔，如 圖3E所示，其主要包括：一載板21，其具有複數個貫穿孔 22，此等貫穿孔22覆蓋有一導電層23、一金屬層24以及一 5 填充材料25以作為一導通孔26，而金屬層24係可配置於導 電層23與填充材料25之間，且於載板21表面上環繞著填充 材料25，以形成一孔環28，此孔環28之外徑不大於貫穿孔 22之孔徑。 綜上所述，藉由本發明之縮小導通孔距離製作細線路之 10 方法，改變傳統製程中導通孔外圍會有大的孔環（約大於 75μπι)，本發明可以精確減小導通孔外圍的孔環（約 15〜25μπι)，也因此，在載板中形成貫穿孔時，可以將貫穿 孔的密集度提昇，也不怕後續製程中所形成的大孔環，而 影響了電路板整體的良率以及無法形成一細線路結構等缺 15 失，俾提供了一具有細線路的高佈線密度之電路板結構。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 > 於上述實施例。 20 【圖式簡單說明】 圖1Α至1F係習知之製作具有大孔環之導通孔之剖視 圖。 圖2係習知之具有此大孔環之導通孔之俯視圖。 圖3 A至3 E係本發明一較佳實施例之製造縮小導通孔距 12 200806126 離製作細線路之方法的剖視圖。 圖4A至4E係本發明一較佳實施例之製造縮小導通孔距 離製作細線路之方法的俯視圖。 【主要元件符號說明】 11，21載板 13,23導電層 15 絕緣樹脂 16,26導通孔 27 阻層 12,22貫穿孔 14,24金屬層 25 填充材料 Π，28孔環 18 光阻10 15 In the present invention, the conductive layer and the metal layer in the via hole have a thickness of about 15 to 25 arrays. More specifically, the metal layer 'on the surface of the carrier plate surrounding the via hole' is formed as a hole ring having a width of about 15 to 25 mm which is substantially the same as the thickness of the conductive layer and the metal layer in the via hole. The invention is not capable of fabricating a better known method because of the conventional via hole distance design. The main reason is that the width of the hole ring formed around the metal layer around the via hole on the surface of the carrier plate is too wide. When the via hole is closer to the _ distance, the distance between the hole ring and the hole ring is caused. By reducing the design of the hole ring, the distance between the check hole and the hole can be reduced, and the wiring capacity of the line can be improved. In turn, it is possible to achieve a circuit board that can produce finer lines and high-density line density. [Embodiment] The embodiment of the present invention will be described by a specific embodiment; the type of the person who is hot-driving can be easily understood by the presently disclosed contents of the 铉士政(10)^丰Λ月曰Other advantages and advantages of the invention may also be implemented or applied by other specific embodiments of the invention. The details in this specification may also be based on different viewpoints and applications without departing from the invention. Various modifications and changes are made under the spirit. 3A to 3E and FIGS. 4A to 4E, wherein FIGS. 3A to 3E are cross-sectional views showing a method of fabricating a thin line for reducing the via hole distance; and FIGS. 4A to 4E are top views of FIGS. 3A to 3E, respectively. However, these figures are simplified diagrams. However, the illustrations only show the components related to the present invention, and the displayed components are not in actual implementation, and the actual number of components, the shape, and the like are designed in an optional manner, and the component layout thereof. Type 10 states may be more complicated. As shown in FIGS. 3A and 4A, first, a carrier 21 is provided. In this example, a copper foil substrate is used, and in this carrier, the carrier 21 is mechanically or laser-drilled. A plurality of through holes 22 are drilled to form a carrier plate 21 having a through hole 22 as shown in FIG. 4A. 15, as shown in FIG. 3B and FIG. 4B, a conductive layer 23 may be deposited on the surface of the carrier 21 and the hole in the through hole 22 in FIG. 3A by sputtering, evaporation, electroless plating or chemical deposition. In this case, it is deposited by electroless plating. The main purpose of forming the conductive layer 23 is to form a current having a sufficient thickness as shown in FIGS. 3C and 4C on the surface of the carrier 21 and the hole 20 of the through hole 22 by a current conduction path. Metal layer 24. Therefore, although many different metals can be used as the conductive layer 23, this embodiment uses copper as the conductive layer 23 to have good conductivity. As shown in FIGS. 3C and 4C, the metal layer 24 may use copper, nickel, chromium, 10 200806126 chin, steel/chromium alloy or tin/lead alloy, while this embodiment uses copper as the metal layer 24 and is plated. The way is formed. 10 15 Next, as shown in FIGS. 3D and 4D, a filling material 25 is applied, for example, the epoxy resin can be filled with the through holes 22 as shown in FIG. 3C, and thus, a plating via hole 26 can be formed, thereby electrically The metal layer 24 on the upper and lower surfaces of the carrier 21 is electrically connected. Then, a resist layer 27 is formed on the upper surface of the carrier 21 having the via holes 26, and the material of the resist layer is photoresist. This resist layer 27 is then patterned by lithography, i.e., exposure and development, wherein the exposure process, in place of conventional ultraviolet light, is primarily based on laser light. The reason for using laser light as a light source is to accurately produce the desired position. The development is to reveal the pattern transferred from the surface of the carrier after exposure. The patterned resist layer 27 is substantially covered and the size of the resist layer 27 is not larger than the through hole of the carrier 21, so that the width of the patterned resist layer 27 is substantially The hole diameter is the same as that of the through hole 22, and its top view is as shown in Fig. 41). ...finally' as shown in Figures 3E and 4E, and then after the above steps are completed, the layout of the line is performed, that is, the metal layer .24 of the upper surface of the carrier above the board is etched, and corresponding to the (four) The electrical layer 23 of the metal layer 24 is also removed together, and partially reveals the surface of the carrier 21, at this time, the metal layer 24 near the surface of the via hole 26, (4) the aperture ring μ, the width of the hole ring It only takes about 15~25_, which means that the distance between the via and the via can be closer when mechanical or laser holes are made, and at the same time, a more precise and finer line (four) can be made. layout. After the layout of the line is completed, the barrier layer is removed, and the invention can be reduced by the invention. 20 200806126 Hole distance method for making the tour road. In addition, the present invention provides a through hole for making a thin line, as shown in FIG. 3E, which mainly includes: a carrier 21 having a plurality of through holes 22, the through holes 22 being covered with a conductive layer 23, A metal layer 24 and a 5 filling material 25 are used as a via hole 26, and the metal layer 24 is disposed between the conductive layer 23 and the filling material 25, and surrounds the filling material 25 on the surface of the carrier board 21 to form A hole ring 28 having an outer diameter no larger than the diameter of the through hole 22. In summary, according to the method of reducing the via hole distance of the present invention to make a fine line 10, a large hole ring (about more than 75 μm) is formed in the periphery of the via hole in the conventional process, and the present invention can accurately reduce the hole around the via hole. Ring (about 15~25μπι), therefore, when the through hole is formed in the carrier, the density of the through hole can be increased, and the large hole ring formed in the subsequent process is not afraid, which affects the overall yield of the circuit board. As well as the inability to form a thin circuit structure, etc., a circuit board structure with a high wiring density of fine lines is provided. The above-described embodiments are merely examples for convenience of description, and the scope of the claims is intended to be based on the scope of the claims, and not limited to the above embodiments. 20 [Simple description of the drawings] Figs. 1A to 1F are cross-sectional views showing the fabrication of via holes having large aperture rings. Figure 2 is a top plan view of a conventional via having such a large aperture ring. 3A to 3E are cross-sectional views showing a method of fabricating a fine wiring by making a reduced via pitch 12 200806126 in accordance with a preferred embodiment of the present invention. 4A through 4E are top views of a method of fabricating a reduced via pitch to produce a thin trace in accordance with a preferred embodiment of the present invention. [Main component symbol description] 11, 21 carrier board 13, 23 conductive layer 15 insulating resin 16, 26 via hole 27 resist layer 12, 22 through hole 14, 24 metal layer 25 filling material Π, 28 hole ring 18 photoresist
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