TW200806125A - Plasma semi additive process method for manufacturing PCB - Google Patents

Plasma semi additive process method for manufacturing PCB Download PDF

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Publication number
TW200806125A
TW200806125A TW095145314A TW95145314A TW200806125A TW 200806125 A TW200806125 A TW 200806125A TW 095145314 A TW095145314 A TW 095145314A TW 95145314 A TW95145314 A TW 95145314A TW 200806125 A TW200806125 A TW 200806125A
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Taiwan
Prior art keywords
plasma
pattern
copper
substrate
dfr
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TW095145314A
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Chinese (zh)
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TWI312649B (en
Inventor
Tae-Il Baek
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Jesagi Hankook Ltd
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/09Treatments involving charged particles
    • H05K2203/095Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1476Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal

Abstract

Disclosed herein is a method of manufacturing a printed circuit board using a plasma semi-additive process (PSAP), including: a first plasma-treating step of improving the adhesion of a DFR; a second plasma-treating step of performing descumming and surface-reforming by plasma-treating the surface between pattern walls formed after the first plasma-treating step; a third plasma- treating step of performing descumming and surface-reforming by forming a circuit by plating copper between the plasma-treated pattern walls, removing the pattern walls through a first etching step while copper remains on the substrate, and then plasma-treating the surface of the exposed substrate and the copper- plated surface; and a second etching step of completing an electric circuit by finally etching the plasma-treated substrate.

Description

200806125 九、發明說明: 【發明所屬之技術領域】 本發明係關於印刷電路基板製造用之PSAP((電漿半加 成,Plasma Semi Additive Process)方法,詳而言之係關於 一種印刷電路基板製造用PSAP方法,在進行印刷電路基 板製造用之SAP(半加成,Semi Additive Process)製程時, 利用電漿來進行洗淨、蝕刻及表面改質以提高微細電路圖 案與底基板之密合力,而製造出更高品質的印刷電路基 板。 【先前技術】 一般而吕’所謂印刷電路基板(PCB),係指待裝載電 氣元件(積體電路、電阻、開關等)之薄板,亦即絕緣體之 環氧或聚酸亞胺樹脂製之基板上貼合銅箔後,在必須殘留 銅箔之電路配線上印刷抗蝕劑,用能溶解銅的蝕刻液處理 基板來蝕去未印刷抗蝕劑的部分,之後除去抗蝕劑以殘留 所期望之銅箔配線而製造出印刷電路基板,然後再在必要 部位組裝元件。 這種印刷電路基板,依各種電子機器、電子通訊機器、 行動電話、筆記型電腦等不同用途而形成各種形態,且具 有各種製造方式。 例如,有別於一般之將鋼表面蝕刻來形成電路圖案的 方式,最近發展出SAP製程,係在銅表面上貼合DFR(乾 膜光阻)’將其曝光顯影而製作出圖案壁後,在圖案壁間實 施鍍銅而形成電路,接著在除去DFR構成之圖案壁的狀態 6 200806125 下,將表面全體蝕刻掉基板銅厚度,而僅在表面殘留銅電 然而,這種SAP製程方式,在DFR積層於銅表面之 作業時,須增大其與表面之密合力,以在製作出微細的融 膜後確保DFR圖案的密合力。又,DFR(乾膜)經曝光顯影 而製作出DFR圖案壁後,如圖丨所示般會殘留長線形態2 殘渣而使不良率變高,當在DFR圖案壁間進行鍍鋼時,因 圖案間之異物等會阻礙鍍敷之物質、或因DFR圖案材本身 之疏水性等,而產生一部分鍍銅的密合性變差之問題。 【發明内容】 本發明係掌握上述習知技術之問題點而為了加以解決 所提出者,其目的係提供一印刷電路基板製造用psAp方 法,係在經由SAP製程來製造印刷電路基板時,在進行主 要製程前,利用真空或大氣壓電漿處理來改質基板表面, 藉此將製程中產生之異物(scum)完全除去,並提高積層作 業時之DFR密合性及DFR圖案壁之密合力,如此可減少 後續步驟之鍍銅時不良的產生,在鍍銅後之DFR除去最終 步驟(鋼蝕刻)時也能謀求均一且平穩的銅蝕刻,而製作出 南品質的印刷電路基板。 為了解決前述技術課題,本發明之印刷電路基板製造 用PSAP方法,其特徵在於,在印刷電路基板製造用之sAp 製程包含以下階段:第丨電漿處理階段,係用包含銅之高 V電性膜塗布或模鑄於PI或絕緣基板之兩表面或一面,在 .亥面積層DFR之前,先對該面施以電漿處理以除去微細的 7 200806125 異物並進行表面改質而提昇DFR之密合力;第2電漿處理 階段,係在第1電漿處理階段後形成DFR圖案,將該圖案 與圖案壁間之表面施以電漿處理以進行去異物及表面改 質;第3電漿處理階段,係將DFR圖案再度用電漿施以均 質蝕刻以減小線寬並擴大DFR圖案間隔後,在電漿處理後 之圖案壁間貫施鍍銅以形成電路,經由第丨蝕刻而在基板 上僅殘留銅後除去圖案壁,將露出之基板表面及鍍銅面施 以電漿處理以進行表面改質;以及第2蝕刻階段,係將電 漿處理後之基板施以最終蝕刻以完成電路。 較佳為,在前述第1、2、3電漿處理階段,電漿產生 為產生電渡之條件為··輸出功率·· UOkw,頻率: 1KHZ〜2_54GHZ之高頻,電壓:真空電漿時為30〜1000V、 大氣壓電漿時為5Kv〜20Kv,環境氣體:選自空氣、02、N2、 CF4、Ar、Η2、NF3所構成群中之一種或二種以上的組合, 處理時間:1〜60分鐘,處理溫度:3〇〜1〇〇c>c。 本發明在印刷電路基板製造用之SAP製程中之必要處 k力屯水步驟來進# PSAp製程,能將藥品步驟所不易除 去之微細異物、殘料除去並進行表面改“謀求均質的 銅钱刻,因此能迅速地製作出高品質的印刷電路基板,並 將製程不良減至最小,而獲得優異的效果。 【實施方式】 以下,$ 所附圖式詳細說明本發明 < 較佳實施例。 圖2係顯示本發明之PSAP方法之步驟圖。200806125 IX. Description of the Invention: [Technical Field] The present invention relates to a PSAP (Plasma Semi Additive Process) method for manufacturing a printed circuit board, and more particularly to a printed circuit board manufacturing When the SAP (semi-additive process) process for manufacturing a printed circuit board is used in the PSAP method, the plasma is used for cleaning, etching, and surface modification to improve the adhesion between the fine circuit pattern and the base substrate. A higher-quality printed circuit board is manufactured. [Prior Art] Generally, the so-called printed circuit board (PCB) refers to a thin plate to be loaded with electrical components (integrated circuits, resistors, switches, etc.), that is, an insulator. After bonding a copper foil to a substrate made of an epoxy resin or a polyimide resin, a resist is printed on a circuit wiring in which a copper foil is left, and the substrate is treated with an etching solution capable of dissolving copper to etch away the unprinted resist. In part, the resist is removed to make a desired copper foil wiring to produce a printed circuit board, and then the components are assembled at necessary locations. The substrate is formed into various forms according to various electronic devices, electronic communication devices, mobile phones, notebook computers, and the like, and has various manufacturing methods. For example, it is different from the general method of etching a steel surface to form a circuit pattern. Developed the SAP process by attaching DFR (dry film photoresist) to the copper surface to expose the film to form a pattern wall, then performing copper plating between the pattern walls to form a circuit, and then removing the pattern wall formed by DFR. State 6 200806125, the surface of the entire surface is etched away from the thickness of the substrate copper, and only the surface of the copper remains. However, this SAP process, in the DFR layering on the copper surface, must increase its adhesion to the surface, After the fine melt film is produced, the adhesion force of the DFR pattern is ensured. Further, after the DFR (dry film) is formed by exposure and development to form a DFR pattern wall, the long-line form 2 residue remains as shown in FIG. When the steel is plated between the walls of the DFR pattern, a part of the plating is caused by the foreign matter between the patterns, which hinders the plating, or the hydrophobicity of the DFR pattern itself. The present invention provides a psAp method for manufacturing a printed circuit board, which is based on the problem of the above-mentioned prior art, and aims to solve the problem. When manufacturing a printed circuit board, the surface of the substrate is modified by vacuum or atmospheric piezoelectric slurry treatment before the main process, thereby completely removing the foreign matter (scum) generated in the process, and improving the DFR adhesion during the lamination operation. The adhesion between the SFR and the DFR pattern wall can reduce the occurrence of defects in the subsequent steps of copper plating. In the final step of the DFR removal after copper plating (steel etching), a uniform and smooth copper etching can be achieved. Quality printed circuit board. In order to solve the above-described problems, the PSAP method for manufacturing a printed circuit board according to the present invention is characterized in that the sAp process for manufacturing a printed circuit board includes the following stage: the second plasma processing stage uses a high V electrical property including copper. The film is coated or molded on both surfaces or one side of the PI or the insulating substrate. Before the DFR layer, the surface is first subjected to a plasma treatment to remove the fine 7 200806125 foreign matter and the surface is modified to enhance the DFR density. In the second plasma treatment stage, a DFR pattern is formed after the first plasma treatment stage, and the surface between the pattern and the pattern wall is subjected to plasma treatment for foreign matter removal and surface modification; third plasma treatment In the stage, after the DFR pattern is again subjected to homogenization etching by plasma to reduce the line width and enlarge the DFR pattern interval, copper plating is applied between the pattern walls after the plasma treatment to form a circuit, and the substrate is formed through the second etching. After removing copper, only the pattern wall is removed, the exposed substrate surface and the copper plating surface are subjected to plasma treatment for surface modification; and in the second etching stage, the plasma-treated substrate is subjected to final etching. To complete the circuit. Preferably, in the first, second, and third plasma processing stages, the plasma is generated to generate electric power as: · output power · UOkw, frequency: 1KHZ~2_54GHZ high frequency, voltage: vacuum plasma It is 30~1000V, 5Kv~20Kv in atmospheric piezoelectric slurry, and the ambient gas is one or more combinations selected from the group consisting of air, 02, N2, CF4, Ar, Η2, and NF3. Processing time: 1~ 60 minutes, processing temperature: 3 〇 ~ 1 〇〇 c > c. According to the invention, in the SAP process for manufacturing a printed circuit board, the k-force water-repellent step is carried out in the #PSAp process, and the fine foreign matter and the residual material which are difficult to remove in the pharmaceutical step can be removed and the surface is changed to "seek a homogeneous copper coin." Therefore, it is possible to quickly produce a high-quality printed circuit board, and to minimize the process defects, and to obtain an excellent effect. [Embodiment] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. Figure 2 is a diagram showing the steps of the PSAP method of the present invention.

.如圖2所不,本發明之印刷電路基板製造用之PSAP 8 200806125 製程大致分成:底基板準備階段(S100),第1電漿處理階 段(S110),光阻形成階段(S120),圖案形成階段(S130),第 2電漿處理階段(S14〇),電路形成階段(sl5〇),第1蝕刻階 段(S160)’第3電漿處理階段(S170),第2蝕刻階段(sl8〇)。 在底基板準備階段(S100),係使用兩面貼合有銅箔之 積層板(CCL)(l〇)當作底基板。 前述積層板(10),係在聚醯亞胺(PI)等聚合物或其他絕 緣材質所製成之基板(12)兩表面加上銅箔(14)而構成。 這時’前述基板(12)視需要也能使用環氧樹脂、玻璃 等材質。 只要如此般準備完成底基板,即可完成第i電漿處理 階段(S100)。 第1電漿處理階段(S110),係利用真空或大氣壓電漿 產生器所產生之電漿,來對位於積層板(10)兩表面之銅箔 (14)表面實施洗淨及表面改質。As shown in Fig. 2, the PSAP 8 200806125 process for manufacturing a printed circuit board of the present invention is roughly divided into a base substrate preparation stage (S100), a first plasma processing stage (S110), a photoresist formation stage (S120), and a pattern. Forming stage (S130), second plasma processing stage (S14〇), circuit forming stage (sl5〇), first etching stage (S160) 'third plasma processing stage (S170), second etching stage (sl8〇) ). In the base substrate preparation stage (S100), a laminate (CCL) (1) on which copper foil is bonded on both sides is used as a base substrate. The laminate (10) is formed by adding a copper foil (14) to both surfaces of a substrate (12) made of a polymer such as polyimide or other insulating material. At this time, the substrate (12) may be made of a material such as epoxy resin or glass as needed. As long as the base substrate is prepared in this manner, the i-th plasma treatment stage (S100) can be completed. In the first plasma treatment stage (S110), the surface of the copper foil (14) on both surfaces of the laminated board (10) is cleaned and surface-modified by means of a plasma generated by a vacuum or an atmospheric piezoelectric slurry generator.

因此,在真空電漿的情形,係將數十個積層板(1〇)裝 入具有多數個收容槽(slot)之積層板匿(magazine rack)而進 行大量處理,it時所使用之電漿產生器,依電極配置形態 有垂直型、水平型,這兩種都能使用。 在此,進行大氣壓電漿處理時較佳為,在上部或下部 設置電衆產生模組,在該模組之電漿噴出部位面,以録 隔一定間隔的方式使待處理之表面通過而進行處理。/、/、 特別是,該電聚產生器較佳為,具備大約i〜遍(依 !次處理t PCB表面積而異)之電聚功率,使用頻率 9 200806125 IKHz〜2.54GHz之高頻;關於電壓,在使用真空電漿時為 3/〜1000V,在使用大氣壓電襞時為5Κν〜2_κν;關於環境 氣體,可依被處理物之材質而適當地選擇空氣、〇2、Ν、 CF4、Ar、H2、NF3等;關於處理時間,依異物量、2材質2表 面而有不肖’但一般以M0分鐘為佳,處理溫度也依被 處理物之材質而不同,但較佳為3〇〜1〇(rc之範圍。 將數值限定在前述範圍之理由在於,依被處理物材質 j不同可能會有多種變化,考慮到通用之pCB㈣時,在 前述處理範圍内能展現最大的處理效率,例如當輸出功率 用量超過5〇kw時,被處理物表面容易損傷而難以對電漿 強度做微細控制,當功率低於lkw以下時,輸出用量太小 而造成去異物&率大幅降⑯,因Λ較佳為控射上述範Therefore, in the case of vacuum plasma, a plurality of laminates (1 inch) are loaded into a magazine rack having a plurality of storage tanks for a large amount of processing, and the plasma used in it is used. The generator has a vertical type and a horizontal type depending on the electrode configuration, and both of them can be used. Here, in the case of performing the atmospheric piezoelectric slurry treatment, it is preferable to provide a power generation module in the upper portion or the lower portion, and to pass the surface to be treated by recording at a certain interval on the surface of the plasma discharge portion of the module. deal with. /, /, In particular, the electro-convergence generator preferably has an electropolymerization power of about i~pass (depending on the processing time of the PCB surface), and the frequency of use is high frequency of 2008-0625 IKHz~2.54GHz; The voltage is 3/~1000V when vacuum plasma is used, and 5Κν~2_κν when using atmospheric piezoelectric iridium. For ambient gas, air, 〇2, Ν, CF4, Ar can be appropriately selected depending on the material of the material to be treated. , H2, NF3, etc.; regarding the processing time, depending on the amount of foreign matter, 2 material 2 surface is not obvious 'but generally M0 minutes is better, the processing temperature is also different depending on the material of the processed material, but preferably 3〇~1 〇 (the range of rc. The reason for limiting the numerical value to the above range is that there may be various variations depending on the material j of the workpiece, and in consideration of the general pCB (four), the maximum processing efficiency can be exhibited within the aforementioned processing range, for example, when When the output power consumption exceeds 5〇kw, the surface of the treated object is easily damaged and it is difficult to finely control the plasma strength. When the power is lower than lkw, the output amount is too small, and the foreign matter & rate is greatly reduced. Better control Said Fan

關於頻率範圍,在1ΚΗζ以上之低頻時,在數微米(〆 以下之微細孔與圖案間等難以形成均等的電漿分布,在 2.54GHz w上之高頻時,由於電漿能量太大而難以控制, 口此較佺為限定在上述範圍。關於施加電壓,在真空時, 於画V以上的情形,受到自由基/離子之強力的表… ♦,被f理物會發生濺蝕或熱損傷(Heat Damage),於3〇 乂下的h形,由於無法有效地提昇自由基/離子之移動速^ (Impact)故較佳為限定在上述範圍;在大氣壓時,為了 /成電水放電,必須使電子或氣體這麼大的阻抗體離子 七必肩具有相當尚的瞬間電子衝擊能量,故最少為 數百V以上,在商用的情形以5KV以上效率較佳,但超 200806125 過20KV時,難以控制電漿能量,容易發生電弧而難以維 持安定的電漿,因此較佳為限定在前述範圍。關於環境氣 體,在進行表面改質及去異物時以氧、氮、氬、氫等為佳, 在進行表面蝕刻時以CL、Αγ、Η" NF3等為佳,在進行 凹凸、親水化、疏水化等之表面改質時,以氧、CP#、Ar、 H2等為佳。 在進行表面親水化時,可單獨使用氧、氬、氫或空氣, 或將氬與氫混合使用,或將氬、氧、氮混合使用。在進行 表面疏水化時,可單獨使用CF4、ΝΙ?3,或將其等混合使用。 依被處理物之處理形態或材質,可單獨使用上述氣體或將 '一種以上混合使用。 β 進行第1電漿處理階段(S110)之理由在於,提高鋼箔(14) 之表面能以使積層時乾膜光阻之密合力極大化,藉此能使 DFR圖案製程之不良減至最小。 經由上述過程將積層板(10)表面施以改質後,接下來 進行光阻形成階段(S 120)。 光阻形成階段(S 120)較佳為積層乾膜形態之光 阻。 .光阻膜除DFR(20)外,也能使用具有相同功能之墨水 及糊劑。 當完成光阻膜之積層後,即可進行圖案形成階段 (S130) 〇 士圖案形成階段(S130),係使用既定光罩將乾膜(2〇)之 特定部分施以曝光、顯影而製作出圖案壁(30)。 200806125 這時,在圖案壁(30)形成過程中之曝光顯影時,在圖 案壁(30)間會發生微細異物(seum)(32)。 ° 這種異物(32)會引發後續步驟之不良,因此必須將其 除去,以往僅經由濕式洗淨處理來除去,因此無法達到完 全除去,且可能會殘留濕式洗淨處理步驟之微細殘留物。70 本發明在前述圖案形成階段(sl3〇)後,以和第丨電漿 處理階段(S110)類似的條件實施第2電漿處理階段(si4〇)水 利用電漿之自由基反應將異物(32)完全除去而實施去 作業。 ” 在此過程,藉由第2電聚處理所實施之去異物作業, 能將圖案壁(30)間之表面(底面)施以親水化改質,俾平穩且 容易地進行後步驟之鍍銅(無孔洞產生)。 “ 當第2電漿處理階段(_)完成即進行電路形成階段 (⑽在形成電路前較佳為,使用電漿敍刻將舰圖案 再度均質化處理’以減小線寬並擴大DFR圖案間隔,藉此, =接下來進行㈣銅時,在同樣面積内能儘量加大鑛銅範 圍,因此能確保銅圖案之完整性。 〜2電漿處理階段(⑴〇) 二 物而親水化後之圖案壁(3°)間,為了形成電通路 而填滿銅,亦即屬於一種鍍銅(40)過程。 換σ之’鑛敷於圖案壁 銅電路係依昭設叶0牵夹开^ )之銅史成鋼電路,這種 士人^ / 案心成’經由最終钱刻步驟就成為 來形成。 锻U 〇)了才木用化學鑛或電鑛等方法 12 200806125 經由鍍鋼(40)來形成電路後,接著進行第i钱刻階^ =第丨㈣階段(叫係利用藥品或電讓,將圖又 案土(3〇)、亦即DFR(20)等材質之圖案壁除去。 當除去DFR(20)圖案後, 發揮電路之特徵,必須將全體 確保銅電路部位之絕緣性,因 的厚度。 基板底的鋼部位露出,為了 除去基板底銅部位的厚度以 此必須基板全體蝕刻掉底銅 Φ 然、而’當這時的餘刻不均一時會發生不良而造成製品 品質降低,並導致PCB動作特性變差,因此要求更均一且 正確的蝕刻。因此’本發明在第1蝕刻階段⑻的)後,藉 土實施第3電漿處理階段(S170)來謀求均一的蝕刻。前‘ 第3電漿處理階段(sl7〇),較佳為以和第i2電漿處理階 段(S 110、S 140)類似的條件來進行。 、’、由弟3電漿處理’構成電路之銅表面被改質,各部 之表面此以相同比例提咼而被施以親水化,在以相同藥 φ 進行餘刻的過程,在相同蝕刻條件下,相較於未經電漿 處理的炀形,電漿處理的結果銅部位(包括底、圖案)的蝕 刻能以2倍厚度且均質地進行。 如此般在第3電漿處理階段(sl7〇)後經由第2蝕刻階 & (S 1 80)進行最終蝕刻而將所有部位的底銅厚均蝕刻掉 後’即形成最終之PCB用電路。 如此般’本發明在印刷電路基板製造用之一般的SAP W程中’於光阻形成前、電路形成前、最終蝕刻前,均透 過電聚處理之物理反應與自由基反應而將存在於基板上之 13 200806125 並將表面改質、提高表面能來進Regarding the frequency range, at a low frequency of 1 ΚΗζ or more, it is difficult to form an equal plasma distribution between micropores and patterns below 〆, and at a high frequency of 2.54 GHz w, it is difficult because the plasma energy is too large. Control, the mouth is more limited to the above range. Regarding the application of voltage, in the case of vacuum, in the case of drawing V or more, subject to the strength of free radicals / ions... ♦, the material will be splashed or thermally damaged (Heat Damage), the h-shape at 3〇乂 is preferably limited to the above range because it cannot effectively increase the free radical/ion moving speed (Impact); at atmospheric pressure, in order to/for electric water discharge, It is necessary to make the electron or gas such a large amount of impedance ions have a considerable instantaneous electron impact energy, so it is at least several hundred V or more. In commercial cases, the efficiency is better than 5KV, but when the temperature is over 20080125, it is difficult. It is preferable to control the plasma energy, and it is easy to generate an arc, and it is difficult to maintain a stable plasma. Therefore, it is preferable to limit the range to the ambient gas, such as oxygen, nitrogen, argon, hydrogen, etc. when performing surface modification and foreign matter removal. Preferably, CL, Αγ, Η" NF3 or the like is preferably used for surface etching, and when surface modification such as unevenness, hydrophilization, or hydrophobization is performed, oxygen, CP#, Ar, H2, or the like is preferably used. When the surface is hydrophilized, oxygen, argon, hydrogen or air may be used alone, or argon may be mixed with hydrogen, or argon, oxygen, and nitrogen may be used in combination. When surface hydrophobization is performed, CF4 and ΝΙ?3 may be used alone. Depending on the treatment form or material of the material to be treated, the above gas may be used alone or in combination of one or more types. The reason for performing the first plasma treatment stage (S110) is to increase the steel foil (14). The surface energy can maximize the adhesion of the dry film photoresist during lamination, thereby minimizing the defects of the DFR pattern process. After the surface of the laminate (10) is modified by the above process, the next step is performed. Photoresist formation stage (S 120). The photoresist formation stage (S 120) is preferably a photoresist of a laminated dry film form. The photoresist film can also use inks and pastes having the same function in addition to DFR (20). When the laminate of the photoresist film is completed, the image can be drawn. Forming stage (S130) In the gentleman pattern forming stage (S130), a specific portion of the dry film (2 turns) is exposed and developed using a predetermined mask to form a pattern wall (30). 30) During exposure and development during formation, a fine foreign matter (32) occurs between the pattern walls (30). ° This foreign matter (32) causes a defect in the subsequent steps, so it must be removed. It is removed by the wet cleaning treatment, so that complete removal cannot be achieved, and the fine residue of the wet cleaning treatment step may remain. 70 The present invention is after the aforementioned pattern forming stage (sl3〇), and the third plasma In the treatment stage (S110), the second plasma treatment stage (si4〇) is carried out under the similar conditions, and the foreign matter (32) is completely removed by the radical reaction of the plasma to carry out the work. In this process, the surface (bottom surface) between the pattern walls (30) can be hydrophilized by the foreign matter operation performed by the second electropolymerization treatment, and the copper plating in the subsequent step can be smoothly and easily performed. (No hole is generated.) "When the second plasma processing stage (_) is completed, the circuit formation stage is performed ((10) It is preferable to use plasma to re-homogenize the ship pattern before forming the circuit to reduce the line. Wide and widened the DFR pattern spacing, whereby = when the (four) copper is carried out, the copper content can be increased as much as possible within the same area, thus ensuring the integrity of the copper pattern. ~ 2 plasma processing stage ((1) 〇) II Between the pattern wall (3°) after hydrophilization, the copper is filled in order to form an electrical path, which is a process of copper plating (40). The sigma is applied to the copper circuit of the pattern wall. 0 pulls the open ^) of the copper Shicheng steel circuit, this kind of scholar ^ / case heart into 'through the final money engraving step to become formed. Forging U 〇) The method of using chemical or electric ore in Caimu 12 200806125 After forming the circuit by plating steel (40), then proceeding to the stage of the second stage ^=第丨(四) (called using drugs or electricity, The pattern wall of the material such as the soil (3〇), that is, DFR (20) is removed. When the DFR (20) pattern is removed, the characteristics of the circuit are used, and the insulation of the copper circuit portion must be ensured as a whole. The thickness of the steel portion at the bottom of the substrate is exposed. In order to remove the thickness of the copper portion at the bottom of the substrate, it is necessary to etch the bottom copper Φ from the entire substrate. However, when the remaining time is not uniform, defects may occur and the quality of the product may be lowered. Since the PCB operating characteristics are deteriorated, a more uniform and correct etching is required. Therefore, after the present invention is subjected to the third plasma processing stage (S170) after the first etching step (8), uniform etching is performed. The first 'third plasma processing stage (sl7) is preferably carried out under conditions similar to those of the i2th plasma processing stage (S110, S140). ', the treatment of the plasma of the brother 3' is the modification of the copper surface of the circuit, and the surface of each part is hydrophilized by the same ratio, and the same etching condition is used in the process of the same medicine φ. Under the plasma treatment, the etching of the copper portion (including the bottom and the pattern) can be performed in a thickness of 2 times and homogeneously compared to the shape of the plasma which is not treated by the plasma. After the third plasma processing stage (sl7〇), the final etching is performed through the second etching step & (S 180), and the copper thickness of all portions is etched away, thereby forming the final PCB circuit. Thus, the present invention is present in the substrate in the general SAP W process for manufacturing a printed circuit board, before the formation of the photoresist, before the formation of the circuit, and before the final etching, by the physical reaction and the radical reaction of the electropolymerization process. 13 of 200806125 and improve the surface and improve the surface energy

2倍。 異物、殘渣等完全除去, 行PSAP製程,藉由提高 【圖式簡單說明】 SAP製程中在乾膜曝光時產生2 times. The foreign matter, residue, etc. are completely removed, and the PSAP process is performed, which is improved by the simple process of the SAP process.

圖1係顯不習知技術之SAP φ 的殘渣之照片。 圖2係顯示本發明的PSAP方法之步驟圖 【主要元件符號說明】 10···積層板(CCL) 12···基板(絕緣板) 14···銅箔 20··· DFR(乾膜光阻) 30···圖案壁 φ 32···異物 40···鍍銅Figure 1 is a photograph showing the residue of SAP φ of a conventional technique. 2 is a view showing the steps of the PSAP method of the present invention [Description of main components] 10···Laminated board (CCL) 12···substrate (insulation board) 14···copper foil 20··· DFR (dry film) Photoresist) 30···pattern wall φ 32···foreign matter 40···copper plating

Claims (1)

200806125 十、申請專利範園: .· 1、—種印刷電路基板製造用電漿半加成方法,係在印 刷电,基板製造用之半加成製程(SAp)包含以下階段: 弟1電漿處理階段’係用包含銅之高導電性膜塗布或 =於絕緣基板之兩表面或—面,在該面積層啊乾 、光阻)之刖’先對該面施以電漿處理以除去微細的異物並 進行表面改質而提昇DFR之密合力; 第2電漿處理階段’係在第1電漿處理階段後形成跳 圖案’將該圖案與圖案壁間之表面施以電衆處理以進行去 異物及表面改質; 所第電水處理階段,係將DFR圖案再度用電漿施以均 貝#心減小線寬並擴大DFR圖案間隔後,在電裝處理後 之圖案壁間實施錢銅以形成電路,經由第1餘刻而在基板 上僅殘留銅後除去圖案壁,將露出之基板表面及鍍銅面施 以電漿處理以進行表面改質;以及 第2蝕刻階段,係將電漿處理後之基板施以最終蝕刻 以完成電路。 、士申叫專利範圍第1項之印刷電路基板製造用電漿 ^法其中,在該第1、2、3電漿處理階段,電漿 的產生電聚之條件為:輸出功率:1〜50kw,頻率: 产54GHZ之兩頻’電壓:真空電漿時為30〜1000V、 二氣壓電漿時為5Kv〜2〇Kv’環境氣體:選自空氣、%,、 4 Ar HrNF3所構成群中之一種或二種以上的組合, 處理時間…60分鐘,處理溫度:3〇〜贿。 15200806125 X. Application for patent garden: .. 1. A semi-additive method for plasma production of printed circuit boards, which is printed in electricity. The semi-additive process (SAp) for substrate manufacturing includes the following stages: The treatment stage is coated with a high-conductivity film containing copper or = on both surfaces or surfaces of the insulating substrate, after the surface layer is dried, and the photoresist is first applied to the surface to remove fine particles. The foreign matter is subjected to surface modification to enhance the adhesion of the DFR; the second plasma treatment stage 'forms a jump pattern after the first plasma treatment stage', and the surface between the pattern and the pattern wall is subjected to electricity treatment for performing To the foreign matter and the surface modification; in the electro-hydraulic treatment stage, the DFR pattern is again applied with the plasma by the plasma. The heart is reduced by the line width and the DFR pattern interval is enlarged, and the money is applied between the pattern walls after the electric decoration. Copper forms a circuit, and only the copper remains on the substrate after the first residue, and the pattern wall is removed, and the exposed substrate surface and the copper plating surface are subjected to plasma treatment for surface modification; and the second etching step is performed. Plasma treated substrate The final etch is done to complete the circuit. In the first, second and third plasma processing stages, the conditions for the plasma generation of the plasma are: output power: 1~50kw. , Frequency: Two frequencies of 54 GHZ 'voltage: 30~1000V for vacuum plasma, 5Kv~2〇Kv' for two-pressure plasma: ambient gas: selected from the group consisting of air, %, and 4 Ar HrNF3 One or more combinations, processing time...60 minutes, processing temperature: 3〇~ bribe. 15
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