200805566 九、發明說明： 【日月 3 發明領域 本發明的實施例是有關於半導體裝置，更特別地，是 5有關於功率金屬氧化物半導體場效電晶體(功率MOSFET)。 發明背景200805566 IX. Description of the Invention: [Sunday 3] Field of the Invention Embodiments of the present invention relate to semiconductor devices, and more particularly, to power metal oxide semiconductor field effect transistors (power MOSFETs). Background of the invention
光刻法是被普遍地使用來製作半導體裝置。在光刻法 中，一個來自一個光罩的圖案是被轉移到一個表面。光線 10是通過該光罩並且聚焦在該表面上。隨著半導體裝置的特 徵越來越小，較佳的聚焦變得更重要。 【發明内容；3 發明概要 方便使用光刻法來製作具有微小特徵之半導體裝置的 方法及/或系統會是有利的。本發明的實施例提供這樣和其 他的優點。 a 在-個實施例中，-種結構最好是包括—個形成於— 個基體中的半導體裝置；一個與該半導體裝置相鄰的 體；一個電氣地連接到該半導體裝置的電氣接％ 、 2。==好是_;及—個連接到該電氣接點的電 連接|§，其中，該電連接器最好是包括鋁。 电 在-個實施例中，該絕緣體的表面與該電 面最好是形成-個實質平坦表面。該實質平/接點的表 光刻法期間的聚焦，因此尺寸較小的徵=表面改進在 形成在該表 5 200805566 [ 面上。 • 被描繪在不同之圖式中之本發明之這些和其他希望之 目的以及料想的優點將會由熟知此項技術的人仕在閱讀後 面的詳細說明之後被確認。 5圖式簡單說明 ‘ 該等附圖，其是被併合在說明書中且形成說明書的一 ' 部份，描繪本發明的實施例而且，與該描述一起，作用來 % 說明本發明的原理··、 第1圖是為一個顯示本發明之一個實施例之結構之選 10擇層的剖視圖。 第2圖是為本發明之一個實施例之第1圖之結構之製造 中所使用之製程的流程圖。 第3、4和5圖是為顯示本發明之一個實施例之第1圖之 結構之製造中之選擇階段的剖視圖。 15 第6圖是為本發明之一個實施例之第1圖之結構之一個 • 部份的由上而下圖示。 第7圖是為一個顯示本發明之另一個實施例之結構之 - 選擇層的剖視圖。 C實施方式] 20較佳實施例之詳細說明 在本發明的後面詳細插述中，很多特定細節是被陳述 俾可提供本發明的貫徹了解。然而，會由熟知此項技術的 人仕所確認的是，本發明在沒有這些特定細節或者其之等 效物之下能夠被實施。在其他例子中，眾所周知的方法、 6 200805566 气 ί 5 程序、組件、和電路為免混淆本發明的特徵而未被詳細描 述。 後面之詳細說明的一些部份是依據用於製造半導體裝 置之運作的程序、邏輯方塊、工序、及其他符號表徵來被 呈現。這些描述和表徵是為由熟知半導體裝置製造之人仕 最有效率地把它們之工作的本質傳達給其他熟知此項技術 之人仕所使用的工具。在本申請案中，一個程序、邏輯方 塊、工序、或其類似是被想像為導致希望之結果之步驟或 者指示的有條理順序。該等步驟是為要求物理量之物理運 10 用。然而，應要謹記的是，所有這些以及類似的詞語是要 與適當的物理量結合在一起而且僅是為施加到這些量的合 宜符號。除非特別敘述否則從後面的討論顯而易見，本申 請案從頭到尾，利用像是”形成”、”執行”、”產生”、”沉積”、” 蝕刻”或其類似般之詞語的討論是指半導體裝置製造的動 15 作和工序(例如，第2圖的工序200)。 要了解的是，該等圖式不是依據比例來繪製，而且僅 被描述之該等結構的部份，以及形成那些結構之不同的 層，是被顯示。為了討論和描繪的簡潔，雖然實際上數個 電晶體會被形成，該工序是就一個單一電晶體來描述。 ， 20 再者，要察覺的是，其他的製造工序和步驟可以與在 此中所討論的工序和步驟一起被執行；即，於在此中所顯 示與描述的步驟之前和之後可以有若干製程步驟。重要 地，本發明的實施例能夠在沒有明顯地擾亂這些其他（習知) 工序和步驟之下結合它們一起來被實施。一般而言，本發 7 200805566 明的不同實施例能夠在沒有明顯地影響週邊的工序與步雜 之下置換一個習知工序的部份。 第1圖是為一個顯示本發明之一個實施例之一個結構 10之選擇層的剖視圖。如上所述，除了被描繪與描述的那 5 些之外，結構1〇可以包括其他裝置、元件及層。 在第1圖的例子中，兩個裝置14和16是形成在基體 之内。在一個實施例中，基體12是為石夕基體。Photolithography is commonly used to fabricate semiconductor devices. In photolithography, a pattern from a reticle is transferred to a surface. Light 10 is passed through the reticle and focused on the surface. As semiconductor devices become smaller and smaller, better focusing becomes more important. SUMMARY OF THE INVENTION 3 SUMMARY OF THE INVENTION It would be advantageous to facilitate the use of photolithography to fabricate methods and/or systems of semiconductor devices having minute features. Embodiments of the present invention provide such and other advantages. In one embodiment, the structure preferably includes a semiconductor device formed in the substrate; a body adjacent to the semiconductor device; and an electrical connection electrically connected to the semiconductor device, 2. ==Good is _; and - an electrical connection to the electrical contact | §, wherein the electrical connector preferably comprises aluminum. In one embodiment, the surface of the insulator and the surface preferably form a substantially planar surface. The substantial flat/contact table is focused during photolithography, so the smaller size of the sign = surface improvement is formed on the surface of the table 5 200805566. These and other desirable objects and advantages of the present invention, which are described in the various figures, will be recognized by those skilled in the art after reading the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS The drawings, which are incorporated in and constitute a part of the specification, depict embodiments of the present invention and, together with the description, serve to illustrate the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a selected layer of a structure showing an embodiment of the present invention. Fig. 2 is a flow chart showing the process used in the manufacture of the structure of Fig. 1 according to an embodiment of the present invention. Figures 3, 4 and 5 are cross-sectional views showing selected stages in the manufacture of the structure of Figure 1 of one embodiment of the present invention. 15 Fig. 6 is a top down view of a portion of the structure of Fig. 1 of an embodiment of the present invention. Figure 7 is a cross-sectional view of a selective layer showing the structure of another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following detailed description of the invention, numerous specific details are set forth to provide a description of the invention. However, it will be recognized by those skilled in the art that the present invention can be practiced without these specific details or equivalents thereof. In other instances, well-known methods, components, components, and circuits have not been described in detail to avoid obscuring the features of the present invention. Portions of the detailed description that follows are presented in terms of procedures, logic blocks, procedures, and other symbolic representations used to fabricate the operation of the semiconductor device. These descriptions and characterizations are used by those skilled in the art of semiconductor devices to most effectively convey the essence of their work to those skilled in the art. In the present application, a program, a logical block, an operation, or the like is a logical order that is conceived to be the step or indication of the result of the desired. These steps are for the physical operation of physical quantities. However, it should be borne in mind that all of these and similar words are intended to be combined with the appropriate physical quantities and are merely intended to be Unless otherwise stated, it will be apparent from the discussion that follows that the discussion of the words "forming," "executing," "generating," "depositing," "etching," or the like, refers to semiconductors from beginning to end. The operation and manufacture of the device (for example, the process 200 in Fig. 2). It is to be understood that the drawings are not drawn to scale, and that only the portions of the structures that are described, and the layers that form those structures, are shown. For the sake of simplicity of discussion and depiction, although in practice a number of transistors will be formed, the process is described in terms of a single transistor. Further, it will be appreciated that other manufacturing processes and steps may be performed with the processes and steps discussed herein; that is, there may be several processes before and after the steps shown and described herein. step. Importantly, embodiments of the invention can be practiced without a significant disruption of these other (common) processes and steps. In general, the different embodiments of the present invention can replace a portion of a conventional process without significantly affecting the surrounding processes and steps. Figure 1 is a cross-sectional view of a selected layer showing a structure 10 of one embodiment of the present invention. As noted above, the structure 1 can include other devices, components, and layers in addition to those depicted and described. In the example of Fig. 1, the two devices 14 and 16 are formed within the substrate. In one embodiment, the substrate 12 is a stone substrate.
一般而s ’裝置14和16是為互補式金屬氧化物半導體 (CMOS)裝置。更特別地，在一個實施例中，裝置14及/或16 10是為功率金屬氧化物半導體場效電晶體(功率MOSFET)。夢 置14和16的細卽未被描繪或描述。像功率mosfet般的筆 置是眾所周知的，而且本發明的實施例能夠適應不同類型 的功率M0SFET。在一個實施例中，裝置14及/或16是為溝 渠式功率MOSFET。 在第1圖的例子中，一個接點22是位於裝置14與裝置16 之間，因此這些裝置能夠彼此電氣接觸或者與其他裝置電 氣接觸。連鮮24接著是與祕22電氣接觸。軸本發明 並未如此限制，在-個實關巾，接點22是由賴成，而 連接器24是由鋁構成。 20 絕緣體18和20是分別相鄰於裝置。雖然本發明 並未如此限制，絕㈣18㈣可以由二氧切或者棚磷石夕 玻璃(BPSG)構成。雖然該料置14和16中之任—者或兩者 疋毛氣連制接點22 ’絕緣體18和2()作絲隔離該等裝置 14和16。換句話說，是有_個從裝置财/或從裝置關接 8 200805566 點22的特定導電路徑。 藉著在第1圖中所示的結構1〇,接點22的上表面是與該 前金屬介電(PMD)表面26實質上同一水平。該接點22與絕 緣體18和20的上表面形成一個實質平坦表面。從下面的討 5論將會見到，由接點22和絕緣體18和20形成的實質平坦表 面幫助較小尺寸特徵的製作，特別是像是接點22和連接器 24般的較小尺寸元件。 第2圖是為在本發明之一個實施例之第1圖之結構1〇之 製造中所使用之工序的流程圖200。雖然特定的步驟是在第 10 2圖揭露’該專步驟是為範例。即，本發明是適合於執行在 弟2圖中所述之步驟的變化或者不同的其他步驟。第2圖是 配合第3、4和5圖作討論，第3、4和5圖是為顯示在本發明 之一個實施例之第1圖之結構1〇之製作中之選擇階段的剖 視圖。 15 在第2圖的方塊2〇1中，且亦配合第3圖所示，一個包括 裝置14的結構是被製造，或者一個如此製成的結構是被得 到。在一個實施例中，一個第一障壁層3〇是被沉積在絕緣 體18和20之上以及在絕緣體18與20之間之基體12的區域之 上。在絕緣體18與20之間的區域是為該接點區域，第丨圖的 2〇 接點22將會被形成在該接點區域中。在一個實施例中，該 第一障壁層30是由氮化鈦(TiN)構成。 在第2圖的方塊202中，且亦配合第3圖所示，一個第一 金屬化層32是沉積在該第一障壁層3〇之上，包括在絕緣體 18和20之上的區域以及在絕緣體18與2〇之間的接點區域。 9 200805566 i 在一個實施例中，該第一金屬化層32包括鎢。另一種材料， • 像是銅般，可以替代使用。在一個實施例中，該第一金屬 化層32是利用化學蒸氣沉積法(cvd)來沉積。 在第2圖的方塊203中，且亦配合第4圖所示，在一個實 5施例中，該第一金屬化層32是被蝕刻（平面蝕刻）到第i圖的 - PMD表面26。換句話說，該第一金屬化層32是被後蝕刻到 • 該第一障壁層30，因此該第一金屬化層32之餘下部份的上 ^ 表面是與絕緣體18和20的上表面實質上同一水平。因此， 一個實質平坦表面40 (相當於該PMD表面26)是形成遍佈該 1〇等絕緣體18和20以及在絕緣體18與20之間的接點區域。 如此形成的表面40是足夠平坦來改進在光刻法期間的 聚焦。即，如果一個表面是太過不平坦的話，該表面的部 伤會疋焦點對準的而該表面的其他部份會是焦距不準的。 然而，根據本發明的實施例，表面4〇是足夠平坦來允許該 15表面之關注的部份在光刻法期間維持焦點對準。藉由改進 φ 整個表面的聚焦，較小尺寸特徵(例如，第1圖的連接器24) 能夠被形成於該表面4〇上。 再者’該接點區域的寬度(在第4圖中以尺寸D表示)能 夠被縮減。縮減該接點區域的一個優點是為裝置(例如，第 20 1圖的裝置14和16)的密度能夠被增加。由於寬度D在尺寸上 縮減’像是|g般的材料可以不再充填該接點區域，俾可形 成一個適當的接點。根據本發明的實施例，第一金屬化層 32的CVD-在一個實施例中，鎢的CVI>是用來適當地充填 較小的接點區域，形成一個適當的接點22。在一個實施例 200805566 中，尺寸D是處於大約0·35-〇·50微米的範圍中。 在第2圖的方塊204中，且亦配合第5圖所示，在一個實 施例中，一個第二障壁層33是沉積於在先前之方塊2〇3中所 形成的表面之上。在一個實施例中，第二障壁層33是由鈦 5 構成。 在第2圖的方塊2〇5中，且亦配合第5圖所示，一個第二 金屬化層34是沉積在該第二障壁層33之上。在一個實施例 中’該弟》—金屬化層34包括崔呂。 在第2圖的方塊2〇6中，一個光罩是根據光刻法工序來 10被使用俾可把該第二金屬化層34定以圖案。該第二金屬化 層34是被蝕刻俾可形成第！圖的連接器24。 第6圖是為本發明之一個實施例之第丨圖之結構1〇的由 上而下圖示，顯示在方塊2〇6之蝕刻處理之後橫越若干接點 22的連接器24 (第2圖）。 15 第7圖是為一個顯示本發明之另一實施例之結構70之 選擇層的剖視圖。相對於第i圖之結構1〇的接點22，其可以 1倥個平面接點，第7圖的接點71延伸至基體12内而且可以 疋一個溝渠式接點。藉著在第7圖中所示的結構7〇，接點 延伸在基體12的上表面72下面。結構70的元件能夠利用第2 2〇 圖的工序200來形成。 總括而言，根據本發明的實施例，使用光刻法來製作 具有較小特徵的半導體裝置是合宜的。較小接點能夠藉由 沉積像是鎢的材料至較小接點區域來被形成。把最終結構 钱刻來形成一個實質平坦表面改進聚焦，允許縮減尺寸特 11 200805566 • 徵被形成於該表面上。 f . 本發明的實施例被如此描述。雖然本發明業已在特定 實施例中作說明，應要察覺的是，本發明不應受限於如此 的實施例，而是可以依據下面的申請專利範圍來被構築。 5 【圖式簡單說明】 ^ 第1圖是為一個顯示本發明之一個實施例之結構之選 擇層的剖視圖。 第2圖是為本發明之一個實施例之第1圖之結構之製造 中所使用之製程的流程圖。 10 第3、4和5圖是為顯示本發明之一個實施例之第1圖之 結構之製造中之選擇階段的剖視圖。 第6圖是為本發明之一個實施例之第1圖之結構之一個 部份的由上而下圖示。 第7圖是為一個顯示本發明之另一個實施例之結構之 15 選擇層的剖視圖。 ^ 【主要元件符號說明】 10 結構 24 連接器 12 基體 26 表面 14 裝置 30 第一障壁層 16 裝置 32 第一金屬化層 18 絕緣體 33 第二障壁層 20 絕緣體 34 第二金屬化層 22 接點 40 表面 12 200805566 70 結構 203 方塊 71 接點 204 方塊 72 上表面 205 方塊 200 工序 206 方塊 201 方塊 202 方塊Typically, s' devices 14 and 16 are complementary metal oxide semiconductor (CMOS) devices. More particularly, in one embodiment, device 14 and/or 16 10 is a power metal oxide semiconductor field effect transistor (power MOSFET). The details of Dreams 14 and 16 are not depicted or described. Pens like power mosfets are well known and embodiments of the present invention are capable of adapting to different types of power MOSFETs. In one embodiment, devices 14 and/or 16 are trench power MOSFETs. In the example of Fig. 1, a contact 22 is located between the device 14 and the device 16, so that the devices can be in electrical contact with each other or in electrical contact with other devices. Lian Xian 24 followed by electrical contact with Mi 22 . The present invention is not so limited. In the case of a solid closure, the joint 22 is made of Lai and the connector 24 is made of aluminum. 20 insulators 18 and 20 are adjacent to the device, respectively. Although the invention is not so limited, the absolute (four) 18 (four) may be composed of dioxo or shed phosphorite glass (BPSG). Although either of the materials 14 and 16 or both of the bristles 22' insulators 18 and 2() are used to isolate the devices 14 and 16. In other words, there is a specific conductive path for the slave device/or slave device 8 200805566 point 22. By the structure 1 shown in Fig. 1, the upper surface of the contact 22 is substantially at the same level as the front metal dielectric (PMD) surface 26. The contact 22 forms a substantially flat surface with the upper surfaces of the insulators 18 and 20. As will be seen from the discussion below, the substantially flat surface formed by the contacts 22 and the insulators 18 and 20 aids in the fabrication of smaller sized features, particularly smaller sized components such as contacts 22 and connectors 24. Fig. 2 is a flow chart 200 showing the steps used in the manufacture of the structure 1 of Fig. 1 of one embodiment of the present invention. Although the specific steps are disclosed in Figure 102, the specific steps are examples. That is, the present invention is a change or a different step suitable for performing the steps described in the Fig. 2 diagram. Fig. 2 is a view in conjunction with Figs. 3, 4 and 5, and Figs. 3, 4 and 5 are cross-sectional views showing a selection stage in the fabrication of the structure 1 of Fig. 1 of one embodiment of the present invention. 15 In block 2〇1 of Fig. 2, and also in conjunction with Fig. 3, a structure comprising device 14 is fabricated, or a structure so produced is obtained. In one embodiment, a first barrier layer 3 is deposited over the insulators 18 and 20 and over the region of the substrate 12 between the insulators 18 and 20. The area between the insulators 18 and 20 is the contact area, and the 2 接 contact 22 of the second figure will be formed in the contact area. In one embodiment, the first barrier layer 30 is comprised of titanium nitride (TiN). In block 202 of FIG. 2, and also in conjunction with FIG. 3, a first metallization layer 32 is deposited over the first barrier layer 3, including regions over insulators 18 and 20, and A contact area between the insulators 18 and 2〇. 9 200805566 i In one embodiment, the first metallization layer 32 comprises tungsten. Another material, • like copper, can be used instead. In one embodiment, the first metallization layer 32 is deposited using chemical vapor deposition (cvd). In block 203 of Fig. 2, and also in conjunction with Fig. 4, in a practical embodiment, the first metallization layer 32 is etched (planar etched) to the - PMD surface 26 of the ith diagram. In other words, the first metallization layer 32 is etched back to the first barrier layer 30, so that the upper surface of the remaining portion of the first metallization layer 32 is substantially opposite to the upper surface of the insulators 18 and 20. On the same level. Thus, a substantially flat surface 40 (corresponding to the PMD surface 26) is formed in the region of the contacts between the insulators 18 and 20 and the insulators 18 and 20. The surface 40 thus formed is sufficiently flat to improve focusing during photolithography. That is, if one surface is too uneven, the surface of the surface will be in focus and the other parts of the surface will be inaccurate. However, in accordance with an embodiment of the present invention, surface 4 is sufficiently flat to allow the portion of interest of the 15 surface to maintain focus during photolithography. By improving the focus of the entire surface of φ, smaller sized features (e.g., connector 24 of Figure 1) can be formed on the surface 4〇. Furthermore, the width of the contact area (indicated by the dimension D in Fig. 4) can be reduced. One advantage of reducing the joint area is that the density of the device (e.g., devices 14 and 16 of Figure 20) can be increased. Since the width D is reduced in size, a material such as |g can no longer fill the contact area, and a suitable contact can be formed. In accordance with an embodiment of the present invention, CVD of first metallization layer 32 - in one embodiment, CVI of tungsten is used to properly fill the smaller contact regions to form a suitable junction 22. In one embodiment 200805566, dimension D is in the range of approximately 0. 35 - 〇 50 microns. In block 204 of Fig. 2, and also in conjunction with Fig. 5, in one embodiment, a second barrier layer 33 is deposited over the surface formed in the previous block 2〇3. In one embodiment, the second barrier layer 33 is composed of titanium 5. In block 2, 5 of Fig. 2, and also in conjunction with Fig. 5, a second metallization layer 34 is deposited over the second barrier layer 33. In one embodiment, the "brother" - metallization layer 34 includes Cui Lu. In block 2, 6 of Fig. 2, a mask is used in accordance with a photolithography process to pattern the second metallization layer 34. The second metallization layer 34 is etched to form the first! Figure connector 24. Figure 6 is a top down view of the structure 1 of the first embodiment of the present invention, showing the connector 24 crossing the plurality of contacts 22 after the etching process of the block 2〇6 (2nd) Figure). 15 Figure 7 is a cross-sectional view of a selected layer showing structure 70 of another embodiment of the present invention. With respect to the joint 22 of the structure 1 of Fig. i, it may be 1 平面 plane joint, and the joint 71 of Fig. 7 extends into the base 12 and may be a ditch joint. The contacts extend below the upper surface 72 of the substrate 12 by the structure 7 所示 shown in FIG. The elements of structure 70 can be formed using step 200 of the second drawing. In summary, it is convenient to use photolithography to fabricate semiconductor devices having smaller features in accordance with embodiments of the present invention. Smaller contacts can be formed by depositing materials like tungsten to smaller contact areas. The final structure is engraved to form a substantially flat surface to improve focus, allowing for downsizing. 11 200805566 • The sign is formed on the surface. f. Embodiments of the invention are described as such. While the invention has been described in connection with the specific embodiments thereof, it should be understood that the invention is not limited to the embodiments, but may be constructed in accordance with the following claims. 5 [Simple Description of the Drawings] ^ Fig. 1 is a cross-sectional view showing a selection layer showing a structure of an embodiment of the present invention. Fig. 2 is a flow chart showing the process used in the manufacture of the structure of Fig. 1 according to an embodiment of the present invention. 10, 4, and 5 are cross-sectional views showing selected stages in the manufacture of the structure of Fig. 1 of one embodiment of the present invention. Fig. 6 is a top down view of a portion of the structure of Fig. 1 of an embodiment of the present invention. Figure 7 is a cross-sectional view of a selected layer showing a structure of another embodiment of the present invention. ^ [Main component symbol description] 10 Structure 24 Connector 12 Base 26 Surface 14 Device 30 First barrier layer 16 Device 32 First metallization layer 18 Insulator 33 Second barrier layer 20 Insulator 34 Second metallization layer 22 Contact 40 Surface 12 200805566 70 Structure 203 Block 71 Contact 204 Block 72 Upper Surface 205 Block 200 Process 206 Block 201 Square 202 Square
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