TW200414532A - Gate self-aligned four-mask power transistor device and the manufacturing method thereof - Google Patents

Abstract

The present invention provides a gate self-aligned four-mask power transistor device and the manufacturing method thereof, and particularly a ate self-aligned four-mask power transistor device and the manufacturing method thereof for reducing the number of masks, the number of processes, the cost, the resistance ratio, and improving the device conductivity. The method is to etch part of the area on the gate oxide layer and the gate polysilicon layer, wherein it forms the unetched gate oxide layer and the gate polysilicon layer right above the p-well area, so as to reduce a mask during conducting the ion implantation in the N+ source area , and to reduce the processes, the cost, and to improve the device quality. The method employs the dry or wet etching after the source implantation to remove the unetched gate oxide layer and the gate polysilicon layer; then, conducting the ion implantation of P+ plugs and depositing a layer of metal Ti for reducing the source contact resistance (Rc) to reduce the connection resistance (R<DSON>), and improve the device conductivity.

Description

200414532 V. Description of the invention (1) (1) Technical field to which the invention belongs: The present invention relates to a gate self-aligned four-mask power transistor device and a manufacturing method thereof, and particularly to a method using a field oxide layer as an isolation The barrier makes it possible to omit a photomask when the N + source region is implanted, which not only does not affect the process and device quality, but also reduces the production cost of the product. After forming the source implant, dry or wet etching is used. The non-etched gate oxide and gate polycrystalline silicon layer are removed, and then P + plugs are implanted, and a layer of metal titanium (T i) is deposited to reduce the source contact resistance (RC), thereby reducing the on-resistance ( RDSQN) to improve the conductivity of the device. (2) Prior technology: According to the production of high-power transistor devices such as high-power MOSFETs, the complexity of the process and product is judged according to the lithography steps and the number of photomasks. Regardless of the production method used, the general process is (1) defining the active area, (2) making P-well or N-well, (3) implanting the channel barrier, (4) growing the oxide layer and the gate polycrystalline silicon layer (5) Doping of various ion implants, (6) Deposition of BPSG, (7) Fabrication of metal wiring, (8) Construction of the entire integrated circuit, etc., the process experienced can be quite complicated, with the simplest single In terms of the structure of the wafer, at least five photomasks for different purposes are required, as shown in Figures 1 (a) to 1 (1). In the traditional wafer manufacturing process, an epitaxial layer 2 is grown on the substrate 1 in an active mask step, and a field oxide layer 3 and a gate oxide layer 3 are grown on the epitaxial layer 2 1 And gate polycrystalline silicon layer 41, as shown in Figures 1 (a) to 1 (c); after the active photomask stage is performed, the main die area (Main Die)

200414532 V. Description of the invention (2) A r e a) ′ perform the polysilicon mask (p 〇 1 y μ a s k) step, _

After part of the structure area is hollowed out, p and f are implanted by ion implantation, as shown in Figures 1 (d) to (e) before the engraving; the gate reticle (n, outer area 5, Mask ) Step, use a mask to cover the hollow area, and then use the P-card area 5 as the source electrode 6, as shown in Figures 1 (f) to 1 (g), the two debris tend to contact the mask (c〇ntact Mask) step, and then deposit BPSG on top of the polysilicon layer 41 and isolate it from the polysilicon layer 41 for isolation, and then t-layer etch or clear etching to completely remove the BPSG layer that is not protected by photoresist. Then P + dopant is introduced into the P-well region as a plug 7, as shown in FIG. 1 (h); finally, a metal mask step is performed to perform alloy-free sputtering And metal wiring process, as shown in Figure 1 (i); &amp; after performing the active mask step, perform polysilicon mask, contact mask, and metal mask in the gate coding area (gate Bias ^ ea). The system is shown in Figures i (j) to 1 (1). At this time, the main structure of the entire integrated circuit is completely presented on the wafer, and a protective layer is deposited above these circuits and components, and then external packaging of the integrated circuit, solder pads, and the like are performed. The wafer made in this way is covered with a photomask in the P-well area, and N is implanted on the P-Shaan area with multiple impurities. Therefore, an additional photomask must be added.

During a production process, increasing the number of photomasks will increase the cost, and one more system will greatly reduce the reliability of the product. In addition, when the aluminum oxide layer is deposited on the gate oxide layer and = 9, the second layer, the isolation is used. The field oxide layer is thick in thickness and the resistance between the contact surface and the resistance between the wires is relatively high, so the conductivity to the device is relatively poor, and it is easy to produce heat flow effects. The present invention is based on the traditional Produced by high power transistor device manufacturing process

Page 7 200414532 V. Description of the invention (3) Various defects of the original device. The present invention proposes a gate self-alignment four-channel photomask power transistor device and a manufacturing method thereof to improve the defects of the prior art. (3) Content of the invention: The object of the present invention is to provide a gate self-aligning four-mask power transistor device with reduced number of masks and a method for manufacturing the same. A secondary object of the present invention is to provide a gate self-aligned four-mask power transistor device for improving conductivity of a device and a manufacturing method thereof. Another object of the present invention is to provide a gate self-aligned four-mask power transistor device with reduced manufacturing process and improved product reliability, and a method for manufacturing the same. The gate self-aligned four photomask power transistor device and its manufacturing method of the present invention are located at the central hollow portion of a gate oxide layer and a polycrystalline silicon layer grown above an epitaxial layer, and a gate oxide remains. Layer and gate polycrystalline silicon layer, doping the N + source in the P-well region, and omitting a photomask; and in aluminum sputtering, the field oxide layer is etched to a small thickness and titanium is sputtered. Achieving components with good electrical conductivity, the following is a technical example of the present invention to achieve the above and other objectives, take a better specific example with a simple process description, so that the reviewers can easily understand. (4). Embodiments: Refer to Figures 2 (a) to 2 (1), which are cross-sectional views of the gate self-aligning four-mask power MOSFET device of the present invention and its manufacturing method. The process steps include the following:

200414532 V. Description of the invention (4) 1. In the Active Mask step: It includes a substrate 1 and a stupid crystal layer 2 is grown on the substrate. An oxide layer is grown on the worm crystal layer 2 by thermal oxidation. 3. A gate oxide layer 3 1 and a polycrystalline silicon layer 4 1 are grown over the field oxide layer 3, and a flat portion of the gate oxide layer 3 1 is a main grain region (M ain Die A rea ), As shown in Figures 2 (a) to 2 (c); 2. After the Active Mask step is performed, in the main die area: execute the polycrystalline lithography mask (Poly

In the mask step), the part that is not protected by photoresist is removed by using an etching technique to form a plurality of gate oxide layers 3 1 and a polycrystalline silicon layer 4 1 as shown in FIG. 2 (d), and an independent gate The polar oxide layer 3 1 ′ and the polycrystalline silicon layer 41 ′, the P-dopant is drawn into the divided P-well region 5 by ion implantation in the central hollow portion, such as the second (d) to 2 (e) As shown in the figure; when the gate mask (N-P 1 us M ask) step is performed, the gate oxide layer and the polycrystalline silicon layer are used for masking. At this time, there is no need to use a mask for masking, that is, ion implantation is performed in the P-well region 5. The N + dopant is approached to form the N + source region 6, as shown in Figures 2 (f) to 2 (g); and then a Contact Mask step is performed in the P-well region. A high concentration of P + dopants is introduced to form P + plugs 7, and then a dielectric material BPSG is deposited over the above elements, and then the BPSG that is not protected by photoresist is removed by dry etching or wet etching, and the independent Gate oxide layer 3 1 ′ and polycrystalline silicon layer 4 1 ′ until the contact windows of the electrodes of the MOSFET device are etched, as shown in FIG. 2 (h); After performing the metal mask (Metal Mask) step, a metal sputtering step can be first sputter titanium (T i) is deposited after the metal alloy,

200414532 5. Description of the invention (5) Or directly deposit aluminum alloy on the surface of the device, and finally metallize to remove the metal layer not covered by photoresist by etching, and then remove the photoresist by dry or fishing method, and the entire structure will appear. The protective layer of the protection element and the circuit is deposited on the device, and the whole process is completed through construction, as shown in Figure 2 (i). Third, the active mask step is performed in the gate coding area. (Gate Bias Area), the gate metallization process is performed: when the hafnium oxide layer 3 is grown, a square wave gate oxide layer 3 1 is formed, and a polycrystalline silicon layer 4 1 is grown thereon, As shown in Fig. 2 (k); thereafter, the dielectric material BPSG is deposited, and then a contact mask step is performed. First, dry etching is performed to remove the BPSG and the polycrystalline silicon layer 31, and then wet etching is performed to The BPSG is etched sideways, but when the BPSG is etched, it is also etched downward. The field oxide layer under the polycrystalline silicon gate layer is thinned, as shown in Figure 2 (k); then the gate metal layer is deposited. Due to the exposed polycrystalline silicon gate layer At the corner of the silicon gate layer 41, titanium (T i) metal sputtering can be used to reduce the contact resistance R c of the gate electrode, and then an aluminum alloy (A 1) is deposited on the titanium metal. If the side etching is wide enough, Aluminium alloy can also be deposited directly, as shown in Figure 2 (1), and the protective layer is deposited and assembled to complete the process of the device of the present invention. A feature of the present invention is that a thick oxide layer needs to be placed under the gate coding region, otherwise, when performing contact window etching, the contact inside the contact window must be restored in the main grain area (Maine Die ie Area). The spar evening layer and the gate oxide layer are completely removed. At the same time, the polycrystalline silicon layer and the oxide layer in the gate coding region will be cut through, which will cause the subsequent deposition of the gate metal layer directly.

Page 10 200414532 V. Description of the invention (6) On the silicon wafer epitaxial layer, in the power metal-oxide-semiconductor field-effect transistor, the epitaxial layer is at the same potential as the drain (D rai η), which leads to the The drain and gate are shorted, causing component failure. In the conventional technology of power field effect transistor, selective contact etching is used to etch the contact window, that is, only the BPSG is removed, and the polycrystalline silicon gate is not etched, so there is no Digging conditions occur, as shown in Figure 1 (k). As mentioned above, the gate self-aligned four-mask power transistor device and its manufacturing method of the present invention, the gate oxide layer and the gate polycrystalline silicon layer are etched to form one or several regions. When the + source region is planted, a photomask can be reduced to reduce the manufacturing process and reduce the cost. Because its N + source portion is self-aligned, the reliability and quality of the device can be improved, which is formed by the process of the present invention. The semiconductor device has the ability to improve the avalanche breakdown voltage, because when the device is in the closed state, because the P-well has a high concentration of doped P + plugs directly contacting the N- epitaxial layer, the resistance between them is low. When operating at high voltage, high current will enter the source from the P + plug well area, so the voltage drop generated in the P-well area will be much less than 0.7 V, making it difficult to conduct the parasitic transistor between them, so Can improve its ability to withstand avalanche breakdown voltage; when sputtering titanium alloy and deposited aluminum metal, it can reduce the contact resistance between metal and polycrystalline silicon and semiconductor, so the device has good conductivity and increases the reliability and reduction of the device Damage due to heat flow. To sum up, the structure and technical means disclosed by the specific examples of the gate self-aligned four-mask power electric crystal device and its manufacturing method of the present invention

200414532 V. Description of the invention (7) Not found in the conventional one, and the specific structure can reduce a photomask, reduce the process, reduce the production cost, the titanium alloy and aluminum alloy deposited on the gate oxide layer and the polycrystalline silicon layer, and P + plug can improve the conductivity of the device, improve the reliability and quality of the device, fully comply with the patent requirements, but the above description is described with the N-Type MOSFET device, the invention can also be applied to the P-Type MOSFET Device, which only needs to change P to N and N to P; those skilled in the art will understand that the present invention is not limited to the above description, but can allow various modifications and changes, All transformation designs made within the scope of the following patent applications are included in the scope of this patent.

Page 12 200414532 Brief Description of Drawings Figures 1 (a) to 1 (c) are cross-sectional views of the active photomask process in the manufacturing steps of a conventional power transistor device. Figures 1 (d) to 1 (i) are the cross-sections of the polysilicon mask, gate mask, contact mask, and metal mask process in the main crystal grain area after the active mask process in the process steps of the traditional power transistor device. Sectional view. Figures 1 (j) to 1 (1) are cross-sectional views of the polysilicon mask, contact mask, and metal mask processes in the gate bias region of the active mask process during the traditional power transistor device manufacturing process. . Figures 2 (a) to 2 (c) are cross-sectional views of the active photomask manufacturing process during the manufacturing steps of a conventional power transistor device. Figures 2 (d) to 2 (i) are the cross-sections of the polysilicon mask, gate mask, contact mask, and metal mask process in the main grain area after the active mask process in the process steps of the traditional power transistor device. Sectional view. Figures 2 (j) to 2 (1) are cross-sectional views of a polysilicon mask, a contact mask, and a metal mask process in a gate bias region after an active mask process in a conventional power transistor device manufacturing process. Description of main component symbols: 1 substrate 2 stupid crystal layer 3 field oxide layer 31 gate oxide layer 31 ’gate oxide layer 41 gate polycrystalline layer 41 ′ gate polycrystalline layer

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Claims (1)

200414532 VI. Application Patent Scope 1. A gate self-aligning four-mask power transistor device 'includes: a substrate, an epitaxial layer growing on the substrate, and a gate oxide layer and a polycrystalline silicon layer growing on the epitaxial Above the layer, one or several gate oxide layers and polycrystalline silicon layers are formed after etching. P-dopant ions are implanted above the epitaxial layer to form a P-well region, and then in the P-well region. N + dopants are implanted to form N + source regions, and P + dopants are implanted to form P + plugs. A BPSG is used for isolation, and the BPSG portion that is not masked by photoresist is etched. It is removed until the contact windows are etched away, a metallized wiring, and a protective layer are deposited on the device. The device is characterized in that the gate oxide layer and the gate polycrystalline silicon layer are etched into one or several and one gate. The electrode oxide layer and the gate polycrystalline silicon layer have a P-well region with a bottomed inwardly-divided P-well structure, and when the N + source region is implanted, at least one photomask can be reduced to reduce process and reduce Manufacturing cost, and improving the conductivity and reliability of the device2. The gate self-aligned four-mask power transistor device described in the first item of the scope of patent application, wherein when the gate metallization is connected to the growth of the gate oxide layer, a square wave is formed, and then a square wave is formed thereon. The gate polycrystalline stone layer is grown. After dry or wet etching, the thickness is small and has a square wave shape. BPSG is deposited thereon, and then it is removed by etching to make the gate appear, and the aluminum alloy is deposited to form a good conductivity and reliable. Sexual increase device. 3. The gate self-aligning four-mask power transistor device described in item 1 of the scope of patent application, wherein the metallized wiring is characterized in that the source metal is formed on the surface of the device to connect the metal parts of the device. 4. Gate self-alignment as described in item 1 and 3 of the patent application Page 15 200414532 6. Scope of patent application The power transistor device of the cover, wherein the metallized wiring is characterized in that an aluminum alloy is deposited on the gate contact window surface. 5. The gate self-aligning four photomask power transistor device as described in claims 1 and 3, wherein the metallized wiring is characterized in that the gate is first sputtered with titanium on the surface of the contact window, Re-deposit aluminum alloy on top of titanium. 6. — A method for manufacturing a gate self-aligned four-mask power transistor device, including the following steps: preparing a substrate; growing an epitaxial layer over the substrate; growing a gate oxide layer and a polycrystalline silicon layer, where Above the epitaxial layer, one or several gate oxide layers and polycrystalline silicon layers are formed after etching. P-dopant ions are implanted above the epitaxial layer to form a P-well region. N + dopants are implanted in the well area to form the N + source region, and then P + dopants are implanted to form the P + plug; BPSG is deposited for isolation, and the unshielded part is etched by etching. Remove until the contact windows are etched away; make metallized wiring connections; deposit aluminum alloy on the surface of the device; deposit a protective layer on the device; form a reduction by combining the above processes and structures The manufacturing process reduces the cost and improves the conductivity and reliability of the device. 7. The method for manufacturing a gate self-aligned four-mask power transistor device as described in item 6 of the patent application, wherein the gate oxide layer and the polycrystalline silicon 200414532 6. Scope of patent application The silicon layer is etched into one or several and one. Gate oxide layer and polycrystalline silicon layer. When N + source region is implanted, a photomask can be reduced, process can be reduced, and manufacturing cost can be reduced. 8. The method for manufacturing a gate self-aligned four-mask power transistor device according to items 6 and 7 of the scope of patent application, characterized in that the P-well region is formed as a split P well with a bottom inward depression. structure. 9. The method for manufacturing a gate self-aligned four-mask power transistor device as described in item 6 of the scope of the patent application, wherein when the gate metallization is connected to the growth of the gate oxide layer, a square wave is formed, and then A gate polycrystalline silicon layer is grown thereon, and the thickness of the gate polycrystalline silicon layer is small or inverted by dry or wet etching. BPSG is deposited thereon, and then the gate electrode is revealed by etching, and the titanium metal and the deposited aluminum alloy are sputtered to form Device with good conductivity and increased reliability. I 0. The manufacturing method of a self-aligned four-mask photoresistor power transistor device as described in item 6 of the scope of patent application, wherein the process of connecting the metalized wiring part is characterized by depositing source metal on the surface of the device To connect the metal parts of the device. II. The manufacturing method of the gate self-aligning four photomask power transistor device as described in the patent application scope item 6 and 10, wherein the process of connecting the metalized wiring part is characterized by depositing aluminum alloy on the gate The pole touches the window surface. 1 2. The manufacturing method of the gate self-aligning four photomask power transistor device as described in item 6 and 10 of the scope of patent application, wherein the process of connecting the metalized wiring part is characterized by first sputtering titanium Metal to gate Page 17 200414532 6. Scope of patent application Those who touch the surface of the window and then deposit Shao alloy on titanium to reduce the contact resistance (R c). Page 18