TW200741840A - Wafer having an asymmetric edge profile and method of making the same - Google Patents

Wafer having an asymmetric edge profile and method of making the same

Info

Publication number
TW200741840A
TW200741840A TW095114099A TW95114099A TW200741840A TW 200741840 A TW200741840 A TW 200741840A TW 095114099 A TW095114099 A TW 095114099A TW 95114099 A TW95114099 A TW 95114099A TW 200741840 A TW200741840 A TW 200741840A
Authority
TW
Taiwan
Prior art keywords
wafer
edge profile
main surface
making
same
Prior art date
Application number
TW095114099A
Other languages
English (en)
Other versions
TWI314758B (en
Inventor
Chih-Ping Kuo
Original Assignee
Touch Micro System Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Touch Micro System Tech filed Critical Touch Micro System Tech
Priority to TW095114099A priority Critical patent/TWI314758B/zh
Priority to US11/456,090 priority patent/US20070248786A1/en
Publication of TW200741840A publication Critical patent/TW200741840A/zh
Priority to US12/212,653 priority patent/US20090023364A1/en
Application granted granted Critical
Publication of TWI314758B publication Critical patent/TWI314758B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/21—Circular sheet or circular blank
    • Y10T428/219—Edge structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
TW095114099A 2006-04-20 2006-04-20 Wafer having an asymmetric edge profile and method of making the same TWI314758B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW095114099A TWI314758B (en) 2006-04-20 2006-04-20 Wafer having an asymmetric edge profile and method of making the same
US11/456,090 US20070248786A1 (en) 2006-04-20 2006-07-07 Wafer having an asymmetric edge profile and method of making the same
US12/212,653 US20090023364A1 (en) 2006-04-20 2008-09-18 Method of making a wafer having an asymmetric edge profile

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095114099A TWI314758B (en) 2006-04-20 2006-04-20 Wafer having an asymmetric edge profile and method of making the same

Publications (2)

Publication Number Publication Date
TW200741840A true TW200741840A (en) 2007-11-01
TWI314758B TWI314758B (en) 2009-09-11

Family

ID=38619804

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095114099A TWI314758B (en) 2006-04-20 2006-04-20 Wafer having an asymmetric edge profile and method of making the same

Country Status (2)

Country Link
US (2) US20070248786A1 (zh)
TW (1) TWI314758B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8710665B2 (en) * 2008-10-06 2014-04-29 Infineon Technologies Ag Electronic component, a semiconductor wafer and a method for producing an electronic component
US20110129648A1 (en) * 2009-11-30 2011-06-02 Yabei Gu Glass sheet article with double-tapered asymmetric edge
TWI669789B (zh) * 2016-04-25 2019-08-21 矽品精密工業股份有限公司 電子封裝件
TWI610403B (zh) * 2017-03-03 2018-01-01 矽品精密工業股份有限公司 基板結構及其製法與電子封裝件
JP2020145272A (ja) * 2019-03-05 2020-09-10 トヨタ自動車株式会社 半導体ウエハ

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0624199B2 (ja) * 1982-07-30 1994-03-30 株式会社日立製作所 ウエハの加工方法
JPS6088535U (ja) * 1983-11-24 1985-06-18 住友電気工業株式会社 半導体ウエハ
JPH0624179B2 (ja) * 1989-04-17 1994-03-30 信越半導体株式会社 半導体シリコンウェーハおよびその製造方法
JPH0624200B2 (ja) * 1989-04-28 1994-03-30 信越半導体株式会社 半導体デバイス用基板の加工方法
US5021882A (en) * 1989-05-24 1991-06-04 Massachusetts Institute Of Technology Definition television systems
DE19632809C2 (de) * 1996-08-14 2002-06-20 Infineon Technologies Ag Gerät zum chemisch-mechanischen Polieren von Wafern
AT411304B (de) * 1997-06-18 2003-11-25 Sez Ag Träger für scheibenförmige gegenstände, insbesondere silizium-wafer
US7258931B2 (en) * 2002-08-29 2007-08-21 Samsung Electronics Co., Ltd. Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination

Also Published As

Publication number Publication date
US20090023364A1 (en) 2009-01-22
TWI314758B (en) 2009-09-11
US20070248786A1 (en) 2007-10-25

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees