TW200736901A - Method and device for monitoring operations of computer system - Google Patents

Method and device for monitoring operations of computer system

Info

Publication number
TW200736901A
TW200736901A TW095128809A TW95128809A TW200736901A TW 200736901 A TW200736901 A TW 200736901A TW 095128809 A TW095128809 A TW 095128809A TW 95128809 A TW95128809 A TW 95128809A TW 200736901 A TW200736901 A TW 200736901A
Authority
TW
Taiwan
Prior art keywords
shift register
circuit
serial
storage element
testing
Prior art date
Application number
TW095128809A
Other languages
English (en)
Inventor
Juergen Sauler
Reinhard Weiberle
Bernd Mueller
Eberhard Boehl
Yorck Collani
Rainer Gmehlich
Original Assignee
Bosch Gmbh Robert
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bosch Gmbh Robert filed Critical Bosch Gmbh Robert
Publication of TW200736901A publication Critical patent/TW200736901A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3065—Monitoring arrangements determined by the means or processing involved in reporting the monitored data
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B9/00—Safety arrangements
    • G05B9/02—Safety arrangements electric
    • G05B9/03—Safety arrangements electric with multiple-channel loop, i.e. redundant control systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
TW095128809A 2005-08-08 2006-08-07 Method and device for monitoring operations of computer system TW200736901A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102005037230A DE102005037230A1 (de) 2005-08-08 2005-08-08 Verfahren und Vorrichtung zur Überwachung von Funktionen eines Rechnersystems

Publications (1)

Publication Number Publication Date
TW200736901A true TW200736901A (en) 2007-10-01

Family

ID=37680924

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095128809A TW200736901A (en) 2005-08-08 2006-08-07 Method and device for monitoring operations of computer system

Country Status (9)

Country Link
US (1) US8108716B2 (zh)
EP (1) EP1915690A2 (zh)
JP (1) JP2009505186A (zh)
KR (1) KR101031181B1 (zh)
CN (1) CN101243403A (zh)
DE (1) DE102005037230A1 (zh)
RU (1) RU2008108475A (zh)
TW (1) TW200736901A (zh)
WO (1) WO2007017396A2 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005037230A1 (de) 2005-08-08 2007-02-15 Robert Bosch Gmbh Verfahren und Vorrichtung zur Überwachung von Funktionen eines Rechnersystems
DE102011086530A1 (de) * 2010-11-19 2012-05-24 Continental Teves Ag & Co. Ohg Mikroprozessorsystem mit fehlertoleranter Architektur
CN103797489B (zh) * 2011-03-21 2017-12-12 爱迪德技术有限公司 用于安全地将程序执行绑定到且节点锁定到受信任的签名授权机构的系统和方法
JP5541246B2 (ja) * 2011-07-21 2014-07-09 株式会社デンソー 電子制御ユニット
DE102012207215A1 (de) 2012-04-30 2013-10-31 Robert Bosch Gmbh Verfahren und Vorrichtung zur Überwachung von Funktionen eines Rechnersystems, vorzugsweise eines Motorsteuersystems eines Kraftfahrzeuges
KR101558280B1 (ko) 2013-09-02 2015-10-12 주식회사 팀스톤 계측 윈도우 제어 방법 및 이를 수행하는 사용자 단말
DE102013224702A1 (de) * 2013-12-03 2015-06-03 Robert Bosch Gmbh Steuergerät für ein Kraftfahrzeug
DE102013227165A1 (de) * 2013-12-27 2015-07-16 Siemens Aktiengesellschaft Überwachungsvorrichtung zur Überwachung eines Schaltkreises
DE102016125240A1 (de) * 2016-12-21 2018-06-21 Endress+Hauser SE+Co. KG Elektronische Schaltung für ein Feldgerät der Automatisierungstechnik
DE102018120344A1 (de) * 2018-08-21 2020-02-27 Pilz Gmbh & Co. Kg Automatisierungssystem zur Überwachung eines sicherheitskritischen Prozesses
DE102020001561A1 (de) 2020-03-10 2021-09-16 Drägerwerk AG & Co. KGaA Medizingeräteanordnung mit einem Prüfmodul
DE102020119297A1 (de) 2020-07-22 2022-01-27 Endress+Hauser SE+Co. KG Verfahren zum Überwachen eines ersten Prozessors eines Sensormoduls durch einen zweiten Prozessor

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233615A (en) 1991-06-06 1993-08-03 Honeywell Inc. Interrupt driven, separately clocked, fault tolerant processor synchronization
US5751932A (en) * 1992-12-17 1998-05-12 Tandem Computers Incorporated Fail-fast, fail-functional, fault-tolerant multiprocessor system
JPH08297588A (ja) 1995-04-25 1996-11-12 Fujitsu Ltd 二重照合装置
US5875195A (en) * 1997-03-31 1999-02-23 International Business Machines Corporation Method and apparatus for error injection techniques
US6625749B1 (en) 1999-12-21 2003-09-23 Intel Corporation Firmware mechanism for correcting soft errors
US6640313B1 (en) 1999-12-21 2003-10-28 Intel Corporation Microprocessor with high-reliability operating mode
US6615366B1 (en) 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode
US6772368B2 (en) 2000-12-11 2004-08-03 International Business Machines Corporation Multiprocessor with pair-wise high reliability mode, and method therefore
DE10136335B4 (de) 2001-07-26 2007-03-22 Infineon Technologies Ag Prozessor mit mehreren Rechenwerken
US7085959B2 (en) 2002-07-03 2006-08-01 Hewlett-Packard Development Company, L.P. Method and apparatus for recovery from loss of lock step
JP2004259137A (ja) * 2003-02-27 2004-09-16 Denso Corp 電子制御装置
EP1639454A2 (de) * 2003-06-24 2006-03-29 Robert Bosch GmbH Verfahren zur umschaltung zwischen wenigstens zwei betriebsmodi einer prozessoreinheit sowie entsprechende prozessoreinheit
DE10349581A1 (de) 2003-10-24 2005-05-25 Robert Bosch Gmbh Verfahren und Vorrichtung zur Umschaltung zwischen wenigstens zwei Betriebsmodi einer Prozessoreinheit
GB0325553D0 (en) * 2003-11-01 2003-12-03 Ibm Method and apparatus for activating/deactivating run-time determined software routines in Java compiled bytecode applications
JP2008518339A (ja) * 2004-10-25 2008-05-29 ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング 少なくとも２つの実施ユニットを有する計算機において切り替える装置および方法
EP1807764A2 (de) * 2004-10-25 2007-07-18 Robert Bosch Gmbh Vorrichtung und verfahren zur modusumschaltung bei einem rechnersystem mit wenigstens zwei ausführungseinheiten
KR100663864B1 (ko) * 2005-06-16 2007-01-03 엘지전자 주식회사 멀티-코어 프로세서의 프로세서 모드 제어장치 및 방법
DE102005037230A1 (de) 2005-08-08 2007-02-15 Robert Bosch Gmbh Verfahren und Vorrichtung zur Überwachung von Funktionen eines Rechnersystems

Also Published As

Publication number Publication date
KR101031181B1 (ko) 2011-04-26
US20100192021A1 (en) 2010-07-29
WO2007017396A2 (de) 2007-02-15
CN101243403A (zh) 2008-08-13
JP2009505186A (ja) 2009-02-05
EP1915690A2 (de) 2008-04-30
WO2007017396A3 (de) 2007-10-25
US8108716B2 (en) 2012-01-31
KR20080032168A (ko) 2008-04-14
DE102005037230A1 (de) 2007-02-15
RU2008108475A (ru) 2009-09-20

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