TW200731278A - Multiported memory with ports mapped to bank sets - Google Patents

Multiported memory with ports mapped to bank sets

Info

Publication number
TW200731278A
TW200731278A TW095147145A TW95147145A TW200731278A TW 200731278 A TW200731278 A TW 200731278A TW 095147145 A TW095147145 A TW 095147145A TW 95147145 A TW95147145 A TW 95147145A TW 200731278 A TW200731278 A TW 200731278A
Authority
TW
Taiwan
Prior art keywords
bank sets
ports mapped
multiported memory
bank
multiported
Prior art date
Application number
TW095147145A
Other languages
English (en)
Inventor
Kuljit S Bains
John B Halbert
Randy B Osborne
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW200731278A publication Critical patent/TW200731278A/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
TW095147145A 2005-12-23 2006-12-15 Multiported memory with ports mapped to bank sets TW200731278A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/317,757 US20070150667A1 (en) 2005-12-23 2005-12-23 Multiported memory with ports mapped to bank sets

Publications (1)

Publication Number Publication Date
TW200731278A true TW200731278A (en) 2007-08-16

Family

ID=38195272

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095147145A TW200731278A (en) 2005-12-23 2006-12-15 Multiported memory with ports mapped to bank sets

Country Status (7)

Country Link
US (1) US20070150667A1 (zh)
KR (1) KR100968636B1 (zh)
CN (1) CN101300558B (zh)
DE (1) DE112006003503T5 (zh)
GB (1) GB2446971B (zh)
TW (1) TW200731278A (zh)
WO (1) WO2007078632A2 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8914589B2 (en) * 2008-09-22 2014-12-16 Infineon Technologies Ag Multi-port DRAM architecture for accessing different memory partitions
US8495310B2 (en) * 2008-09-22 2013-07-23 Qimonda Ag Method and system including plural memory controllers and a memory access control bus for accessing a memory device
US8250312B2 (en) * 2009-04-29 2012-08-21 Micron Technology, Inc. Configurable multi-port memory devices and methods
US8769213B2 (en) 2009-08-24 2014-07-01 Micron Technology, Inc. Multi-port memory and operation
US9158683B2 (en) * 2012-08-09 2015-10-13 Texas Instruments Incorporated Multiport memory emulation using single-port memory devices
US9299400B2 (en) 2012-09-28 2016-03-29 Intel Corporation Distributed row hammer tracking
US9934143B2 (en) 2013-09-26 2018-04-03 Intel Corporation Mapping a physical address differently to different memory devices in a group
US9117542B2 (en) 2013-09-27 2015-08-25 Intel Corporation Directed per bank refresh command
US9361973B2 (en) 2013-10-28 2016-06-07 Cypress Semiconductor Corporation Multi-channel, multi-bank memory with wide data input/output
US9779813B2 (en) 2015-09-11 2017-10-03 Macronix International Co., Ltd. Phase change memory array architecture achieving high write/read speed

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03238539A (ja) * 1990-02-15 1991-10-24 Nec Corp メモリアクセス制御装置
US5875470A (en) * 1995-09-28 1999-02-23 International Business Machines Corporation Multi-port multiple-simultaneous-access DRAM chip
US6877071B2 (en) * 2001-08-20 2005-04-05 Technology Ip Holdings, Inc. Multi-ported memory
KR100546331B1 (ko) * 2003-06-03 2006-01-26 삼성전자주식회사 스택 뱅크들 마다 독립적으로 동작하는 멀티 포트 메모리장치
JP3811143B2 (ja) * 2003-07-09 2006-08-16 株式会社東芝 メモリ制御回路
US7167946B2 (en) * 2003-09-30 2007-01-23 Intel Corporation Method and apparatus for implicit DRAM precharge
US7533232B2 (en) * 2003-11-19 2009-05-12 Intel Corporation Accessing data from different memory locations in the same cycle
US20050138276A1 (en) * 2003-12-17 2005-06-23 Intel Corporation Methods and apparatus for high bandwidth random access using dynamic random access memory

Also Published As

Publication number Publication date
WO2007078632A3 (en) 2007-09-13
KR20080077214A (ko) 2008-08-21
WO2007078632A2 (en) 2007-07-12
DE112006003503T5 (de) 2008-10-30
GB2446971A (en) 2008-08-27
US20070150667A1 (en) 2007-06-28
CN101300558B (zh) 2010-12-22
GB0806199D0 (en) 2008-05-14
GB2446971B (en) 2010-11-24
CN101300558A (zh) 2008-11-05
KR100968636B1 (ko) 2010-07-06

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