TW200701717A - Prediction of an optimal sampling point for clock resynchronization in a source synchronous data channel - Google Patents

Prediction of an optimal sampling point for clock resynchronization in a source synchronous data channel

Info

Publication number
TW200701717A
TW200701717A TW095105939A TW95105939A TW200701717A TW 200701717 A TW200701717 A TW 200701717A TW 095105939 A TW095105939 A TW 095105939A TW 95105939 A TW95105939 A TW 95105939A TW 200701717 A TW200701717 A TW 200701717A
Authority
TW
Taiwan
Prior art keywords
clock
prediction
source synchronous
data channel
sampling point
Prior art date
Application number
TW095105939A
Other languages
English (en)
Inventor
Sudhanshu Jain
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of TW200701717A publication Critical patent/TW200701717A/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0091—Transmitter details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
TW095105939A 2005-02-24 2006-02-22 Prediction of an optimal sampling point for clock resynchronization in a source synchronous data channel TW200701717A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/063,969 US20060188046A1 (en) 2005-02-24 2005-02-24 Prediction of an optimal sampling point for clock resynchronization in a source synchronous data channel

Publications (1)

Publication Number Publication Date
TW200701717A true TW200701717A (en) 2007-01-01

Family

ID=35457307

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095105939A TW200701717A (en) 2005-02-24 2006-02-22 Prediction of an optimal sampling point for clock resynchronization in a source synchronous data channel

Country Status (5)

Country Link
US (1) US20060188046A1 (zh)
EP (1) EP1696600B1 (zh)
CN (1) CN1825794A (zh)
DE (1) DE602005022547D1 (zh)
TW (1) TW200701717A (zh)

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US8024599B2 (en) * 2007-03-08 2011-09-20 Sandisk Il Ltd Bias and random delay cancellation
US8837657B1 (en) * 2012-07-18 2014-09-16 Cypress Semiconductor Corporation Multi-phase sampling circuits and methods
US8941780B2 (en) * 2013-01-22 2015-01-27 Silicon Image, Inc. Mechanism for facilitating dynamic phase detection with high jitter tolerance for images of media streams
US10153844B2 (en) 2017-04-03 2018-12-11 Futurewei Technologies, Inc. Channel recovery in burst-mode, time-division multiplexing (TDM) passive optical networks (PONs)
US10778364B2 (en) 2017-04-15 2020-09-15 Futurewei Technologies, Inc. Reduced power consumption for digital signal processing (DSP)-based reception in time-division multiplexing (TDM) passive optical networks (PONs)
CN114153772B (zh) * 2020-09-08 2024-04-12 珠海全志科技股份有限公司 数据采样点的确定方法及装置

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EP0618700A1 (en) * 1993-04-02 1994-10-05 ALCATEL BELL Naamloze Vennootschap Data synchronization device
JPH07311735A (ja) * 1994-05-18 1995-11-28 Hitachi Ltd データ転送装置
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US6255880B1 (en) * 1999-10-25 2001-07-03 Xilinx, Inc. One-shot DLL circuit and method
JP3671782B2 (ja) * 1999-12-10 2005-07-13 富士通株式会社 信号位相調整回路
US6621760B1 (en) * 2000-01-13 2003-09-16 Intel Corporation Method, apparatus, and system for high speed data transfer using source synchronous data strobe
US6990161B2 (en) * 2001-01-09 2006-01-24 International Business Machines Corporation Phase selection mechanism for optimal sampling of source synchronous clocking interface data
US20020090045A1 (en) * 2001-01-10 2002-07-11 Norm Hendrickson Digital clock recovery system
JP3597142B2 (ja) * 2001-04-20 2004-12-02 日本電気株式会社 中心位相判定回路とその中心位相判定方法
US6917660B2 (en) * 2001-06-04 2005-07-12 Intel Corporation Adaptive de-skew clock generation
US6496043B1 (en) * 2001-12-13 2002-12-17 Lsi Logic Corporation Method and apparatus for measuring the phase of captured read data
US7103126B2 (en) * 2002-01-17 2006-09-05 Micron Technology, Inc. Method and circuit for adjusting the timing of output data based on the current and future states of the output data
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JP3761481B2 (ja) * 2002-03-26 2006-03-29 株式会社東芝 同期回路
KR100448707B1 (ko) * 2002-08-20 2004-09-13 삼성전자주식회사 클럭 및 데이터 복원 회로 및 방법
US6680874B1 (en) * 2002-08-29 2004-01-20 Micron Technology, Inc. Delay lock loop circuit useful in a synchronous system and associated methods
US7113560B1 (en) * 2002-09-24 2006-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Serial link scheme based on delay lock loop
US7164742B2 (en) * 2002-10-31 2007-01-16 Intel Corporation Deskew architecture
US7043654B2 (en) * 2002-12-31 2006-05-09 Intel Corporation Selecting a first clock signal based on a comparison between a selected first clock signal and a second clock signal
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US20060187729A1 (en) * 2005-02-24 2006-08-24 Broadcom Corporation Source synchronous communication channel interface receive logic

Also Published As

Publication number Publication date
EP1696600A3 (en) 2006-11-15
DE602005022547D1 (de) 2010-09-09
EP1696600B1 (en) 2010-07-28
CN1825794A (zh) 2006-08-30
US20060188046A1 (en) 2006-08-24
EP1696600A2 (en) 2006-08-30

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