TW200632930A - Memory module and signal line arrangement method thereof - Google Patents
Memory module and signal line arrangement method thereofInfo
- Publication number
- TW200632930A TW200632930A TW095108720A TW95108720A TW200632930A TW 200632930 A TW200632930 A TW 200632930A TW 095108720 A TW095108720 A TW 095108720A TW 95108720 A TW95108720 A TW 95108720A TW 200632930 A TW200632930 A TW 200632930A
- Authority
- TW
- Taiwan
- Prior art keywords
- pcb
- same signal
- signal applying
- memory module
- contact
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10159—Memory
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10545—Related components mounted on both sides of the PCB
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050021552A KR100615606B1 (ko) | 2005-03-15 | 2005-03-15 | 메모리 모듈 및 이 모듈의 신호 라인 배치 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200632930A true TW200632930A (en) | 2006-09-16 |
TWI303437B TWI303437B (en) | 2008-11-21 |
Family
ID=37009119
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095108720A TWI303437B (en) | 2005-03-15 | 2006-03-15 | Memory module and signal line arrangement method thereof |
Country Status (4)
Country | Link |
---|---|
US (1) | US7390973B2 (zh) |
JP (1) | JP5052801B2 (zh) |
KR (1) | KR100615606B1 (zh) |
TW (1) | TWI303437B (zh) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101166401B (zh) * | 2006-10-16 | 2011-11-30 | 辉达公司 | 用于在高速系统中放置多个负载的方法和系统 |
KR101639618B1 (ko) | 2009-02-03 | 2016-07-15 | 삼성전자주식회사 | 전자 소자 모듈 |
US8502390B2 (en) | 2011-07-12 | 2013-08-06 | Tessera, Inc. | De-skewed multi-die packages |
US8513817B2 (en) | 2011-07-12 | 2013-08-20 | Invensas Corporation | Memory module in a package |
US8823165B2 (en) | 2011-07-12 | 2014-09-02 | Invensas Corporation | Memory module in a package |
US8659140B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
TWI501254B (zh) | 2011-10-03 | 2015-09-21 | Invensas Corp | 用於具有正交窗之多晶粒導線結合總成之短線最小化 |
EP2764544A1 (en) | 2011-10-03 | 2014-08-13 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
TWI515864B (zh) | 2011-10-03 | 2016-01-01 | 英帆薩斯公司 | 具有自封裝中心偏移之端子格柵之短線最小化 |
US8659141B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization using duplicate sets of terminals for wirebond assemblies without windows |
KR101894824B1 (ko) * | 2011-10-03 | 2018-09-04 | 인벤사스 코포레이션 | 윈도우 없는 와이어 본드 어셈블리를 위해 이중의 단자 세트를 이용하는 스터브 최소화 |
US8659142B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
US8629545B2 (en) | 2011-10-03 | 2014-01-14 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
JP5919872B2 (ja) * | 2012-02-21 | 2016-05-18 | 富士通株式会社 | 多層配線基板及び電子機器 |
US8787034B2 (en) | 2012-08-27 | 2014-07-22 | Invensas Corporation | Co-support system and microelectronic assembly |
US8848391B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support component and microelectronic assembly |
US9368477B2 (en) | 2012-08-27 | 2016-06-14 | Invensas Corporation | Co-support circuit panel and microelectronic packages |
US8848392B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support module and microelectronic assembly |
US9070423B2 (en) | 2013-06-11 | 2015-06-30 | Invensas Corporation | Single package dual channel memory with co-support |
US9123555B2 (en) | 2013-10-25 | 2015-09-01 | Invensas Corporation | Co-support for XFD packaging |
US9281296B2 (en) | 2014-07-31 | 2016-03-08 | Invensas Corporation | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design |
US9691437B2 (en) | 2014-09-25 | 2017-06-27 | Invensas Corporation | Compact microelectronic assembly having reduced spacing between controller and memory packages |
US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
US9679613B1 (en) | 2016-05-06 | 2017-06-13 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3370203A (en) * | 1965-07-19 | 1968-02-20 | United Aircraft Corp | Integrated circuit modules |
US5138438A (en) * | 1987-06-24 | 1992-08-11 | Akita Electronics Co. Ltd. | Lead connections means for stacked tab packaged IC chips |
JP3487524B2 (ja) * | 1994-12-20 | 2004-01-19 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
JPH10303562A (ja) | 1997-04-30 | 1998-11-13 | Toshiba Corp | プリント配線板 |
US6021048A (en) * | 1998-02-17 | 2000-02-01 | Smith; Gary W. | High speed memory module |
US6915566B2 (en) | 1999-03-01 | 2005-07-12 | Texas Instruments Incorporated | Method of fabricating flexible circuits for integrated circuit interconnections |
JP4002378B2 (ja) | 1999-12-27 | 2007-10-31 | エルピーダメモリ株式会社 | 電子回路 |
KR100355240B1 (ko) * | 2001-02-02 | 2002-10-11 | 삼성전자 주식회사 | 클럭 공유 양면 메모리 모듈 및 그 배선방법 |
US8125087B2 (en) * | 2001-02-20 | 2012-02-28 | Intel Corporation | High-density flip-chip interconnect |
JP3990578B2 (ja) | 2002-02-26 | 2007-10-17 | 京セラ株式会社 | 配線基板およびそれを用いた電子装置 |
US7071547B2 (en) * | 2002-09-11 | 2006-07-04 | Tessera, Inc. | Assemblies having stacked semiconductor chips and methods of making same |
JP2004128315A (ja) | 2002-10-04 | 2004-04-22 | Sanyo Electric Co Ltd | 半導体集積回路及びその配線方法 |
US7093076B2 (en) | 2002-12-12 | 2006-08-15 | Samsung Electronics, Co., Ltd. | Memory system having two-way ring topology and memory device and memory module for ring-topology memory system |
KR100688501B1 (ko) * | 2004-09-10 | 2007-03-02 | 삼성전자주식회사 | 미러링 구조를 갖는 스택 boc 패키지 및 이를 장착한양면 실장형 메모리 모듈 |
US7309914B2 (en) * | 2005-01-20 | 2007-12-18 | Staktek Group L.P. | Inverted CSP stacking system and method |
US7291907B2 (en) * | 2005-02-28 | 2007-11-06 | Infineon Technologies, Ag | Chip stack employing a flex circuit |
-
2005
- 2005-03-15 KR KR1020050021552A patent/KR100615606B1/ko active IP Right Grant
-
2006
- 2006-02-17 US US11/357,500 patent/US7390973B2/en not_active Expired - Fee Related
- 2006-03-15 JP JP2006071647A patent/JP5052801B2/ja not_active Expired - Fee Related
- 2006-03-15 TW TW095108720A patent/TWI303437B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100615606B1 (ko) | 2006-08-25 |
US7390973B2 (en) | 2008-06-24 |
JP5052801B2 (ja) | 2012-10-17 |
TWI303437B (en) | 2008-11-21 |
JP2006260755A (ja) | 2006-09-28 |
US20060207788A1 (en) | 2006-09-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |