TW200620320A - Memory module, memory unit, and hub with non-periodic clock and methods of using the same - Google Patents

Memory module, memory unit, and hub with non-periodic clock and methods of using the same

Info

Publication number
TW200620320A
TW200620320A TW094115446A TW94115446A TW200620320A TW 200620320 A TW200620320 A TW 200620320A TW 094115446 A TW094115446 A TW 094115446A TW 94115446 A TW94115446 A TW 94115446A TW 200620320 A TW200620320 A TW 200620320A
Authority
TW
Taiwan
Prior art keywords
hub
methods
periodic clock
same
memory module
Prior art date
Application number
TW094115446A
Other languages
English (en)
Inventor
You-Keun Han
Hui-Chong Shin
Seung-Jin Seo
Byung-Se So
Young-Man Ahn
Seung-Man Shin
Jung-Kuk Lee
Ho-Suk Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200620320A publication Critical patent/TW200620320A/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
TW094115446A 2004-08-31 2005-05-12 Memory module, memory unit, and hub with non-periodic clock and methods of using the same TW200620320A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020040068811A KR100551475B1 (ko) 2004-08-31 2004-08-31 비주기 클록옵션을 가지는 메모리 모듈과 모듈용 메모리칩 및 허브 칩
US11/029,008 US7606110B2 (en) 2004-08-31 2005-01-05 Memory module, memory unit, and hub with non-periodic clock and methods of using the same

Publications (1)

Publication Number Publication Date
TW200620320A true TW200620320A (en) 2006-06-16

Family

ID=36139561

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094115446A TW200620320A (en) 2004-08-31 2005-05-12 Memory module, memory unit, and hub with non-periodic clock and methods of using the same

Country Status (4)

Country Link
US (1) US7606110B2 (zh)
KR (1) KR100551475B1 (zh)
CN (1) CN1744228A (zh)
TW (1) TW200620320A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI768703B (zh) * 2020-09-07 2022-06-21 日商鎧俠股份有限公司 半導體積體電路及其試驗方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100588593B1 (ko) * 2005-06-09 2006-06-14 삼성전자주식회사 레지스터형 메모리 모듈 및 그 제어방법
KR100705335B1 (ko) 2005-10-31 2007-04-09 삼성전자주식회사 메모리 장치, 메모리 시스템 및 메모리 장치의 데이터입출력 방법
DE102006025133A1 (de) * 2006-05-30 2007-12-06 Infineon Technologies Ag Speicher- und Speicherkommunikationssystem
KR100871706B1 (ko) * 2007-03-13 2008-12-08 삼성전자주식회사 클럭 미러링 스킴을 구현하는 메모리 장치 및 이를장착하는 메모리 시스템
KR100863016B1 (ko) 2007-05-31 2008-10-13 주식회사 하이닉스반도체 동작 모드 설정 장치, 이를 포함하는 반도체 집적 회로 및반도체 집적 회로의 제어 방법
US8467486B2 (en) * 2007-12-14 2013-06-18 Mosaid Technologies Incorporated Memory controller with flexible data alignment to clock
US8781053B2 (en) * 2007-12-14 2014-07-15 Conversant Intellectual Property Management Incorporated Clock reproducing and timing method in a system having a plurality of devices
US8094504B2 (en) * 2008-01-04 2012-01-10 Integrated Device Technology Inc. Buffered DRAM
KR101203036B1 (ko) 2011-01-26 2012-11-20 윈본드 일렉트로닉스 코포레이션 메모리장치 및 그의 접근방법

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1246361B (it) * 1990-07-13 1994-11-17 Lonati Srl Macchina circolare per maglieria, calzetteria o simile, in particolareper l'esecuzione di lavorazioni con punti spugna.
US5359232A (en) * 1992-05-08 1994-10-25 Cyrix Corporation Clock multiplication circuit and method
US5311486A (en) * 1992-09-11 1994-05-10 Ltx Corporation Timing generation in an automatic electrical test system
US5485602A (en) * 1993-12-27 1996-01-16 Motorola, Inc. Integrated circuit having a control signal for identifying coinciding active edges of two clock signals
US5689690A (en) * 1995-09-25 1997-11-18 Credence Systems Corporation Timing signal generator
US5786732A (en) * 1995-10-24 1998-07-28 Vlsi Technology, Inc. Phase locked loop circuitry including a multiple frequency output voltage controlled oscillator circuit
JPH1011966A (ja) * 1996-06-27 1998-01-16 Mitsubishi Electric Corp 同期型半導体記憶装置および同期型メモリモジュール
US5796995A (en) * 1997-02-28 1998-08-18 Texas Instruments Incorporated Circuit and method for translating signals between clock domains in a microprocessor
JP2002082830A (ja) * 2000-02-14 2002-03-22 Mitsubishi Electric Corp インターフェイス回路
GB2370667B (en) * 2000-09-05 2003-02-12 Samsung Electronics Co Ltd Semiconductor memory device having altered clock frequency for address and/or command signals, and memory module and system having the same
US7000138B1 (en) * 2001-06-07 2006-02-14 Cirrus Logic, Inc Circuits and methods for power management in a processor-based system and systems using the same
DE10138883B4 (de) * 2001-08-08 2006-03-30 Infineon Technologies Ag Verfahren sowie Vorrichtung zur synchronen Signalübertragung zwischen Logik-/Speicherbausteinen
EP1302775A1 (en) * 2001-10-16 2003-04-16 Italtel s.p.a. A clock generation system for a prototyping apparatus
DE10249886B4 (de) * 2002-10-25 2005-02-10 Sp3D Chip Design Gmbh Verfahren und Vorrichtung zum Erzeugen eines Taktsignals mit vorbestimmten Taktsingaleigenschaften
US7177888B2 (en) * 2003-08-01 2007-02-13 Intel Corporation Programmable random bit source
US6958925B1 (en) * 2003-12-24 2005-10-25 Cypress Semiconductor Corporation Staggered compare architecture for content addressable memory (CAM) device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI768703B (zh) * 2020-09-07 2022-06-21 日商鎧俠股份有限公司 半導體積體電路及其試驗方法

Also Published As

Publication number Publication date
US20060044927A1 (en) 2006-03-02
CN1744228A (zh) 2006-03-08
KR100551475B1 (ko) 2006-02-14
US7606110B2 (en) 2009-10-20

Similar Documents

Publication Publication Date Title
TW200620320A (en) Memory module, memory unit, and hub with non-periodic clock and methods of using the same
WO2007149212A3 (en) Rfid device with first clock for data acquisition and/or calibration of second clock
TW200640146A (en) Data cleaning with an asynchronous reference clock
TW200625324A (en) Method of testing a memory module and hub of the memory module
GB0523073D0 (en) Distributed lock
WO2008076919A3 (en) System and method for computer network scheduling and communication
TW200618476A (en) Flip flop circuit & same with scan function
EP2028660A3 (en) Clock signal generator for generating stable clock signals, semiconductor memory device including the same, and methods of operating
ATE394714T1 (de) Elektronisches gerät und empfangsteuerungsverfahren für elektronisches gerät
TW200637149A (en) Clock converting device and testing device
TW200713268A (en) Data output device of semiconductor memory device
TW200943727A (en) Method and apparatus for generating or utilizing one or more cycle-swallowed clock signals
UA82957C2 (en) Two-component epoxy amine primer system and epoxy functional extended urethane
WO2006094884A3 (en) User interface for appointment scheduling system showing appointment solutions within a day.
WO2008027792A3 (en) Power line communication device and method with frequency shifted modem
WO2003073244A3 (en) Frequency divider
TW200601351A (en) Semiconductor memory device having test mode for data access time
TW200501586A (en) Delay locked loop (DLL) circuit and method for locking clock delay by using the same
TW200630018A (en) Rack bracket structure
EP4053520A4 (en) LIGHT RECEIVING ELEMENT, TELEMETRY MODULE AND ELECTRONIC INSTRUMENT
DE602006020778D1 (de) System und verfahren zur seriellen datenkommunikation
GB0325842D0 (en) Computer system with first and second clock synthesizers
ATE430320T1 (de) Adaptive speicherkalibration unter verwendung von bins
TW200715726A (en) Optical transceiver module and calibration method thereof
TW200746170A (en) Memory circuit