TW200617685A - Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment - Google Patents

Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment

Info

Publication number
TW200617685A
TW200617685A TW094124752A TW94124752A TW200617685A TW 200617685 A TW200617685 A TW 200617685A TW 094124752 A TW094124752 A TW 094124752A TW 94124752 A TW94124752 A TW 94124752A TW 200617685 A TW200617685 A TW 200617685A
Authority
TW
Taiwan
Prior art keywords
memory
command
primitives
bus operation
multiprocessor environment
Prior art date
Application number
TW094124752A
Other languages
English (en)
Other versions
TWI391826B (zh
Inventor
Michael Norman Day
Charles Ray Johns
Peichun Peter Liu
Thuong Quang Truong
Takeshi Yamazaki
Original Assignee
Sony Computer Entertainment Inc
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc, Ibm filed Critical Sony Computer Entertainment Inc
Publication of TW200617685A publication Critical patent/TW200617685A/zh
Application granted granted Critical
Publication of TWI391826B publication Critical patent/TWI391826B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
TW094124752A 2004-07-29 2005-07-21 在包含直接記憶體存取（ｄｍａ）裝置之多處理器系統中產生記憶體障礙的方法、設備和電腦程式產品 TWI391826B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/902,474 US7725618B2 (en) 2004-07-29 2004-07-29 Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment

Publications (2)

Publication Number Publication Date
TW200617685A true TW200617685A (en) 2006-06-01
TWI391826B TWI391826B (zh) 2013-04-01

Family

ID=35733704

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094124752A TWI391826B (zh) 2004-07-29 2005-07-21 在包含直接記憶體存取（ｄｍａ）裝置之多處理器系統中產生記憶體障礙的方法、設備和電腦程式產品

Country Status (9)

Country Link
US (1) US7725618B2 (zh)
EP (1) EP1782220B1 (zh)
JP (1) JP4678623B2 (zh)
KR (1) KR100866714B1 (zh)
CN (1) CN101052954B (zh)
AT (1) ATE403905T1 (zh)
DE (1) DE602005008747D1 (zh)
TW (1) TWI391826B (zh)
WO (1) WO2006040692A1 (zh)

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US9026744B2 (en) 2005-03-23 2015-05-05 Qualcomm Incorporated Enforcing strongly-ordered requests in a weakly-ordered processing

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US7243200B2 (en) 2004-07-15 2007-07-10 International Business Machines Corporation Establishing command order in an out of order DMA command queue
US7725618B2 (en) 2004-07-29 2010-05-25 International Business Machines Corporation Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment
DE102004046438B4 (de) * 2004-09-24 2006-07-06 Infineon Technologies Ag Vorrichtung zum Steuern des Zugriffs von Verarbeitungseinrichtungen auf Speicher in einem eingebetteten System
US7716387B2 (en) * 2005-07-14 2010-05-11 Canon Kabushiki Kaisha Memory control apparatus and method
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JP4446968B2 (ja) * 2006-02-22 2010-04-07 シャープ株式会社 データ処理装置
US7917676B2 (en) * 2006-03-10 2011-03-29 Qualcomm, Incorporated Efficient execution of memory barrier bus commands with order constrained memory accesses
US7610458B2 (en) * 2006-04-25 2009-10-27 International Business Machines Corporation Data processing system, processor and method of data processing that support memory access according to diverse memory models
US7454580B2 (en) * 2006-04-25 2008-11-18 International Business Machines Corporation Data processing system, processor and method of data processing that reduce store queue entry utilization for synchronizing operations
US7783817B2 (en) * 2006-08-31 2010-08-24 Qualcomm Incorporated Method and apparatus for conditional broadcast of barrier operations
US7941627B2 (en) * 2008-02-01 2011-05-10 International Business Machines Corporation Specialized memory move barrier operations
US8327101B2 (en) * 2008-02-01 2012-12-04 International Business Machines Corporation Cache management during asynchronous memory move operations
US8015380B2 (en) * 2008-02-01 2011-09-06 International Business Machines Corporation Launching multiple concurrent memory moves via a fully asynchronoous memory mover
US8275963B2 (en) * 2008-02-01 2012-09-25 International Business Machines Corporation Asynchronous memory move across physical nodes with dual-sided communication
US8095758B2 (en) * 2008-02-01 2012-01-10 International Business Machines Corporation Fully asynchronous memory mover
US8245004B2 (en) * 2008-02-01 2012-08-14 International Business Machines Corporation Mechanisms for communicating with an asynchronous memory mover to perform AMM operations
US8356151B2 (en) * 2008-02-01 2013-01-15 International Business Machines Corporation Reporting of partially performed memory move
US7991981B2 (en) * 2008-02-01 2011-08-02 International Business Machines Corporation Completion of asynchronous memory move in the presence of a barrier operation
JP5187038B2 (ja) * 2008-07-15 2013-04-24 セイコーエプソン株式会社 マルチプロセッサシステム及びそれを搭載した流体吐出装置
GB2469299B (en) * 2009-04-07 2011-02-16 Imagination Tech Ltd Ensuring consistency between a data cache and a main memory
US8352682B2 (en) * 2009-05-26 2013-01-08 Qualcomm Incorporated Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system
US8997103B2 (en) * 2009-09-25 2015-03-31 Nvidia Corporation N-way memory barrier operation coalescing
US8832403B2 (en) * 2009-11-13 2014-09-09 International Business Machines Corporation Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses
WO2012036954A2 (en) * 2010-09-15 2012-03-22 Rambus Inc. Scheduling amongst multiple processors
US20150033234A1 (en) * 2013-07-23 2015-01-29 Qualcomm Incorporated Providing queue barriers when unsupported by an i/o protocol or target device
CN108139903B (zh) * 2015-07-21 2019-11-15 安培计算有限责任公司 依dmb操作用加载/存储操作实施加载撷取/存储释放指令
KR101892357B1 (ko) * 2016-10-11 2018-08-27 한국과학기술원 실리콘 반도체를 기반으로 하는 광 빔 포밍 네트워크 칩
KR102262209B1 (ko) * 2018-02-09 2021-06-09 한양대학교 산학협력단 더미 입출력 요청을 이용한 배리어 명령 전달 방법 및 그 장치
DE102020127704A1 (de) 2019-10-29 2021-04-29 Nvidia Corporation Techniken zum effizienten transferieren von daten an einem prozessor
US11803380B2 (en) 2019-10-29 2023-10-31 Nvidia Corporation High performance synchronization mechanisms for coordinating operations on a computer system

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9026744B2 (en) 2005-03-23 2015-05-05 Qualcomm Incorporated Enforcing strongly-ordered requests in a weakly-ordered processing

Also Published As

Publication number Publication date
US20060026309A1 (en) 2006-02-02
JP2008508586A (ja) 2008-03-21
CN101052954A (zh) 2007-10-10
TWI391826B (zh) 2013-04-01
EP1782220B1 (en) 2008-08-06
US7725618B2 (en) 2010-05-25
DE602005008747D1 (de) 2008-09-18
JP4678623B2 (ja) 2011-04-27
EP1782220A1 (en) 2007-05-09
CN101052954B (zh) 2011-10-19
KR20070038518A (ko) 2007-04-10
WO2006040692A1 (en) 2006-04-20
ATE403905T1 (de) 2008-08-15
KR100866714B1 (ko) 2008-11-03

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